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Computer Organization &
Architecture (KCS 302)
UNIT – 1
SANJAY GOSWAMI, Asst. Prof.,
CS/IT Department, UCER, Prayagraj
Course Outcome (CO)
1.Studying of the internal bus structure, internal register organization
and instruction processing in the digital computer system.
2.Understanding the representation of integer and decimal numbers
and their arithmetic or logics in digital system with study of designing
ALU.
3.Detail study and analysis of Hardwired and Micro programmed
control unit implementation techniques with sound knowledge of
pipelining.
4.Detail study and analysis of different type of computer memories
and their implementations.
5.Understanding the different ways of communication between
peripheral devices, memories and standard I/O interfaces and
compare them.
Sanjay Goswami, UCER - Prayagraj

Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs.
The half adder circuit is designed to add two single bit binary number A and B.
It is the basic building block for addition of two single bit numbers. This circuit
has two outputs carry and sum.
Block Diagram Truth Table

Sum = A’B + AB’ Carry = AB
Logic Diagram

Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can
add two one-bit numbers A and B, and carry c. The full adder is a three input and
two output combinational circuit.
Block diagram Truth Table
Sum (S) = A xor B xor C

Carry Out (Co) = AB + BC + AC = (A xor B)Cin + AB

Logic Diagram
S = (X xor Y xor Z) and C = (X xor Y).Cin + AB

Logic Diagram 4-Bits Parallel Adder

4-Bits Parallel Adder Carry Propagation
Consider the full adder circuit shown above with corresponding truth table. If we define
two variables as carry generate Gi and carry propagate Pi then,
P i = Ai ⊕ B i
Gi = Ai Bi
The sum output and carry output can be expressed as
Si = Pi ⊕ Ci
C i +1 = Gi + Pi Ci
Where Gi is a carry generate which produces the carry when both Ai, Bi are one
regardless of the input carry. Pi is a carry propagate and it is associate with the
propagation of carry from Ci to Ci +1.
The carry output Boolean function of each stage in a 4 stage carry-Lookahead adder
can be expressed as C1 = G0 + P0 Cin
C2 = G1 + P1 C1
= G1 + P1 G0 + P1 P0 Cin
C3 = G2 + P2 C2
= G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 Cin
C4 = G3 + P3 C3
= G3 + P3 G2+ P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 Cin
Logic Diagram 4-Bits Lookhead Carry Generator

Logic Diagram 4-Bits Fast Adder
(Parallel Adder with Lookhead Carry Generator)

4-Bits Adder / Subtractor
The Arithmetic micro-operations like addition and subtraction can be

combined into one common circuit by including an exclusive-OR gate with
each full adder. The block diagram for a 4-bit adder-subtractor circuit can be
represented as:

Working
 When the mode input (M) is at a low logic, i.e. '0', the circuit act as an
adder and when the mode input is at a high logic, i.e. '1', the circuit
act as a subtractor.
 The exclusive-OR gate connected in series receives input M and one
of the inputs B.
 When M is at a low logic, we have B⊕0 = B.
The full-adders receive the value of B, the input carry is 0, and the
circuit performs A plus B.
 When M is at a high logic, we have B⊕1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input
carry. The circuit performs the operation A plus the 2's complement of
B.
Binary Incrementer
It adds 1 binary value to the existing binary value stored in the register or
in other words we can simply say that it increases the value stored in the
register by 1. For any n-bit binary incrementer ,‘n’ refers to the storage
capacity of the register which needs to be incremented by 1. So we
require ‘n’ number of half adders .

Working
 The half adders are connected one after the other , as it has 2 inputs
and 2 outputs , so for the LSB ( least significant bit) half adder or the
right most half adder is given 1 as direct input( first input) and A0
which is the first bit of the register (second input) , so we get the two
output : sum (S0) and carry (C).
 The carry(C) from previous half adder is propagated to the next half
adder, so the carry output of the previous half adder becomes the
input of the next higher order half adder.
 So considering the case for 4 half adders the circuit gets in total 4 bits
(A0, A1, A2, A3), 1 is added and we get an incremented output.

Binary Drecrementer
It subtracts 1 binary value from the existing binary value stored in the
register or in other words we can simply say that it decreases the existing
value stored in the register by 1. For any n- bit binary decrementer, needs
to be decremented by 1 (using 2’s complement such as for 4-bits, 2’s
complement 0001 is 1111). So we require ‘n’ number of full adders.

Working
 It consists of 4 full adders, connected one after the other. Each full
adder has 3 inputs (carry input, 1, A) and 2 outputs (carry output and
S)
 A full adder basic consist of 2 half adders and an OR gate.
 The carry(C) from previous full adder is propagated to the next full
adder. So carry output from one full adder becomes one of the three
input of the next full adder.
 It follows the concept of 2’s complement, so we take 1 as input in all
4 full adder as seen from the above diagram.
 So we add 1111 in order to subtract 1.

IEEE 754 Format (IEEE – Institute of
Electrical and Electronics Engineers)
Floating Point Numbers

Parts- (+/-)mantissa , (+/-)exponent
923.456 x 1021
normalized mantissa
9.2345 x 10 23
0.8762 x 10 21 (not normalize)
8.762 x 1020 (normalize)

Examples: (in Binary System)
11.101 x 220 (not normalize)
0.1001 x 220 (not normalize)

0.001001 x 2 20 (not normalize)

Example: Represents 11.25 into IEEE 754 32-bits
Floating Point Formats.
Sign (S) Exponent (E) Fractional Mantissa (F)

1 bit 8 bits 23 bits
IEEE 32-bit Format

1. The Sign bit represents the mantissa sign, is either 0 (+
ve no.) or 1 (- ve no.).
2. The fractional part (F) of the mantissa.
3. The non-fractional part is not stored, and assumed to be 1
(i.e. normalized), so the actual mantissa is (1.F)2.
4. The exponent is stored in biased 127. Hence E, when
interpreted as an unsigned binary number, is the (exponent
+ 127).
Sanjay Goswami, UCER - Prayagraj 19
Now 11.25 in binary is
= 1011.01 or 1.01101 x 23
then exponent is
= (127 + 3) = 130 in binary 10000010
So IEEE 32-bits format is
= 0 10000010 01101000000000000000000
Similarly if -11.25 =
1 10000010 01101000000000000000000
IEEE 754 64-bit Format
(exponent is 1023 biased)
Sign (S) Exponent (E) Fractional Mantissa (F)
1 bit 11 bits 52 bits
n-1
Note: biasedvalue = 2 – 1
(here, n- nos. of bit in exponent part)

IEEE 754 format for floating point numbers
representation 32-bits
Example : convert 1.1101 x 210 32-bits IEEE format.
Biased Exponent = 10 +127=137

10001001
0 10001001 110100000000000…23bits
Example : -1.1101 x 210
1 10001001 110100000000000…23bits
Example : -1.1101 x 2-10
biased exponent = -10+127 =117
01110101
1 01110101 11010000000000000…23bits
Example: 25.25 in IEEE 32 bits format.
25.25 = 11001.11001 in binary

Normalized it = 1.100111001 x 24
Biased exponent = 4 + 127 = 131
131 =10000011 in binary
Ans 0 10000011 10011100100000…23bits
IEEE 754 format for 64 bits

Sign(1) exponent (11)[biased 1023]
decimal part of normalized mantissa (52)
as in above example = 1.100111001 x24
exponent biased = 4+1023 = 1027
10000000011 in binary
Ans 0 10000000011 Sanjay
1001110010000…
Goswami, UCER - Prayagraj
52bits
Hardware Multiplication Algorithm

Hardware’s Used in Multiplication Algorithm

Flowchart for Hardware Multiplication Algorithm

Example for Hardware Multiplication Algorithm

Booth’s Multiplication Algorithm
 Multiply negative numbers in 2’s complement form

Flowchart for Booth’s Multiplication Algorithm

Example for Booth’s Multiplication Algorithm

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Computer Organization &

Architecture (KCS 302)

Sanjay Goswami, UCER - Prayagraj

Block Diagram Truth Table

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Block diagram Truth Table

Sum (S) = A xor B xor C

Sanjay Goswami, UCER - Prayagraj

S = (X xor Y xor Z) and C = (X xor Y).Cin + AB

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

The Arithmetic micro-operations like addition and subtraction can be

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Floating Point Numbers

0.8762 x 10 21 (not normalize)

8.762 x 1020 (normalize)

0.1001 x 220 (not normalize)

0.001001 x 2 20 (not normalize)

1.001 x 217 (normalize)

Sanjay Goswami, UCER - Prayagraj

Sign (S) Exponent (E) Fractional Mantissa (F)

IEEE 32-bit Format

Sanjay Goswami, UCER - Prayagraj 21

Example : convert 1.1101 x 210 32-bits IEEE format.

Biased Exponent = 10 +127=137

25.25 = 11001.11001 in binary

IEEE 754 format for 64 bits

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

Sanjay Goswami, UCER - Prayagraj

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