LogicDesign 8 1
LogicDesign 8 1
Ch9
note 6
Topics
¨ State diagram
¨ State transition table
¨ State assignment
¨ Next state and Output functions
IN D Q D Q D Q
CLK
1 0 1 1
1
1
000 1 010 101 0 111
0
0 0 0 1 0
001 011
Output values shown 0
within state node
0 0
0 1 0 1
100 100 0
101
0 1 0
1
1 1 1
1
010 110 010 110
0 1 1 0 0 1 0
0 0
001 1 111 011 001 1 111 011 1
1
0 0
IN
OUT
D Q D Q D Q
CLK
NS1 = I
NS2 = PS1 + PS2 × I
NS3 = PS2
O = PS3
000 Reset
0 1
1
010 110
0 1 1 0
¨ An alternative implementation with S/R FFs 001 1 111
0
011
1
0
R = Reset
Reset S = PS2 × I
NS1 = I
NS2 = PS1
R S R S R S NS3 = PS2
In D Q D Q D Q Out O = PS3
CLK
¨ The set input (S) does the median filter function by making
the next state 111 whenever the input is 1 and PS2 is 1 (1
input to state x1x)
S3' S4'
0,1/0 0/0 1/0
Reset
No need to minimize states!
4 FFs for the shift register
0/0 1/0 è can express up to 16 states
0/0 1/0 0/0 0/0 0/1 0/0 1/0 0/0 1/0 1/0
1/0 1/0 1/0 0/1 1/0 0/0
1010
Initial realization
Inputs Output
Outputs
Function ¨ Block Diagram for
Next State Synchronous Mealy Machine
Function
State
ROM Registers
A0 D0 ¨ ROM-based Realization
Inputs Outputs
An-1 Dk-1 ¤ Inputs & Current State form the
An Dk address
An+m-1 Dk+m-1 ¤ ROM data bits form the Outputs
& Next State
State
17 Digital Logic Design
000
S0
0/1 1/0
0 0 0 1 1 0 1 1
0 0 1 0 0 1 0 0 1
0 0 1 1 0 1 0 1 CLK 9 CLK 15
QD Z
0 1 0 0 1 1 0 1 175 14
1 X converter ROM QD
0 1 0 1 0 0 0 0 X Z 13 D 10
0 C QC
D2 12 11
0 1 1 0 1 0 0 0 Q2
5 QC
Q1 D1 B
0 1 1 1 X X X X 4 A QB 7
Q0 D0
QB 6
1 0 0 0 0 0 1 0
2
1 0 0 1 0 1 0 0 1 QA
1 CLR 3
0 QA
1 0 1 0 1 1 0 0 \Reset
1 0 1 1 1 1 0 1
1 1 0 0 0 1 1 0
1 1 0 1 1 0 0 0
1 1 1 0 X X X X
1 1 1 1 X X X X Excess-3 synchronous Mealy ROM-based
implementation
18 Digital Logic Design
PLA-based design
S0 S1 S2
S4 S6 S5 S3
DQ
Q
Seq
N
Q1
DQ
Seq
D
Open
DQ
Com
Reset
Q0
DQ
Seq
N
Q1
DQ
Seq
D
OPEN Open
DQ
Seq
Reset
¨ Combinational logic
elements (SoP)
¨ Sequential logic
elements (D-FFs)
¨ Up to 10 outputs
¨ Up to 10 FFs
¨ Up to 22 inputs
OE