The S-R Latch (Quickstart Tutorial)
October 27, 2022 by Omar Muñoz Urias
The S-R latch is a key circuit in digital storage units. In this tutorial, you
will learn how it works, its truth table, and how to build one with
different logic gates.
S-R Latch Symbol
What is an S-R Latch?
Before starting with the S-R latch you need to know what a latch is. A
latch is an asynchronous circuit (it doesn’t require a clock signal to
work), and it has two stable states, HIGH (“1”) and LOW (“0”), that can
be used for storing binary data. Many sequential circuits and larger
storage devices, such as shift registers, use latches as their principal
building block.
The simplest latch is the Set-Reset (S-R) latch. You can build one by
connecting two NOR gates with a cross-feedback loop.
S-R Latch with NOR gates
This feedback path is crucial to storing one bit of data as long as the
circuit is powered. In this circuit, the upper gate has the S input and
the main output Q, while the lower gate has the R input and the
inverted output Q̅ .
How does the S-R Latch work?
First of all, let’s define the truth table of the S-R latch:
Input S Input R Output Q
0 0 Previous State
0 1 0
1 0 1
1 1 0 (Invalid)
S-R Latch truth table
Now, let’s analyze how the S-R latch works using its truth table and its
circuit with NOR gates. Remember that the NOR gate only gives “1”
when both inputs are “0”, with any other input combination the output
is “0”.
You can see in the truth table that when both inputs S and R are equal
to “0”, the output Q remains the same as it was. This is the memory
function of the S-R latch because it saves the previous value. Suppose
the Q output is “1” in the present state. If you now place both inputs in
“0”, then the output will remain “1” as follows:
Then, how would you “Reset” the Q output to “0”? Well, as you can see
in the truth table, you need a “1” in the R input and a “0” in the S
input.
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But, if you want to “Set” a “1” in the Q output just follow the truth
table and place a “1” in the S input and a “0” in the R input.
Finally, the S and R inputs should never be “1” at the same time
because the NOR gate only gives “1” when both of its inputs are “0”,
but if one input is “1”, then the output will be “0”. As a result, if S and R
are “1”, both latches’ outputs will be “0” at the same time, something
that violates this latch’s working principle.
SR-LATCH WITH NAND GA
The D Latch (Quickstart Tutorial)
December 13, 2022 by Omar Muñoz Urias
The D Latch is a logic circuit most frequently used for storing data in
digital systems. It is based on the S-R latch, but it doesn’t have an
“undefined” or “invalid” state problem. In this tutorial, you will learn
how it works, its truth table, and how to build one with logic gates.
D Latch Symbol
What is a D Latch?
A D latch can store a bit value, either 1 or 0. When its Enable pin is
HIGH, the value on the D pin will be stored on the Q output. It builds
upon the design of the S-R latch, with a few added logic gates. You
can see a D Latch circuit based on the S-R latch built with NAND
gates below:
D Latch
Circuit
The inverter on the input makes sure the S and the R inputs are always
opposites, to avoid the invalid state of both being 1. The two NAND
gates create a new input, E (Enable), that lets you control when you
want to change the output to whatever is on the D input.
This means that the output Q can only change when the enable signal
is 1. If it’s 0, the output is unaffected by any changes on D.
You can also build a D Latch with AND and NOR gates as follows:
The D Latch can also be used to introduce delay in timing circuits, as a
buffer, or for sampling data at specific intervals.
What’s the Difference Between Latch and
Flip Flop?
The terms latch and flip flop are sometimes incorrectly used as
synonyms since both can store a bit (1 or 0) at their outputs.
While a latch can change its output at any time as long as it’s enabled,
a flip flop is an edge-triggered device that needs a clock transition to
change its output.
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To build a D Flip Flop, you’ll need two D latches, like this:
How Does the D Latch Work?
Since the output Q only changes when the E input is 1, you’ll get the
following truth table:
E D Q Description
Memory
0 X Q
(no change)
1 0 0 Reset Q to 0
1 1 1 Set Q to 1
D Latch Truth Table
In the first row of the truth table, the E input is 0. That means the latch
is not enabled, so nothing happens. The Q output keeps whatever
value it had. No matter what value the D input has, the Q output won’t
change, it will keep its value as it is. This is how this circuit
“remembers” a bit.
Take a look at the next two rows. Here the E input is 1, so the latch is
enabled. This means that if the D input is 0, the Q output will be reset
to 0. If the D input is 1, the Q output will be set to 1.
Analyzing the Circuit
You can build a D Latch circuit by adding three logic gates to the S-R
latch circuit. In the next image, you can see the D Latch circuit’s bit
path when it is enabled and it has 0 on the D input.
he JK Flip Flop
The JK Flip-flop is similar to the SR Flip-flop but there is no change in state when the J
and K inputs are both LOW
Unlike the JK Flip-flop, the basic S-R NAND flip-flop circuit has many
advantages and uses in sequential logic circuits but it suffers from two basic
switching problems.
1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
2. if Set or Reset change state while the enable (EN) input is high the
correct latching action may not occur
Then to overcome these two fundamental design problems with the SR flip-
flop design, the JK flip Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs and
is considered to be a universal flip-flop circuit. The two inputs labelled “J” and
“K” are not shortened abbreviated letters of other words, such as “S” for Set
and “R” for Reset, but are themselves autonomous letters chosen by its
inventor Jack Kilby to distinguish the flip-flop design from other types.
The sequential operation of the JK flip flop is exactly the same as for the
previous SR flip-flop with the same “Set” and “Reset” inputs. The difference
this time is that the “JK flip flop” has no invalid or forbidden input states of the
SR Latch even when S and R are both at logic “1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can occur
when both inputs S and R are equal to logic level “1”. Due to this additional
clocked input, a JK flip-flop has four possible input combinations, “logic 1”,
“logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to
that of an SR Bistable Latch as seen in the previous tutorial except for the
addition of a clock input.
The Basic JK Flip-flop
Both the S and the R inputs of the previous SR bistable have now been
replaced by two inputs called the J and K inputs, respectively after its inventor
Jack Kilby. Then this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced
by two 3-input NAND gates with the third input of each gate connected to the
outputs at Q and Q. This cross coupling of the SR flip-flop allows the
previously invalid condition of S = “1” and R = “1” state to be used to produce
a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through
the lower NAND gate. If the circuit is “RESET” the K input is inhibited by the
“0” status of Q through the upper NAND gate. As Q and Q are always different
we can use them to control the input. When both inputs J and K are equal to
logic “1”, the JK flip flop toggles as shown in the following truth table.
