System Verilog Data Type

wire and reg:

The wire nets act like real wires in circuits. The reg type holds their values until
another value is put on them, just like a register hardware component. The
declarations for wire and reg signals are inside a module but outside any initial
or always block.

• reg is x unknown, wire is z.

• An integer declares one or more variables of type integer. These variables
can hold values ranging from -2^31 to (2^31)-1.
• The real variables are stored as 64-bit quantities, and store the real values.
Real numbers can be specified in either decimal notation (for example,
14.72) or in scientific notation (for example, 39e8).
Logic:

• As the difference between reg and wire types often causes confusion, a new
binary data type was introduced in System-Verilog.

• The logic type was introduced as a replacement for both the reg and wire
types. As the logic type combines the characteristics of the reg and wire
types, we can use it in pretty much any part of our System-Verilog code.

• This is in contrast to the reg and wire types which can only be used in
procedural blocks and continuous assignment respectively. All of this
makes the logic type much more flexible. As a result, it is easier to
understand and work with.

• As a general rule, we should use the logic type for any binary signal in our
System-Verilog design. The only exception to this is when we want to drive
a signal from more than one source. As it's illegal to drive a logic type from
more than one source, we would have to use a wire type for this.
 System-Verilog bit Type

• bit type in either procedural blocks or in the continuous assignment.

• Here, the logic type, the bit type uses 2 states rather than 4.
• However, the bit type uses half the amount of memory that the logic type
requires as it has less states. This can speed up the execution time of our
simulations.
Verilog Integer Type
• The code snippet below shows how we declare and assign an integer type in
System-Verilog:

•
System-Verilog int Type
• By default, the int type is a 32 bit signed number which we can use to model
whole numbers in System-Verilog.
• We should generally use the int type instead of the integer type within our
System-Verilog testbenches.

System-Verilog byte Type

• The System-Verilog byte type is an 8 bit data type which we can use to
model whole numbers.
• signed byte type, only accept values from -127 to 127.
• unsigned byte type, only accept values from 0 to 255.
• Like the int type, the byte type only uses 2 states. As a result of this, we
should avoid using this type in System-Verilog based designs.
• However, we should use the byte type in our testbenches as it uses less
memory and can reduce execution times.

System-Verilog short-int type:

• The System-Verilog short-int type is a 16-bit data type which we can use to
model whole numbers.

String
Event:
• An identifier declared as an event data type is called a named event.
• Named event is a data type which has no storage.
• The event is used to convey an important message between the classes.
• The message could be that generated completed the process of sending all
the stimuli.
• message something like this could be send between the classes with the help
of an event.
• To trigger an event, we used -> operator.
• To sense an event, used this two operator edge sensitive_blocking @(),
level_sensitive_non-blocking wait().
• System-Verilog event is used to synchronize between two or more processes
or threads.

Triggered:
• The "triggered" event property evaluates to true if the given event has been
triggered in the current time-step and false otherwise.
• If event_identifier is null, then the triggered event property evaluates to
false.
• an event trigger shall unblock the waiting process whether the wait executes
before or at the same simulation time as the trigger operation.
• In the following example, event "e" is triggered at time 20,40,60,80 . So the
Value of "e.triggered" should be TRUE at time 20,40,60,80 and FALSE at
rest of the time.
Wait():

• Named Event triggering occurrence can also be recognized by using the

event control wait().
• Wait() statement gets blocked until it evaluates to TRUE.

Race Condition:
• For a trigger to unblock a process waiting on an event, the waiting process
must execute the @ statement before the triggering process executes the
trigger operator, ->. If the trigger executes first, then the waiting process
remains blocked.
• event_name.triggered statement, an event trigger shall unblock the waiting
process whether the wait executes before or at the same simulation time as
the trigger operation.
• event_name.triggered statement, an event trigger shall unblock the waiting
process whether the wait executes before or at the same simulation time as
the trigger operation.
• The triggered event property, thus, helps eliminate a common race condition
that occurs when both the trigger and the wait (using @) happen at the same
time.
• A process that blocks waiting for an event might or might not unblock,
depending on the execution order of the waiting and triggering processes
(race condition).
• However, a process that waits on the triggered state always unblocks,
regardless of the order of execution of the wait and trigger operations.

Nonblocking Event Trigger:

 System Verilog Array
An array is a group of variables having the same data type. It can be
accessed using an index value.
Types of an array:
1) Fixed-size array in System-Verilog.
2) Single dimensional array.
3) Multidimensional array.
a) Two-dimensional array.
b) Three-dimensional array
4)Packed and Unpacked array in System-Verilog.
5)Dynamic array in System-Verilog.
7)Associative array in System-Verilog.
Example:
int array1 [6] //fixed size single dimension array
int array2 [5:0] //fixed size single dimension array
int array3 [3:0][2:0] //fixed size multi dimension array
bit [7:0] array4[2:0] //unpacked array declaration
bit [2:0][7:0] array5 //packed array declaration
bit [2:0][7:0] array6 [3] //mixed packed and unpacked array

Fixed size array

In fixed size array, array size will be constant throughout the simulation,
Once the array is declared no need to create it.
By default, the array will be initialized with value ‘0’.
Fixed Size Array Example

This example shows array declaration and array manipulation using

for and foreach loop.
System-Verilog Dynamic Array
Dynamic Array:

A dynamic array is one dimension of an unpacked array whose size can

be set or changed at run-time. Dynamic array is Declared using an empty
word subscript [ ].

The space for a dynamic array doesn’t exist until the array is explicitly
created at run-time, space is allocated when new [number] is called. the
number indicates the number of space/elements to be allocated.

Dynamic array Syntax

 Associative Arrays

As we saw, dynamic arrays are useful at dealing with a collection of variables

(contiguous) whose number can change dynamically (resize, allocate new
elements, etc.). In contrast, an associative array is kind of a lookup table. The
memory is not allocated until it is used, and the data are stored at the so-called
indices.

You look up data by using an index which acts like a key to that location. This is
like a tag memory in a cache subsystem where the cache lines are sparsely located
at indices which are known as tags. You store data at a given key (index) and look
it up using the same key. This way you can take advantage of limited sparse
memory. When the size of the collection of variables is unknown or the data space
is sparse, an associative array is a better option over a dynamic array.

Array elements in associative arrays are allocated dynamically. Associative array

elements are unpacked. The associative array maintains the entries that have been
assigned values and their relative order according to the index data type. “real” or
“short-real” data types, or a type containing a real or short real, is an illegal index
type.

Here is the syntax:

data_type array_id [index_type];

where data_type is the data type of the array elements. array_id is the name ofthe
array. And index_type is the data type used as the index (or key).Some examples
of associative arrays. We will see each one in detail:
num(), first() and last() method’s
Queues

System-Verilog provides several data structures to store a collection of objects. A

queue is such a data structure. A queue is a variable-size, ordered collection of
homogeneous (same type) elements. A queue supports access to all its elements as
well as insertion and removal at the beginning or the end of the queue.

The 0th position represents the first and $ represents the last element of the queue.
A queue is actually a one-dimensional unpacked array. Queues are declared using
the same syntax as unpacked arrays. The only difference is that a queue can grow
and shrink automatically. Thus, like arrays, queues can be manipulated using the
indexing, concatenation, slicing operator syntax, and equality operators. The
difference between an array and a queue is that an array is a non-variable size
collection of the same type of variables, while a queue is a variable size ordered
collection of homogeneous objects.

Queues can be used to model last-in, first-out (LIFO) or first-in, first-out

(FIFO)buffers. A queue can have variable length, including a length of 0. This
makes a queue an ideal candidate as a storage element that can shrink or grow as
elements are deleted or added to it without fixing an artificial upper limit on its size
as a regular fixed size array.

Queues are declared using the same syntax as unpacked arrays but specifying“$”
as the array size.

Here’s the syntax:

module tb;
int arr[$];
initial begin
arr ={1,2,3};
$display("arr : %op", arr);
end
endmodule