UNIT 5

FIELD EFFECT TRANSISTOR

UNIT – V
Field Effect Transistors (FET): JFET Construction, Principle of Operation, Pinch-Off Voltage,
Volt-Ampere Characteristics, Comparison of BJT and FET, Biasing of FET, FET as Voltage
Variable Resistor.
Introduction to MOSFET, MOSFET Characteristics in Enhancement and Depletion mode.
FET Amplifiers: Small Signal Model, Analysis of JFET Amplifiers, Analysis of CS, CD, CG JFET
Amplifiers. Basic concepts of MOS Amplifiers.

5.1 INTRODUCTION

1. The Field effect transistor is abbreviated as FET, it is an another semiconductor device like a
BJT which can be used as an amplifier or switch.
2. The Field effect transistor is a voltage operated device. Whereas Bipolar junction transistor is a
current controlled device. Unlike BJT a FET requires virtually no input current.
3. This gives it an extremely high input resistance, which is its most important advantage over a
bipolar transistor.
4. FET is also a three terminal device, labeled as source, drain and gate.
5. The source can be viewed as BJT’s emitter, the drain as collector, and the gate as the counter part
of the base.
6. The material that connects the source to drain is referred to as the channel.

7. FET operation depends only on the flow of majority carriers ,therefore they are called uni polar
devices. BJT operation depends on both minority and majority carriers.

8. As FET has conduction through only majority carriers it is less noisy than BJT.

9. FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less
space than BJTs.

10. FET amplifiers have low gain bandwidth product due to the junction capacitive effects and
produce more signal distortion except for small signal operation.

11. The performance of FET is relatively unaffected by ambient temperature changes. As it has a
negative temperature coefficient at high current levels, it prevents the FET from thermal
breakdown. The BJT has a positive temperature coefficient at high current levels which leads to
thermal breakdown.
5.2 CLASSIFICATION OF FET:

There are two major categories of field effect transistors:

1. Junction Field Effect Transistors

2. MOSFETs

These are further sub divided in to P- channel and N-channel devices.

MOSFETs are further classified in to two types Depletion MOSFETs and Enhancement MOSFETs
When the channel is of N-type the JFET is referred to as an N-channel JFET ,when the channel is of
P-type the JFET is referred to as P-channel JFET.

The schematic symbols for the P-channel and N-channel JFETs are shown in the figure.

Fig 5.1 schematic symbols for the P-channel and N-channel JFET
5.3 CONSTRUCTION AND OPERATION OF N- CHANNEL FET

If the gate is an N-type material, the channel must be a P-type material.

CONSTRUCTION OF N-CHANNEL JFET

Fig 5.2 Construction of N-Channel JFET

A piece of N- type material, referred to as channel has two smaller pieces of P-type material attached
to its sides, forming PN junctions. The channel ends are designated as the drain and source and the
two pieces of P-type material are connected together and their terminal is called the gate. Since this
channel is in the N-type bar, the FET is known as N-channel JFET.
OPERATION OF N-CHANNEL JFET:-

The overall operation of the JFET is based on varying the width of the channel to control the drain
current. A piece of N type material referred to as the channel, has two smaller pieces of P type material
attached to its sites, farming PN –Junctions. The channel ends are designated as drain and the source.
With the gate terminal not connected and the potential applied positive to the drain and negative to the
source a drain current Id flows. When the gate is biased negative with respective to the source the PN
junctions are reverse biased and depletion regions are formed. The channel is more lightly doped than
the P type gate , so the depletion regions penetrate deeply into the channel. Since depletion region is a
region depleted of charge carriers it behaves as an Insulator. The result is that the channel is narrowed.
Its resistance is increased and Id is reduced. When the negative gate bias voltage is further increased, the
depletion regions meet at the center and Id is cut off completely.

There are two ways to control the channel width

1. By varying the value of Vgs

2. And by Varying the value of Vds holding Vgs constant
1 By varying the value of Vgs :-

We can vary the width of the channel and in turn vary the amount of drain current.
This can be done by varying the value of Vgs. This point is illustrated in the fig below. So channel is
of N type and gate is of P type that constitutes a PN junction. This PN junction is always reverse
biased in JFET operation. The reverse bias is applied by a battery voltage Vgs connected between
the gate and the source terminal i.e positive terminal of the battery is connected to the source and
negative terminal to gate.

When a PN junction is reverse biased the electrons and holes diffuse across junction by leaving
immobile ions on the N and P sides , the region containing these immobile ions is known as
depletion regions.
1) If both P and N regions are heavily doped then the depletion region extends symmetrically on
both sides.
2) But in N channel FET P region is lightly doped than N type thus depletion region extends
more in N region than P region.
3) So when no Vds is applied the depletion region is symmetrical and the conductivity becomes
Zero. Since there are no mobile carriers in the junction.
4) As the reverse bias voltage is increases the thickness of the depletion region also increases. i.e.
the effective channel width decreases .
5) By varying the value of Vgs we can vary the width of the channel.

2 Varying the value of Vds holding Vgs constant :-

1) When no voltage is applied to the gate i.e. Vgs=0 , Vds is applied between source and drain the
electrons will flow from source to drain through the channel constituting drain current Id .
2) With Vgs= 0 for Id= 0 the channel between the gate junctions is entirely open .In response to a
small applied voltage Vds , the entire bar acts as a simple semi conductor resistor and the current
Id increases linearly with Vds .
3) The channel resistances are represented as rd and rs as shown in the fig.
 4) This increasing drain current Id produces a voltage drop across rd which reverse biases the gate
to source junction,(rd> rs) .Thus the depletion region is formed which is not symmetrical .
5) The depletion region i.e. developed penetrates deeper in to the channel near drain and less
towards source because Vrd >> Vrs. So reverse bias is higher near drain than at source.
6) As a result growing depletion region reduces the effective width of the channel. Eventually a
voltage Vds is reached at which the channel is pinched off. This is the voltage where the current
Id begins to level off and approach a constant value.
7) So, by varying the value of Vds we can vary the width of the channel holding Vgs constant.

When both Vgs and Vds is applied:-

It is of course in principle not possible for the channel to close Completely and there by reduce the
current Id to Zero for, if such indeed, could be the case the gate voltage Vgs is applied in the direction to
provide additional reverse bias
 1) When voltage is applied between the drain and source with a battery Vdd, the electrons flow
from source to drain through the narrow channel existing between the depletion regions. This
constitutes the drain current Id, its conventional direction is from drain to source.
2) The value of drain current is maximum when no external voltage is applied between gate and
source and is designated by Idss.

3) When Vgs is increased beyond Zero the depletion regions are widened. This reduces the
effective width of the channel and therefore controls the flow of drain current through the
channel.
4) When Vgs is further increased a stage is reached at which to depletion regions touch each other
that means the entire channel is closed with depletion region. This reduces the drain current to
Zero.

CHARACTERISTICS OF N-CHANNEL JFET

The family of curves that shows the relation between current and voltage are known as
characteristic curves.

There are two important characteristics of a JFET.

1) Drain or VI Characteristics
2) Transfer characteristics

1. Drain Characteristics:-
Drain characteristics shows the relation between the drain to source voltage Vds
and drain current Id. In order to explain typical drain characteristics let us consider the curve with
Vgs= 0.V.
 1) When Vds is applied and it is increasing the drain current ID also increases linearly up to knee
point.
2) This shows that FET behaves like an ordinary resistor. This region is called as ohmic region.
3) ID increases with increase in drain to source voltage. Here the drain current is increased slowly
as compared to ohmic region.

4) It is because of the fact that there is an increase in VDS . This in turn increases the reverse
bias voltage across the gate source junction .As a result of this depletion region grows in size
thereby reducing the effective width of the channel.

5) All the drain to source voltage corresponding to point the channel width is reduced to a
minimum value and is known as pinch off.

5) The drain to source voltage at which channel pinch off occurs is called pinch off voltage(Vp).

PINCH OFF Region:-

1) This is the region shown by the curve as saturation region.

2) It is also called as saturation region or constant current region. Because of the channel is
occupied with depletion region , the depletion region is more towards the drain and less
towards the source, so the channel is limited, with this only limited number of carriers are
only allowed to cross this channel from source drain causing a current that is constant in this
region. To use FET as an amplifier it is operated in this saturation region.
3) In this drain current remains constant at its maximum value IDSS.

4) The drain current in the pinch off region depends upon the gate to source voltage and
is given by the relation

2
Id =Idss [1-Vgs/Vp] This is known as shockley’s relation.
 BREAKDOWN REGION:-

1) The region is shown by the curve. In this region, the drain current increases rapidly as the
drain to source voltage is increased.
2) It is because of the gate to source junction due to avalanche effect.
3) The avalanche break down occurs at progressively lower value of VDS because the reverse
bias gate voltage adds to the drain voltage thereby increasing effective voltage across the
gate junction.This causes

1. The maximum saturation drain current is smaller

2. The ohmic region portion decreased.
4) It is important to note that the maximum voltage VDS which can be applied to FET is
the lowest voltage which causes available break down.

2. TRANSFER CHARACTERISTICS:-

These curves shows the relationship between drain current ID and gate to source voltage VGS
for different values of VDS.
1) First adjust the drain to source voltage to some suitable value , then increase the gate to
source voltage in small suitable value.
2) Plot the graph between gate to source voltage along the horizontal axis and current ID on
the vertical axis. We shall obtain a curve like this.

3) As we know that if Vgs is more negative curves drain current to reduce . where Vgs is made
sufficiently negative, Id is reduced to zero. This is caused by the widening of the depletion
region to a point where it is completely closes the channel. The value of Vgs at the cutoff
point is designed as Vgsoff
The upper end of the curve as shown by the drain current value is equal to Idss that is when Vgs = 0 the
drain current is maximum.
 4) While the lower end is indicated by a voltage equal to Vgsoff
5) If Vgs continuously increasing , the channel width is reduced , then Id =0
6) It may be noted that curve is part of the parabola; it may be expressed
2
as Id=Idss[1-Vgs/Vgsoff]

DIFFERENCE BETWEEN Vp AND Vgsoff –

Vp is the value of Vgs that causes the JFET to become constant current component, It is
measured at Vgs =0V and has a constant drain current of Id =Idss .Where Vgsoff is the value of Vgs that
reduces Id to approximately zero.

Why the gate to source junction of a JFET be always reverse biased ?

The gate to source junction of a JFET is never allowed to become forward biased because
the gate material is not designed to handle any significant amount of current. If the junction is allowed to
become forward biased, current is generated through the gate material. This current may destroy the
component.

There is one more important characteristic of JFET reverse biasing i.e. J FET ‘s have
extremely high characteristic gate input impedance. This impedance is typically in the high mega ohm
range. With the advantage of extremely high input impedance it draws no current from the source. The
high input impedance of the JFET has led to its extensive use in integrated circuits. The low current
requirements of the component makes it perfect for use in ICs. Where thousands of transistors must be
etched on to a single piece of silicon. The low current draw helps the IC to remain relatively cool, thus
allowing more components to be placed in a smaller physical area.

JFET PARAMETERS

The electrical behavior of JFET may be described in terms of certain parameters. Such parameters are
obtained from the characteristic curves.

A C Drain resistance(r d):

It is also called dynamic drain resistance and is the a.c.resistance between the drain and source terminal
when the JFET is operating in the pinch off or saturation region.It is given by the ratio of small change
in drain to source voltage ∆Vds to the corresponding change in drain current ∆Id for a constant gate to
source voltage Vgs.

Mathematically it is expressed as rd=∆Vds/ ∆Id where Vgs is held

constant. TRANSCONDUCTANCE (gm):

It is also called forward transconductance . It is given by the ratio of small change in drain current (∆Id)
to the corresponding change in gate to source voltage (∆Vds). Mathematically the transconductance can
be written as gm=∆Id/∆Vds
 AMPLIFICATION FACTOR (µ)

It is given by the ratio of small change in drain to source voltage (∆Vds) to the corresponding change in
gate to source voltage (∆Vgs)for a constant drain current (Id).

Thus µ=∆Vds/∆Vgs when Id held constant

The amplification factor µ may be expressed as a product of transconductance (gm)and ac drain

resistance (rd) µ=∆Vds/∆Vgs=gm rd

MOSFET

We now turn our attention to the insulated gate FET or metal oxide semi conductor FET which is
having the greater commercial importance than the junction FET.

Most MOSFETS however are triodes, with the substrate internally connected to the source. The circuit
symbols used by several manufacturers are indicated in the Fig below.

(a) Depletion type MOSFET (b) Enhancement type MOSFET

Here are two basic types of MOSFETS

(1) Depletion type (2) Enhancement type MOSFET.

D-MOSFETS can be operated in both the depletion mode and the enhancement mode. E MOSFETS
are restricted to operate in enhancement mode. The primary difference between them is their physical
construction. The construction difference between the two is shown in the fig given below.
 As we can see the D MOSFET have physical channel between the source and drain
terminals(Shaded area)

The E MOSFET on the other hand has no such channel physically. It depends on the gate voltage
to form a channel between the source and the drain terminals.

Both MOSFETS have a glass insulating layer SiO2 between the gate made up of metal which is
conductor and the substrate as another conductor, hence it is referred to as MOSFET. It is analogous to
parallel plate capacitor with a dielectric between two conducting layers.

Since the gate is insulated from the rest of the component, the MOSFET is sometimes
referred to as an insulated gate FET or IGFET.

The foundation of the MOSFET is called the substrate. This material is represented in the schematic
symbol by the center line that is connected to the source.
In the symbol for the MOSFET, the arrow is placed on the substrate. As with JFET an arrow pointing
in represents an N-channel device, while an arrow pointing out represents p-channel device.

CONSTRUCTION OF AN N-CHANNEL MOSFET:-

The N- channel MOSFET consists of a lightly doped p type substance into which two heavily doped
n+ regions are diffused as shown in the Fig. These n+ sections , which will act as source and drain.
A thin layer of insulation silicon dioxide (SIO2) is grown over the surface of the structure, and
holes are cut into oxide layer, allowing contact with the source and drain. Then the gate metal area is
overlaid on the oxide, covering the entire channel region. Metal contacts are made to drain and source
and the contact to the metal over the channel area is the gate terminal. The insulating layer of sio2
results in an extremely high input resistance (10 10 to 10power 15ohms) for MOSFET.

DEPLETION MOSFET

The basic structure of D –MOSFET is shown in the fig. An N-channel is diffused or implanted
between source and drain with the device an appreciable drain current IDSS flows for zero gate to
source voltage, Vgs=0.
Depletion mode operation:-
1) The above fig shows the D-MOSFET operating conditions with gate and source terminals shorted
together(VGS=0V)

2) At this stage ID= IDSS where VGS=0V, with this voltage VDS, an appreciable drain current
IDSS flows.

3) If the gate to source voltage is made negative i.e. VGs is negative. Positive charges are induced in
the channel through the SIO2 of the gate capacitor.

4) Since the current in a FET is due to majority carriers (electrons for an N-type material) , the
induced positive charges make the channel less conductive and the drain current drops as Vgs is
made more negative.

5) The re distribution of charge in the channel causes an effective depletion of majority carriers ,
which accounts for the designation depletion MOSFET.

6) That means biasing voltage Vgs depletes the channel of free carriers This effectively reduces the
width of the channel , increasing its resistance.

7) Note that negative Vgs has the same effect on the MOSFET as it has on the JFET.

8) As shown in the fig above, the depletion layer generated by Vgs (represented by the white space
between the insulating material and the channel) cuts into the channel, reducing its width. As a
result ,Id<Idss. The actual value of ID depends on the value of Idss,Vgs(off) and Vgs.

Enhancement mode operation of the D-MOSFET:-

1) This operating mode is a result of applying a positive gate to source voltage Vgs to the device.
2) When Vgs is positive the channel is effectively widened. This reduces the resistance of the
channel allowing ID to exceed the value of IDSS
3) When Vgs is given positive the majority carriers in the p-type are holes. The holes in the p type
substrate are repelled by the +ve gate voltage.
 4) At the same time, the conduction band electrons (minority carriers) in the p type material are
attracted towards the channel by the +gate voltage.
5) With the build up of electrons near the channel , the area to the right of the physical channel
effectively becomes an N type material.
6) The extended n type channel now allows more current, Id> Idss

Characteristics of Depletion MOSFET:-

The fig. shows the drain characteristics for the N channel depletion type MOSFET

1) The curves are plotted for both Vgs positive and Vgs negative voltages
.
2) When Vgs=0 and negative the MOSFET operates in depletion mode when Vgs is positive the
MOSFET operates in the enhancement mode.
3) The difference between JFET and D MOSFET is that JFET does not operate for positive values
of Vgs.

4) When Vds=0, there is no conduction takes place between source to drain, if Vgs<0 and Vds>0
then Id increases linearly.

5) But as Vgs,0 induces positive charges holes in the channel, and controls the channel width. Thus
the conduction between source to drain is maintained as constant, i.e. Id is constant.

6) If Vgs>0 the gate induces more electrons in channel side, it is added with the free electrons
generated by source. again the potential applied to gate determines the channel width and
maintains constant current flow through it as shown in Fig
TRANSFER CHARACTERISTICS:-

The combination of 3 operating states i.e. Vgs=0V, VGs<0V, Vgs>0V is represented by the D
MOSFET transconductance curve shown in Fig.

1) Here in this curve it may be noted that the region AB of the characteristics similar to that of
JFET.

2) This curve extends for the positive values of Vgs

3) Note that Id=Idss for Vgs=0V when Vgs is negative,Id< Idss when Vgs= Vgs(off) ,Id is reduced
to approximately omA.Where Vgs is positive Id>Idss.So obviously Idss is not the maximum
possible value of Id for a MOSFET.

4) The curves are similar to JFET so thet the D MOSFET have the same transconductance equation.

E-MOSFETS

The E MOSFET is capable of operating only in the enhancement mode. The gate potential must
be positive w.r.t to source.

1) when the value of Vgs=0V, there is no channel connecting the source and drain materials.

2) As a result , there can be no significant amount of drain current.

3) When Vgs=0, the Vdd supply tries to force free electrons from source to drain but the presence
of p-region does not permit the electrons to pass through it. Thus there is no drain current at
Vgs=0,

4) If Vgs is positive, it induces a negative charge in the p type substrate just adjacent to the SIO2
layer.

5) As the holes are repelled by the positive gate voltage, the minority carrier electrons attracted
toward this voltage. This forms an effective N type bridge between source and drain providing a
path for drain current.

6) This +ve gate voltage forma a channel between the source and drain.

7) This produces a thin layer of N type channel in the P type substarate.This layer of free electrons
is called N type inversion layer.
8) The minimum Vgs which produces this inversion layer is called threshold voltage and is
designated by Vgs(th). This is the point at which the device turns on is called the threshold
voltage Vgs(th)
9) When the voltage Vgs is <Vgs (th) no current flows from drain to source.

10) However when the voltage Vgs > Vgs (th) the inversion layer connects the drain to source and
we get significant values of current.

CHARACTERISTICS OF E MOSFET:-

1. DRAIN CHARACTERISTICS

The volt ampere drain characteristics of an N-channel enhancement mode MOSFET are given in the
Figure
 2. TRANSFER CHARACTERISTICS:-

1) The current Idss at Vgs≤ 0 is very small beinf of the order of a few nano amps.
2) As Vgs is made +ve , the current Id increases slowly at forst, and then much more rapidly with
an increase in Vgs.
3) The standard transconductance formula will not work for the E MOSFET.
4) To determine the value of ID at a given value of VGs we must use the
2
following relation Id =K[Vgs-Vgs(Th)]

Where K is constant for the MOSFET . found as

K=

From the data specification sheets, the 2N7000 has the following ratings.

Id(on)= 75mA(minimum).

And Vgs(th)=0.8(minimum)

5.8 APPLICATION OF MOSFET

One of the primary contributions to electronics made by MOSFETs can be found in the area of
digital (computer electronics). The signals in digital circuits are made up of rapidly switching dc
levels. This signal is called as a rectangular wave ,made up of two dc levels (or logic levels). These
logic levels are 0V and +5V.
 A group of circuits with similar circuitry and operating characteristics is referred to as a logic
family. All the circuits in a given logic family respond to the same logic levels, have similar speed
and power-handling capabilities , and can be directly connected together. One such logic family is
complementary MOS (or CMOS) logic. This logic family is made up entirely of MOSFETs.

5.9 BIASING FET:-

For the proper functioning of a linear FET amplifier, it is necessary to maintain the
operating point Q stable in the central portion of the pinch off region The Q point should be
independent of device parameter variations and ambient temperature variations

This can be achieved by suitably selecting the gate to source voltage VGS and drain current ID
which is referred to as biasing

JFET biasing circuits are very similar to BJT biasing circuitsThe main difference
between JFET circuits and BJT circuits is the operation of the active components themselves

There are mainly two types of Biasing circuits

1) Self bias
2) Voltage divider bias.

SELF BIAS
Self bias is a JFET biasing circuit that uses a source resistor to help reverse bias the JFET gate. A
self bias circuit is shown in the fig. Self bias is the most common type of JFET bias. This JFET must be
operated such that gate source junction is always reverse biased. This condition requires a negative VGS
for an N channel JFET and a positive VGS for P channel JFET. This can be achieved using the self bias
arrangement as shown in Fig. The gate resistor RG doesn’t affect the bias because it has essentially no
voltage drop across it, and : the gate remains at 0V .RG is necessary only to isolate an ac signal from
ground in amplifier applications. The voltage drop across resistor RS makes gate source junction reverse
biased.
DC analysis of self Bias:-
For the dc analysis coupling capacitors are open circuits for the N channel FET in Fig (a)

IS produces a voltage drop across RS and makes the source positive w.r.t ground. In any JFET circuit all
the source current passes through the device to the drain circuit. This is due to the fact that there is no
significant gate current.

We can define source current as IS = ID

(VG =0 because there is no gate current flowing in RG So VG across RG is zero) VG

=0 then VS= ISRS =ID RS

VGS = VG-VS =0-ID RS=- ID RS

Id=Idss[1-VGS/VP]2 where VGS for N channel JFET is =-id Rs

Substuting this value in the above equation

Id=Idss[1- ]2 Id=Idss[1+ ]2
 VOLTAGE DIVIDER BIAS:-

The fig. shows N channel JFET with voltage divider bias. The voltage at the source of JFET must
be more positive than the voltage at the gate in order to keep the gate to source junction reverse biased.
The source voltage is

VS = IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the
voltage divider formula.

Vg= Vdd

For dc analysis

Applying KVL to the input

circuit VG-VGS-VS =0

:: VGS = VG-Vs=VG-ISRS and VGS = VG-IDRS :: IS = ID

 Applying KVL to the input circuit we get VDS+IDRD+VS-VDD =0

::VDS = VDD-IDRD-IDRS VDS = VDD-ID ( RD +RS )

The Q point of a JFET amplifier , using the voltage divider bias

is IDQ = IDSS [1-VGS/VP]2 VDSQ = VDD-ID ( RD+RS )

COMPARISON OF MOSFET WITH JFET

a. In enhancement and depletion types of MOSFET, the transverse electric field induced
across an insulating layer deposited on the semiconductor material controls the
conductivity of the channel.

b. In the JFET the transverse electric field across the reverse biased PN junction controls the
conductivity of the channel.
c. The gate leakage current in a MOSFET is of the order of 10-12A. Hence the input resistance
of a MOSFET is very high in the order of 1010 to 1015 Ω. The gate leakage current of a JFET
is of the order of 10-9A., and its input resistance is of the order of 108Ω.

d. The output characteristics of the JFET are flatter than those of the MOSFET, and hence the
drain resistance of a JFET (0.1 to 1MΩ) is much higher than that of a MOSFET (1 to
50kΩ).

e. JFETs are operated only in the depletion mode. The depletion type MOSFET may be
operated in both depletion and enhancement mode.

f. Comparing to JFET, MOSFETs are easier to fabricate.

g. Special digital CMOS circuits are available which involve near zero power dissipation
and very low voltage and current requirements. This makes them suitable for portable
systems.

5.5 THE FET SMALL SIGNAL MODEL

The linear small signal equivalent circuit for the FET can be obtained in a manner similar to that
used to derive the corresponding model for a transistor.

We can express the drain current iD as a function f of the gate voltage and drain voltage Vds. Id

=f(Vgs,Vds) (1)
The transconductance gm and drain resistance rd:-

If both gate voltage and drain voltage are varied, the change in the drain current is approximated
by using taylors series considering only the first two terms in the expansion

∆id= |vds=constant .∆vgs |vgs=constant

∆vds we can write ∆id=id

∆vgs=vgs

∆vds=vds

Id=gm v Vds→(1)

Where gm= |Vds |Vds

gm= |Vds is the mutual conductance or transconductance. It is also called as gfs or

yfs common source forward conductance .
The second parameter rd is the drain resistance or output resistance is defined as

rd= |Vgs |Vgs=

|Vgs rd= |Vgs

The reciprocal of the rd is the drain conductance gd .It is also designated by Yos and Gos and
called the common source output conductance . So the small signal equivalent circuit for FET can be
drawn in two different ways.

1. small signal current –source

model 2.small signal voltage-source

model.

A small signal current –source model for FET in common source configuration can be drawn satisfying
Eq→(1) as shown in the figure(a)
 This low frequency model for FET has a Norton’s output circuit with a dependent current
generator whose magnitude is proportional to the gate-to –source voltage. The proportionality factor is
the trans conductance ‘gm’. The output resistance is ‘rd’. The input resistance between the gate and source
is infinite, since it is assumed that the reverse biased gate draws no current. For the same reason the
resistance between gate and drain is assumed to be infinite.

The small signal voltage-source model is shown in the figure(b).

This can be derived by finding the Thevenin’s equivalent for the output part of fig(a) .

These small signal models for FET can be used for analyzing the three basic FET amplifier
configurations:

1) common source (CS) 2) Common drain (CD) or source follower

3. common gate(CG).
(a)Small Signal Current source model for FET (b)Small Signal voltage source model for FET

Here the input circuit is kept open because of having high input impedance and the output circuit
satisfies the equation for ID

FET AMPLIFIERS
INTRODUCTION
Field Effect Transistor (FET) amplifiers provide an excellent voltage gain and high input
impedence. Because of high input impedence and other characteristics of JFETs they are preferred over
BJTs for certain types of applications.

There are 3 basic FET circuit configurations:

i)Common Source
ii)Common Drain
iii)Common Gain
 Similar to BJT, CE, CC and CB circuits, only difference is in BJT large output collector
current is controlled by small input base current whereas, FET controls output current by means of
small input voltage. In both the cases output current is controlled variable.
FET amplifier circuits use voltage controlled nature of the JFET. In Pinch off region, ID
depends only on VGS.
Common Source (CS) Amplifier

A simple Common Source amplifier and associated small signal equivalent circuit using voltage-source
model of FET is shown in Figure
Voltage Gain
Source resistance (RS) is used to set the Q-Point but is bypassed by CS for mid-frequency operation.
From the small signal equivalent circuit ,the output voltage
VO = -gmVgs(RD//rd)

Where Vgs = Vi , the input voltage,

Hence, the voltage gain,
AV = VO / Vi = -gm(RD//rd)

Input Impedence
From Figure Input Impedance is Zi = RG
For voltage divider bias as in CE Amplifiers of BJT
RG = R1 ║ R2
Output Impedance
Output impedance is the impedance measured at the output terminals with the input voltage VI = 0 .
From the Figure when the input voltage Vi = 0, Vgs = 0 and hence
Output impedance Zo = rd ║ RD , Normally rd will be far greater than RD . Hence Zo ≈ RD

Common Drain Amplifier

In this circuit, input is applied between gate and source and output is taken between source and drain.

In this circuit, the source voltage is Vs = VG+VGS

 When a signal is applied to the JFET gate via C1 ,VG varies with the signal. As VGS is fairly constant
and Vs = VG+VGS, Vs varies with Vi.
The following figure shows the low frequency equivalent model for common drain circuit.

Input Impedance Zi

Zi = RG
Output Impedance Zo : It is given by
Voltage gain (Av)
It is given by

Substitute the value Vo and Vi. Then

Common drain circuit does not provide voltage gain.& there is no phase shift between input and
output voltages.
 Common Gate Amplifier
In this circuit, input is applied between source and gate and output is taken between drain and gate.

In CG Configuration, gate potential is at constant potential. so, increase in input voltage Vi in positive
direction increase the negative gate source voltage. Due to decrease in ID drop IDRD reduces. Since
VD= VDD-IDRD, the reduction in ID results in an increase in output voltage.

1. Input Impedance
After substituting and simplification,

Output Impedance Zo
 3.Voltage gain (Av)

Table summarizes the performance of common gate amplifier

 JFET AS A VVR OR VDR

Let us consider the drain characteristics of FET as shown in the fig.

● FET is a device that is usually operated in the constant-current portion of its output characteristics.
● But if it is operated in the region prior to pinch-off (that is where VDS is small, say below 100 mV), it will
behave as a voltage-variable resistor (VVR).
● It is due to the fact that in this region drain-to-source resistance RDS can be controlled by varying the bias
voltage VGS.
● In such applications the FET is also referred to as a voltage-variable resistor or voltage dependent resistor.
● It finds applications in many areas where this property is useful.
● Figure shows the drain characteristic curves for a 2N 5951 in the ohmic region (i.e. for low VDS).
● From the characteristic curve it can be seen that RDS varies with VGS. Ex: when VGS = 0, RDS = 133 ohm
and when VGS = – 2 V, RDS = 250 ohm.
● Because of this a JFET operating in the ohmic region with small ac signals acts as a voltage-controlled
resistance.
● Note that the drain curves shown in figure, extend on both sides of the origin.
● This means that a JFET can be employed as a voltage-variable resistor for small ac signals, typically those
less than 100 mV.
● When it is employed in this way, it does not require a dc drain voltage from the supply. All that is required is
an ac input signal.
Basic concepts of MOSFET Amplifier
For a MOSFET to produce linear amplification, it has to operate in its saturation region, unlike
the Bipolar Junction Transistor (BJT).

But just like the BJT, it too needs to be biased around a centrally fixed Q-point.

Common Source D-MOSFET Amplifier

Fig.1 shows a common-source amplifier using n-channel D-MOSFET. Since the source terminal
is common to the input and output terminals, the circuit is called common source amplifier.

The circuit is zero biased with an a.c. source coupled to the gate through the coupling
capacitor C1 .
The gate is at approximately 0V d.c. and the source terminal is grounded, thus making VGS = 0V
.
Operation
The input signal (Vin ) is capacitively coupled to the gate terminal .
In the absence of the signal, d.c. value of VGS = 0V .
When signal (Vin) is applied, Vgs swings above and below its zero value , producing a swing in
drain current Id .
▪ A small change in gate voltage produces a large change in drain current as in JFET. This fact
makes MOSFET capable of raising the strength of a weak signal; thus acting as an amplifier.
▪ During the positive half-cycle of the signal, the positive voltage on the gate increases and
produces the enhancement-mode. This increases the channel conductivity and hence the
drain current .
▪ During the negative half-cycle of the signal, the positive voltage decreases and produces
depletion-mode. This decreases the conductivity and hence the drain current .
The result of above action is that a small change in gate voltage produces a large change in the
drain current. This large variation in drain current produces a large a.c. output voltage across
drain resistance RD. In this way, D-MOSFET acts as an amplifier.
 Common Source E-MOSFET Amplifier
The Enhancement MOSFETS, or E-MOSFETS, only conduct when a suitable gate-to-source positive
voltage is applied, unlike Depletion type MOSFETs. which conduct only when the gate voltage is zero.
However, due to the construction and physics of an enhancement type MOSFET, there is a minimum
gate-to-source voltage, called the threshold voltage VTh that must be applied to the gate before it starts to
conduct, thus allowing the drain current to flow.
In other words, an E-MOSFET does not conduct until the gate-source voltage, VGS is less than the
threshold voltage, VTh. .
But as the forward bias at the gate increases, the drain current ID (or drain-source current, IDS) will also
increase, making the E-MOSFET ideal for use in MOSFET amplifier circuits.

Differences Between BJT and JFET

BASIS OF
BJT FET
COMPARISON
Bipolar Junction Transistors are
Field Effect Transistors are
bipolar devices in which there is a
Description unipolar devices, in which only the
flow of both majority and
majority carriers flows.
minority charge carriers.
It consist of three terminals that is, It consist of three terminals that is,
emitter, base and collector which Source, drain and gate which are
Terminals
are denoted by E, B and C denoted by S, D and G
respectively. respectively.
FETs are voltage controlled. They
BJTs are current controlled. They
only require a voltage applied to
Functionality require a bias current to the base
the door to enable or disable the
terminal to operate.
FET.
The input circuit of BJT is The input circuit of FET is
Impedance forward biased and therefore BJT reversed biased and therefore FET
has low input impedance. exhibits relatively higher
 impedance.
Output Current The base current controls the The Gate voltage controls the
Control output current. output current.
FET is less noisy compared to
Noise BJT has more noisy operation.
BJT.
Temperature BJT has a positive temperature FET has a negative temperature
Coefficient coefficient at high current levels. coefficient at high current levels.
Switching Speed & It has lower switching speed and It has higher switching speed and
Cut off Frequencies cut off frequencies. cut off frequencies.
FETs are relatively smaller in size
BJT are larger in size and
especially in case of integrated
Size therefore require more space than
circuits composed of many
FETs normally.
transistors.
BJT are most preferred during the FETs are most preferred during the
Suitability
application of low current. applications of high current.
Relationship In BJT the relation between input In FET, the relation between input
Between Input And and output is considered to be and output is considered to be
Output linear. non-linear.
FETs are relatively costly to
Cost BJTs are cheaper to produce.
produce.
Due to reduction in minority FET operation does not depend
carrier lifetime, the performance upon the minority carriers and
Effect Of Radiation
of BJT is degraded by neutron therefore they can tolerate much
radiation. higher level of radiation.
FETs are more popular around the
BJTs are less popular and less
Usage world and most of the current
frequently used.
application or devices use FETs.

Differences Between JFET And MOSFET

S. No JFET MOSFET
1 MOSFET(Metal–Oxide–Semicond
JFET(Junction Gate Field-Effect uctor Field-Effect Transistor) is a
Transistor) is a three-terminal four-terminal semiconductor
semiconductor device. device.

2 It can only operates in the depletion mode. It operates in both depletion mode
and enhancement mode.
3 It has high input impedance on the order of 1010 It offers even higher input
 ohms, therefore they are more sensitive towards impedance than the JFETs,
input voltage signals. theredore they are more resistive.
4 It allows the gate leakage current on the order of While the gate leakage current for
10^-9 A MOSFETs will be of the order of
10^-12 A.
5 It is relatively cheaper than MOSFETs It is expensive one.
6 These are ideal for low noise applications. These are mainly used for high
noise applications.
7 These are less susceptible to damage because of These are more susceptible to
the high input capacitance. damage because of the metal oxide
insulator.
8 Manufacturing process of JFETs is simple. Manufacturing process of
MOSFETs is complex.