Presentation Topic

Analog and Digital Electronics

Yogesh K Sharma
[email protected]
Department of Computer Engineering

BRACT’S, Vishwakarma Institute of Information Technology, Pune-48

(An Autonomous Institute affiliated to Savitribai Phule Pune University)

(NBA and NAAC accredited, ISO 9001:2015 certified)
 Introduction
To
Programmable Logic Devices(PLD’s)

Unit - 4

Courtesy: R. P. Jain & J. S. Katre (Modern Digital Electronics)

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 2

 Course Objectives
1. To learn and understand basic digital circuit design techniques.
2. To study the implementation of digital circuits using combinational logic.
3. To study the implementation of digital circuits using sequential logic.
4. To illustrate the concept of PLD’s.
5. To study the implementation of digital circuits using VHDL.
6. To understand basics of Logic Families and IOT circuit boards in development of mini digital circuits.

Course Outcome
1. Simplify Boolean algebraic expressions for designing digital circuits using K- Maps. (Analyzing)
2. Apply digital concepts in designing combinational circuits. (Applying)
3. Apply digital concepts in designing sequential circuits. (Applying)
4. Implement digital circuits using PLA and PAL. (Applying)
5. Design digital circuits using VHDL. (Applying)
6. Design and implementation of Mini digital circuit applications. (Applying)
.

Yogesh K Sharma, Department of Computer Engineering, VIIT , Pune-48 3

 Introduction to PLD’s

Introduction to PLD’s:

➢ Introduction to PLD’s: - ROM, PAL, PLA, Applications of

PLAs to implement combinational and sequential logic
circuits.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 4

 Programmable Logic Device
➢ A Combinational PLD is an integrated circuit with programmable gates divided into
an AND array and an OR array to provide an AND-OR sum of product
implementation.
➢ We have studied different IC’s such as multiplexers, demultiplexers, adders, code
converters which are called as fixed function ICs.
➢ The advantages of designing logic circuits using the fixed function ICs are low
development cost & easy testing, & disadvantages is requirement of large board
space, large power requirements, no security, additional costs needed for the
modification of existing circuit.
➢ The ICs that are used for designing a specific application is called the application
specific integrated circuits (ASICs). They are too complex to design.
➢ The third approach to the problem of digital circuit design is to use the programmable
logic devices (PLDs). It has the advantages of both the approaches discussed
earlier.
➢ PLD are special type of ICs which can be programmed by the users as per their
requirements.
➢ Thus it is possible to implement a combinational or sequential circuit using the PLD
ICs.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 5

 Programmable Logic Device
Advantages of PLDs:
➢ Reduced space requirement.
➢ Reduction in power requirement.
➢ Increased speed of switching.
➢ Better security, Higher density, low production cost as compared to
ASICS.
➢ Low development cost, short design cycle i.e. time required to implement
the design is short.
➢ More flexibility to the designer.
➢ Reprogramming is possible to be done within few seconds.
➢ Modifications can be carried out within a short span of time.
➢ An important application of PLDs is that we can prepare prototype ASIC
design, & reduces the time required to design ASIC

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 6

 Programmable Logic Device
Types of PLDs:
➢ Programmable Read only memories (PROMs).
➢ Programmable Logic Array (PLAs).
➢ Programmable Array Logic (PALs).
➢ Simple Programmable Logic Devices (SPLDs).
➢ Complex Programmable Logic Devices (CPLDs).
➢ Field Programmable Gate Arrays (FPGAs).

Note:
➢ Stores permanent binary information (nonvolatile). Can be read only
(cannot be altered). Information is specified by designer and physically
inserted (embedded) into the PLD.
➢ Programmable connections are formed by fuses, masks, or antifuses
depending on the technology.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 7

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 8
 ROM as PLD

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 9

 ROM as PLD
➢ k x 2k decoder to decode input address.
➢ n OR gates with 2k input each.
➢ Decoder output is connected to all n OR gates through
fuses.
➢ ROM -> 2k x n programmable connections.
➢ EX: 4 x 2 ROM.
➢ Truth table -> address and content of ROM.
➢ Programming -> stores truth table in ROM.
➢ 0 = Open connection = Fuse blown.
➢ 1 = Closed connection = Fuse intact.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 10

 ROM as PLD

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 11

 Function Synthesis with ROM

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 12

 Programmable Logic Array
➢ A PLD generally consists of programmable array of logic gates.
Interconnections are made with the array inputs.
➢ The outputs are connected to the device pins through inverting or
noninverting buffers and flip flops.
➢ The logic gates used can be two level AND-OR, NAND-NAND or NOR-
NOR configuration. Sometimes AND-OR-EXOR configuration is also
used.
➢ There are two types of PLDs namely the PLA i.e. programmable logic
arrays and PAL i.e. the programmable array logic. Due to the used of
AND matrix followed by the OR matrix, we can use them for the
implementation of logic functions in the SOP form.
➢ A PLA consists of two level of AND-OR circuit on the same chip.
➢ The AND matrix can be used to implement the product terms in the SOP
form and the OR matrix is used for implementing the sum of product
term.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 13

➢ Behave like a ROM but has different structure:
➢ Uses ANDs array instead of decoder to produce product terms of inputs
➢ Has programmable connections before ANDs, between ANDs and ORs,
after ORs. That is 2nk + km + m fuses
➢ More flexible than ROM but more difficult to program.
➢ Logic expressions for content information to be stored in PLA must be
obtained first, then minimized, and finally programmed into the PLA using a
PLA program table.
➢ PLA program table specifies product terms and sum terms of information
that will be stored in PLA.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 14

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 15
 Function Synthesis with PLA

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 16

 Function Synthesis with PLA

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 17

 Programmable Logic Array
Input Buffers: (See Pg. No. 14-12 J.S. Katre)
➢ It is used for avoiding the loading of sources connected at the inputs.
➢ Buffers are of two types namely, inverted buffers and non-inverted buffers.
➢ One such buffer is used for each of the M input lines.

AND Matrix:
➢ There are 2M inputs for each AND gate, Po is the output of one of such an AND
gate.
➢ There is a nichrome fuse link connected in series with each input. Thus Po=0 if
all the fuse links are intact.
➢ In an unprogrammed PLA device all the fuse links are intact.
➢ Thus it consists of ‘n’ such AND gates formed with the help of diodes. Each AND
gate has 2M inputs. The output is thus a product term. So the required product
term can be generated by opening the unwanted nichrome fuse links.
➢ The (x) marks indicate that a connection is present. Each AND gate has 2M
inputs which are shown only by a single line.
➢ When a logic function is to be implemented, we have to program the array. In
programming the desired connections are left with the (x) marks and such mark
is not used when connection is not required.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 18

 Programmable Logic Array(PLA)
OR Matrix:
➢ The output of AND matrix is used as the inputs to the OR matrix. These
are applied to the bases of transistors.
➢ An OR gate is formed by parallel connected transistors and the load is
common and connected in the emitters.
➢ The required sum terms are obtained by opening the unwanted fuse
links.
➢ It is possible to programme the OR matrix, by open circuiting the
unwanted fuse links. The open fuse links are equivalent to a “0” at the
input of corresponding OR gate.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 19

 The OR Array

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 20

 The AND Array

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 21

 Programmable Logic Array
Invert/Non Invert Matrix:
➢ The block following the OR matrix is the inverting/non inverting matrix
which is basically a programmable buffer.
➢ It can invert its input if active low output is required. Its input is passed
without any inversion, if active high output is required.
➢ Thus the sum of product terms obtained at the outputs of the OR matrix
can be either inverted or passed through as it is.
➢ For the EX-OR gate, if the fuse link is closed, then one of inputs will be 0.
Hence 0 + S= S. Whereas if the fuse link is opened then that input will
be treated as 1. So 1 + S = S. i.e. inversion will take place.
Output Buffers:
➢ The current sourcing capability of the PLA can be increased by using the
output buffer. The PLA outputs are generally TTL compatible.
➢ In tristate output buffer, the chip enable CE input is applied to the output
buffers. When CE =0, the outputs will be made available.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 22

 Programmable Logic Array
Output through Buffers and Flip Flops:
➢ If the PLA devices are to be used for state machine applications, then the
output circuit consists of buffers and flip flops.
➢ The OR gate outputs are connected to the inputs of the positive edge
triggered SR flip flops. The flip flop outputs are then applied to the tristate
buffers and the device outputs are obtained as the buffer outputs.

Programming Procedure for PLA:

➢ PLA programming is similar to the ROM programming.
➢ Like ROM, it is possible to mask programme the PLA devices.
➢ According to the requirement specified by the user, the manufacturer
prepares a mask and the data patterns are stored on the PLA.
➢ In field PLA (FPLA), all the nichrome fuse elements are intact at the time
of manufacturing. At the time of programming, all the unwanted links are
open circuited electrically.
➢ It is not possible to reprogramme an FPLA.
Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 23
 Programmable Logic Array
Applications Areas of PLA:
➢ We can implement the combinational as well as the sequential circuits
using PLA.
➢ For implementing the combinational circuits, the PLA devices with only
output buffers are used.
➢ For implementing the sequential circuits, the PLA devices with flip flop
and buffers are included in the output stage.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 24

Programmable Array Logic(PAL)
➢ Similar to PLA
➢ Only the connection inputs to ANDs are programmable
➢ Easier to program than but not as flexible as PLA
➢ There are feedback connections
➢ Logic expressions for content information to be stored in PAL must
be obtained first, then minimized, and finally programmed into the
PAL using a PAL program table
➢ PAL program table specifies only product terms of information that
will be stored in PAL.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 25

Field Programmable Logic Array
➢ FPLA can be programmed by the user.
➢ Commercial hardware programmer units are available for use in conjunction
with certain FPLAs.
➢ Here we have fused programmable AND array and fused programmable OR
array.

Field Programmable Gate Array (FPGA)

➢ It is an integrated circuit designed to be configured by the customer or
designer after manufacturing “field-programmable”.
➢ It consists of an array of logic blocks with programmable row and column
and interconnecting channels surrounded by programmable input output
blocks.
➢ It is generally specified using a hardware description language(HDL).

Complex Programmable Logic Devices(CPLD):

➢ It is a collection of individual PLDs on a single chip, with a programmable
interconnection structure that allows the PLDs to get connected as the
user wants.
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Design a BCD to Excess-3 code convertor and implement using suitable PLA.

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 38

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Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 41
 End
of
Unit-4

Yogesh K Sharma, Department of Computer Engineering, VIIT, Pune-48 42