ADE (Unit 4) (PLD)
ADE (Unit 4) (PLD)
Yogesh K Sharma
[email protected]
Department of Computer Engineering
Unit - 4
Course Outcome
1. Simplify Boolean algebraic expressions for designing digital circuits using K- Maps. (Analyzing)
2. Apply digital concepts in designing combinational circuits. (Applying)
3. Apply digital concepts in designing sequential circuits. (Applying)
4. Implement digital circuits using PLA and PAL. (Applying)
5. Design digital circuits using VHDL. (Applying)
6. Design and implementation of Mini digital circuit applications. (Applying)
.
Introduction to PLD’s:
Note:
➢ Stores permanent binary information (nonvolatile). Can be read only
(cannot be altered). Information is specified by designer and physically
inserted (embedded) into the PLD.
➢ Programmable connections are formed by fuses, masks, or antifuses
depending on the technology.
AND Matrix:
➢ There are 2M inputs for each AND gate, Po is the output of one of such an AND
gate.
➢ There is a nichrome fuse link connected in series with each input. Thus Po=0 if
all the fuse links are intact.
➢ In an unprogrammed PLA device all the fuse links are intact.
➢ Thus it consists of ‘n’ such AND gates formed with the help of diodes. Each AND
gate has 2M inputs. The output is thus a product term. So the required product
term can be generated by opening the unwanted nichrome fuse links.
➢ The (x) marks indicate that a connection is present. Each AND gate has 2M
inputs which are shown only by a single line.
➢ When a logic function is to be implemented, we have to program the array. In
programming the desired connections are left with the (x) marks and such mark
is not used when connection is not required.