14

The Instruction Set of 8086

1. How many instructions are there in the instruction set of 8086?

Ans. There are 117 basic instructions in the instruction set of 8086.
2. Do 8086 and 8088 have the same instruction set?
Ans. Yes, both 8086 and 8088 have the same instruction set.
3. Mention the groups in which the instruction set of 8086 can be categorised.
Ans. The instruction set of 8086 can be divided into the following number of groups,
namely:
z Data transfer instructions
z Arithmetic instructions
z Logic instructions
z Shift instructions
z Rotate instructions
z Flag control instructions
z Compare instructions
z Jump instructions
z Subroutines and subroutine handling instructions
z Loop and loop handling instructions
z Strings and string handling instructions.
4. Mention the different types of data transfer instructions.
Ans. The different types include:
z Move byte or word instructions (MOV)
z Exchange byte or word instruction (XCHG)
z Translate byte instructions (XLAT)
z Load effective address instruction (LDA)
z Load data segment instruction (LDS)
z Load extra segment instruction (LES)
5. Can the MOV instruction transfer data directly between a source and
destination that both reside in external memory?
Ans. No, it cannot. With the first MOV instruction, data from the source memory is to be moved
into an internal register-normally accumulator. The second MOV instruction places the
accumulator content into the destination memory.
 The Instruction Set of 8086 227

6. Explain the following two examples:

(a) MOV CX, CS
(b) MOV AX, [ALPHA]
Ans. (a) MOV CX, CS: It stands for, “move the contents of CS into CX”. If CS contains
1234 H, then on execution of this instruction, content of CX would become 1234 H
i.e., content of CH = 12 H and Content CL = 34 H.
(b) MOV AX, [ALPHA]: Let, data segment register DS contains 0300 H and ALPHA
corresponds to a displacement of 1234 H. Then the instruction stands for, “move the
content of the memory location offset by 1234 H from the starting location 0300 H
of the current data segment into accumulator AX”. The physical address is
PA = 03000 H + 1234 H = 04234 H
Thus execution of the instruction results in content of memory location 04234 H
is moved to AL and content of memory location 04235 H is moved to AH.
7. Show the forms of XCHG instruction and its allowed operands.
Ans. These are shown below in Fig. 14.1
Mnemonic Meaning Format Operation Flags affected

XCHG Exchange XCHG D,S (D)↔(S) None

(a)

Destination Source
Accumulator Reg16
Memory Register
Register Register

(b)
Fig.14.1: (a) Exchange data transfer instruction (b) Allowed operands

8. Explain the instruction XCHG BX, CX.

Ans. The execution of this instruction interchanges the contents of BX and CX, i.e., original
content of CX moves over to BX and original content of BX moves over to CX.
9. Explain XLAT instruction.
Ans. The translate (XLAT) data transfer instruction is shown in Fig.14.2. It can be used for
say an ASCII to EBCDIC code conversion.

Mnemonic Meaning Format Operation Flags affected

XLAT Translate XLAT ((AL)+(BX)+(DS)O)→(AL) None

Fig.14.2: Translate data transfer instruction

The content of BX represents the offset of the starting address of the look up table
from the beginning of the current data segment while the content of AL represents the
offset of the element which is to be accessed from the beginning of the look up table.
As an example, let DS = 0300 H, BX = 1234 H and AL = 05 H.
Hence, PA = 03000 H + 1234 H + 05 H = 04239 H
228 Understanding 8085/8086 Microprocessors and Peripheral ICs through Questions and Answers

Thus, execution of XLAT would put the content of 04239 H into AL register.
Conceptually, the content of 04239 H in EBCDIC should be the same as the ASCII
character equivalent of 05 H.
10. Explain the instruction LEA, LDS and LES.
Ans. These three instructions are explained in Fig.14.3. These instructions stand for load
register with effective address (LEA), load register and data segment register (LDS) and
load register and extra segment register (LES) respectively.
Mnemonic Meaning Format Operation Flags affected

LEA Load effective address LEA Reg 16, EA (EA)→(Reg16) None

LDS Load register and DS LDS Reg 16, Mem 32 (Mem 32)→(Reg16)
(Mem 32)→(Reg16)
(Mem 32+2)→(ES) None
(Mem 32+2)→(Reg 16)
LES Load register and ES LES Reg 16, Mem 32 (Mem 32+2)→(ES) None

Fig.14.3: LEA, LDS and LES data transfer instructions

LEA instruction loads a specified register with a 16-bit offset value. LDS and LES
instructions load the specified register as well as DS or ES segment register respectively.
Thus a new data segment will be activated by a single execution.
11. Indicate the different types of arithmetic instructions possible with 8086.
Ans. The different arithmetic instructions are addition, subtraction, multiplication and division
and are shown in Fig.14.4.
Addition

ADD Add byte or word

ADC Add byte or word with carry
INC Increment byte or word by 1
AAA ASCII adjust for addition
DAA Decimal adjust for addition

Subtraction
SUB Subtract byte or word
SBB Subtract byte or word with borrow
DEC Decrement byte or word by 1
NEG Negate byte or word
AAS ASCII adjust for subtraction
DAS Decimal adjust for subtraction

Multiplication
DIV Divide byte or word unsigned
IDIV Integer divide byte or word
AAD ASCII adjust for division
CBW Convert byte to word
CWD Convert word to double word

Fig.14.4: Arithmetic instructions

 The Instruction Set of 8086 229

12. Show the allowed operands for the instruction ADD, ADC and INC.
Ans. The allowed operands for ADD and ADC are shown in Fig.14.5 (a) and for INC it is shown
in Fig.14.5 (b).

Destination Source
Register Register
Register Memory
Destination
Memory Register
Register Immediate Reg 16
Memory Immediate Reg 8
Accumulator Immediate Memory
(b)
(a)
Fig.14.5: (a) Allowed operands for ADD and ADC
(b) Allowed operands for INC

13. Show the different subtraction arithmetic instructions. Also show the allowed
operands for (a) SUB and SBB (b) DEC and (c) NEG instructions.
Ans. The different subtraction arithmetic instructions and the allowed operands, for the
different instructions are shown in Fig. 14.6 (a), (b), (c) and (d) respectively.
Mnemonic Meaning Format Operation Flags affected

SUB Subtract SUB D,S (D)–(S)→(D) OF, SF, ZF, AF, PF, CF
Borrow→(CF)
SBB Subtract with borrow SBB D,S (D)–(S)–(CF)→(D ) OF, SF, ZF, AF, PF, CF
DEC Decrement by 1 DEC D (D)–1→(D) OF, SF, ZF, AF, PF
NEG Negate NEG D 0–(D)→(D) OF, SF, ZF, AF, PF, CF
1→(CF)
DAS Decimal adjust for DAS SF, ZF, AF, PF, CF
subtraction OF undefined
AAS AASCII adjust for AAS AF, CF, OF, SF, ZF,
subtraction PF undefined

(a)

Destination Source
Register Register
Register Memory
Memory Register Destination Destination
Accumulator Immediate Reg16 Register
Register Immediate Reg 8 Memory
Memory Immediate Memory
(b) (c) (d)
Fig.14.6: (a) Subtraction arithmetic operations
(b) Allowed operands for SUB and SBB instructions
(c) Allowed operands for DEC instruction
(d) Allowed operands for NEG instruction
230 Understanding 8085/8086 Microprocessors and Peripheral ICs through Questions and Answers

14. Show the different multiplication and division instructions and also the
allowed operands.
Ans. The different multiplication and division instructions and also the allowed operands are
shown in Fig.14.7 (a) and (b) respectively.

Mnemonic Meaning Format Operation Flags affected

MUL Multiply MUL S → (AX)
(AL).(S8)→ OF, CF, SF, ZF, AF,
(unsigned) (AX).(S16)→
→ (DX).(AX) PF, undefined
DIV Division DIV S (1) Q((AX)/(S8))→→ (AL) OF, SF, ZF, PF, CF
(unsigned) R((AX)/(S8))→→ (AH) undefined
(2) Q((DX, AX)/(S16))→→ (AX)
R((DX,AX)/(S16))→ → (DX)
If Q is FF16 in case (1) or
FFFF16 in case (2), then
type 0 interrupt occurs.
IMUL Integer multiply IMUL S (AL).(S8)→
→ (AX) OF, CF, SF, ZF,
(signed) (AX).(S16)→→ (DX),(AX) AF, PF undefined
IDIV Integer divide IDIV S (1) Q((AX)/(S8))→→ (AX) OF, SF, ZF, AF,
(signed) R((AX)/(S8))→→ (AH) PF, CF undefined
(2) Q((DX,AX)/(S16))→→ (AX)
R((DX,AX)(S16))→ → (DX)
If Q is positive and exceeds
7FFF16, or if Q is negative
and becomes less than 800116,
then type 0 interrupt occurs
AAM Adjust AL for AAM → AH
Q((AL)/10))→ SF, ZF, PF,
multiplication → AL
R((AL)/10))→ OF, AF, CF undefined
AAD Adjust AX for AAD .
(AH) 10 + AL → AL SF, ZF, PF,
division 00 → AH OF, AF, CF undefined
CBW Convert byte CWD → (All bits of AH)
(MSB of AL)→ None
to word
CWD Convert word to CWD → (All bits of DX)
(MSB of AX)→ None
double word

(a)

Source
Reg 8
Reg 16
Mem 8
Mem 16
(b)
Fig.14.7: (a) Multiplication and division instructions (b) Allowed operands.
15. Show the different logic instructions and also the allowed operands for
(a) AND, OR and XOR (b) NOT instructions.
Ans. The different logic instructions as also the allowed operands for different instructions are
shown in Fig.14.8 (a), (b) and (c) respectively.