MODULE – 4

THE MEMORY SYSTEM

 BASICCONCEPTS:
 The maximum size of the Main Memory (MM) that can be
used in any computer is determined by its addressing scheme.
 For example, a 16-bit computer that generates 16-bit
addresses is capable of addressing up to 216 =64K memory
locations.
 If a machine generates 32-bit addresses, it can access up to
232 = 4G memory locations. This number represents the size
of address space of the computer.
 If the smallest addressable unit of information is a memory
word, the machine is called word-addressable.
 If individual memory bytes are assigned distinct addresses,
the computer is called byte-addressable.
 Most of the commercial machines are byte-addressable.
 For example in a byte-addressable 32-bit computer, each
memory word contains 4 bytes.
 A possible word-address assignment would be:
 Word Address Byte Address
0 0 1 2 3
4 4 5 6 7
8 8 9 10 11

. …..

. …..
. …..

•With the above structure a READ or WRITE may

involve an entire memory word or it may involve only
a byte.
• In the case of byte read, other bytes can also be
read but ignored by the CPU.
•However, during a write cycle, the control circuitry
of the MM must ensure that only the specified byte
is altered by sending 32 bit address.
•In this case, the higher-order 30 bits of address can
specify the word and the lower-order 2 bits can
specify the byte within the word.
CPU-Main Memory Connection – A block schematic: -

 Data transfer between CPU and MM takes place

through the use of two CPU registers, usually called
MAR (Memory Address Register) and MDR (Memory
Data Register).
 If MAR is K bits long and MDR is “n” bits long, then
the MM unit may contain upto 2k addressable
locations and each location will be “n” bits wide, while
the word length is equal to “n” bits.
 During a “memory cycle”, n bits of data may be
transferred between the MM and CPU.
 This transfer takes place over the processor bus,
which has k address lines (address bus), n data lines
(data bus) and control lines like Read, Write and
Memory Function completed (MFC) for coordinating
for byte transferred (control bus).
 For a read operation, the CPU loads the address into MAR, set
R/W to 1 and sets other control signals if required.
 The data from the MM is loaded into MDR and memory sets
MFC to 1.
 For a write operation, MAR, MDR are suitably loaded by the
CPU,R/W is set to 0 and other control signals are set suitably.
 The MM control circuitry loads the data into appropriate locations
and sets MFC to 1. This organization is shown in the following
block schematic.
 Some Basic Concepts
 Memory Access Times: -
 It is a useful measure of the speed of the memory unit.
 It is the time that elapses between the initiation of an
operation and the completion of that operation (for
example, the time between READ and MFC).
 Memory Cycle Time :-
 It is an important measure of the memory system.
 It is the minimum time delay required between the
initiations of two successive memory operations (for
example, the time between two successive READ
operations).
 The cycle time is usually slightly longer than the access
time.
 RAM:
 A memory unit is called a Random Access Memory if
any location can be accessed for a READ or WRITE
operation in some fixed amount of time that is
independent of the location’s address.
 Main memory units are of this type distinguishes them
from serial or partly serial access storage devices
such as magnetic tapes and disks which are used as
the secondary storage device.
 Cache Memory:-
Memory:-
 The CPU of a computer can usually process instructions and
data faster than they can be fetched from compatibly priced
main memory unit.
 Thus the memory cycle time becomes the bottleneck in the
system.
 One way to reduce the memory access time is to use cache
memory.
 This is a small and fast memory that is inserted between the
larger, slower main memory and the CPU.
 This holds the currently active segments of a program and its
data.
 Because of the locality of address references, the CPU
can, most of the time, find the relevant information in the
cache memory itself (cache hit) and infrequently needs
access to the main memory (cache miss) with suitable
size of the cache memory, cache hit rates of over 90%
are possible leading to a cost-effective increase in the
performance of the system.
 Memory Interleaving: -
 This technique divides the memory system into a
number of memory modules and arranges
addressing so that successive words in the address
space are placed in different modules.
 When requests for memory access involve
consecutive addresses, the access will be to different
modules. Since parallel access to these modules is
possible, the average rate of fetching words from the
Main Memory can be increased.
 Virtual Memory: -
 In a virtual memory System, the address generated by the
CPU is referred to as a virtual or logical address. The
corresponding physical address can be different and the
required mapping is implemented by a special memory
control unit, often called the memory management unit.
The mapping function itself may be changed during
program execution according to system requirements.
 Because of the distinction made between the logical
(virtual) address space and the physical address space;
while the former can be as large as the addressing
capability of the CPU, the actual physical memory can
be much smaller.
 Only the active portion of the virtual address space is
mapped onto the physical memory and the rest of the
virtual address space is mapped onto the bulk storage
device used.
 If the addressed information is in the Main Memory
(MM), it is accessed and execution proceeds.
 SEMICONDUCTOR RAM MEMORIES
 Internal Organization of Memory Chips
 Memory cells are usually organized in the form of an array,
in which each cell is capable of storing on bit of information.
 Each row of cells constitutes a memory word, and all cells of
a row are connected to a common line referred to as the
word line, which is driven by the address decoder on the
chip.
 The cells in each column are connected to a Sense/Write
circuit by two bit lines.
 The Sense/Write circuits are connected to the data I/O lines
of the chip.
 During the read operation, these circuits‟ sense, or read,
the information stored in the cells selected by a word line
and transmit this information to the output data lines.
 During the write operation, the Sense/Write circuits receive
the input information and store in the cells of the selected
word
 The above figure is an example of a very small memory
chip consisting of 16 words of 8 bits each.
 16 8 organization.
This is referred to as a 16×8
 The data input and the data output of each sense/Write
circuit are connected to a single bidirectional data line
that can be connected to the data bus of a computer.
 Two control lines, R/W (Read/ Write) input specifies the
required operation, and the CS (Chip Select) input
selects a given chip in a multichip memory system
 The memory circuit given above stores 128 bits and
requires 14 external connections for address, data
and control lines.
 Of course, it also needs two lines for power supply
and ground connections.
 Consider now a slightly larger memory circuit, one that
has a 1k (1024) memory cells.
 1k 1 memory organization, the representation is
For a 1k×1
given next.
 The required 10-bit address is divided into two groups
of 5 bits each to form the row and column addresses
for the cell array
 A row address selects a row of 32 cells, all of which
are accessed in parallel.
 However, according to the column address, only one
of these cells is connected to the external data line by
the output multiplexer and input de- multiplexer.
Static Memories

 Memories that consist of circuits capable of

retaining their state as long as power is applied are
known as static memories.
 b b‘

X Y

Word line
Bit lines

 Basic Static RAM cell illustration

 The above figure illustrates how a static RAM
(SRAM) cell may be implemented.
 Two inverters are cross- connected to form a
latch. The latch is connected to two bit lines by
transistors T1 and T2.
 These transistors act as switches that can be
opened or closed under control of the word
line.
 When the word line is at ground level, the
transistors are turned off and the latch retains
its state.
 For example, let us assume that the cell is in
state 1 if the logic value at point X is 1 and at
point Y is 0.
 This state is maintained as long as the signal
on the word line is at ground level.
Read Operation
 In order to read the state of the SRAM cell, the
word line is activated to close switches T1and T2.
 If the cell is in state 1, the signal on the bit line b is
high and the signal on the bit line b’ is low. The
opposite is true if the cell is in state 0.
 Thus b and b’ are compliments of each other.
Sense/Write circuits at the end of the bit lines
monitor the state of b and b’ and set the output
accordingly.
Write Operation
 The state of the cell is set by placing the
appropriate value on bit line b and its complement
b’, and then activating the word line.
 This forces the cell into the corresponding state.
 The required signals on the bit lines are generated
by the Sense/Write circuit.
CMOS Cell
 A CMOS realization of the static RAM cell is given
below:
 Transistor pairs (T3, T5) and (T4, T6) form the
inverters in the latch (see Appendix A).
 The state of the cell is read or written as just
explained.
 For example, in state 1, the voltage at point X is
maintained high by having transistors T3and T6 on,
while T4 and T5 are off.
 Thus, if T1 and T2 are turned on(closed), bit lines b
and b’ will have high and low signals, respectively.
 As long as Vsupply = 5V or 3.3 V the cell will retain
its state. If power is interrupted, the cell content will
be lost.
 When power is restored, the latch will settle in to
stable state but it will not necessarily to the same
state when cell interrupted.
 Hence SRAM’s are Volatile memories.
 Major advantage of CMOS cell is their low power
consumption.
 Access time is few nanoseconds.
Asynchronous DRAMS

 Static RAM’s are fast, but expensive because of several

transistors utilization.
 To overcome this problem DRAMs are designed.
 Information is stored in a dynamic memory cell in the
form of a charge on a capacitor, and this charge can be
maintained for only tens of milliseconds.
 Since the cell is required to store information for a
much longer time, its contents must be periodically
refreshed by restoring the capacitor charge to its full
value.
 An example of a dynamic memory cell that consists of
a capacitor, C, and a transistor, T, is shown below:
Single transistor dynamic cell
 1T Dynamic cell contd….
 A sense amplifier connected to the bit line detects
whether the charge stored on the capacitor is above
the threshold.
 If so, it drives the bit line to a full voltage that
represents logic value 1.
 This voltage recharges the capacitor to full charge
that corresponds to logic value 1.
 If the sense amplifier detects that the charge on the
capacitor will have no charge, representing logic
value 0.
 Because of high density and low cost DRAMs are
most widely used in memory chips.
 A 16 - mega bit DRAM chip
 2M 8, is shown below.
Configured as 2M×8,
 Each row can store 512 bytes.
 12 bits to select a row, and 9 bits to select a group in a
row.
 Total of 21bits.
 First apply the row address; RAS signal latches
the row address. Then apply the column address,
CAS signal latches the address.
 Timing of the memory unit is controlled by a
specialized unit which generates RAS and CAS.
 This is asynchronous DRAM
16M bits DRAM Configuration

A20 – A9

A8 – A0
For Read or Write operation
 First Row address is applied, it is loaded into the row
address latch in response to RAS input to the chip.
 Then read operation is initiated, in which all selected
rows are read and refreshed.
 Shortly after the row address is loaded, the column
address is applied to the address pins and loaded in to
column address latch under CAS signal.
 Next this information makes appropriate group, 8 cells
for R/W will be selected by sense/Write circuit.
 If R/W =1,Information will transfer to Data Lines
 Otherwise, data on data lines(D0-D7) will write in to
selected Group cells.
 The timing in this circuit of the memory device is
controlled asynchronously through special memory
control circuit generates RAS and CAS.
 Fast Page Mode
 Suppose if we want to access the consecutive bytes in the
selected row.
 This can be done without having to reselect the row.
◦ Add a latch at the output of the sense circuits in each row.
 All the latches are loaded when the row is selected.
 Different column addresses can be applied to select and
place different bytes on the data lines.
 Consecutive sequence of column addresses can be applied
under the control signal CAS, without reselecting the row.
◦ Allows a block of data to be transferred at a much faster
rate than random accesses.
◦ A small collection/group of bytes is usually referred to as a
block.
 This transfer capability is referred to as the fast page mode
feature.
 Synchronous DRAMs
 Recently, In these DRAMs, operation is directly
synchronized with a clock signal. The below given
figure indicates the structure of an SDRAM.
SDRAM Contd
Contd…..
…..

 The output of each sense amplifier is connected to

a latch.
 A Read operation causes the contents of all cells in
the selected row to be loaded into these latches.
 But, if an access is made for refreshing purpose
only, it will not change the contents of these
latches; it will merely refresh the contents of the
cells.
 Data held in the latches that correspond to the
selected column(s) are transferred into the output
register, thus becoming available on the data
output pins.
 SDRAM contd
contd…..
…..
 SDRAMs have several different modes of operation,
which can be selected by writing control information
into a mode register.
 For example, burst operations of different lengths are
specified.
 The burst operations use the block transfer capability
described before as fast page mode feature.
 In SDRAMs, it is not necessary to provide externally
generated pulses on the CAS line to select successive
columns.
 The necessary control signals are provided internally
using a column counter and the clock signal.
 New data can be placed on the data lines in each clock
cycles. All actions are triggered by the rising edge of
the clock.
Timing Diagram
Timing diagram contd
contd….
….

The above figure shows the timing diagram for a
burst read of length 4.
◦ First, the row address is latched under control of the
RAS signal.
◦ Then, the column address latched under control of the
CAS signal.
◦ After a delay of one clock cycle, the first set of data bits
is placed on the data lines.
◦ The SDRAM automatically increments the column
address to access next three sets of the bits in the
selected row, which are placed on the data lines in the
next clock cycles.
◦ SDRAMs have built in refresh circuitry. A part of this circuitry is a
typical refresh counter, which provides the address of the rows
that are selected for refreshing
 Latency and Bandwidth
 The speed and efficiency of computer depends on
data(data words, blocks of data or data of a page )
transfer between memory and the disks.
 In turn, the speed and efficiency impacts the
performance of a computer system.
 Good performance of computer is defined using 2
parameters: Memory Latency and Bandwidth
 Memory latency is the time it(CPU) takes to transfer
a word of data to or from memory
 In case of burst mode of operation, rate at which
successive words transfer
 Memory bandwidth is the number of bits or bytes
that can be transferred in one second.
 Double Data Rate- Synchronous DRAMs
(DDR- SDRAMs)
 DDRSDRAMs- Cell array is organized in two
banks.
 To assist the processor in accessing data at high
enough rate, the cell array is organized in two
banks.
 Each bank can be accessed separately.
Consecutive words of a given block are stored in
different banks.
 Such interleaving of words allows simultaneous
access to two words that are transferred on the
successive edges of the clock.
 This type of SDRAM is called Double Data Rate
SDRAM (DDR-SDRAM).
 Semi-Conductor ROM Memories
 Semiconductor Read-Only Memory (ROM) units are
well suited as the control store components in micro
programmed processors and also as the parts of the
main memory that contain fixed programs or
data(hard disks). The following figure shows a
possible configuration for a bipolar ROM cell.
 The word line is normally held at a low voltage.
 If a word is to be selected, the voltage of the
corresponding word line is momentarily raised, which
causes all transistors whose emitters are connected
to their corresponding bit lines to be turned on.
 The current that flows from the voltage supply to the
bit line can be detected by a sense circuit.
 The bit positions in which current is detected are read
as 1s, and the remaining bits are read as 0’s.
 Therefore, the contents of a given word are
determined by the pattern of emitter to bit - line
connections similar configurations are possible in
MOS technology.
 PROM
 Data are written into a ROM at the time of
manufacturing providing programmable ROM (PROM)
devices allow the data to be loaded by the user.
 Programmability is achieved by connecting a fuse
between the emitter and the bit line. Thus, prior to
programming, the memory contains all 0’s.
 The user can inserts 1’s at the required locations by
burning out the fuses at these locations using high-
current pulses.
 This process is irreversible.
 ROMs are attractive when high production volumes
are involved.
 For smaller numbers, PROMs provide a faster and
considerably less expensive approach.
 EPROM
 Chips which allow the stored data to be erased and new
data to be loaded.
 Such a chip is an erasable, programmable ROM,
usually called an EPROM.
 It provides considerable flexibility during the
development phase.
 An EPROM cell bears considerable resemblance to the
dynamic memory cell.
 As in the case of dynamic memory, information is stored
in the form of a charge on a capacitor.
 The main difference is that the capacitor in an EPROM
cell is very well insulated.
 Its rate of discharge is so low that it retains the stored
information for very long periods.
 EPROM
 To write information, allowing charge to be stored on
the capacitor.
 The contents of EPROM cells can be erased by
increasing the discharge rate of the storage capacitor
by several orders of magnitude. This can be
accomplished by allowing ultraviolet light into the chip
through a window provided for that purpose, or by the
application of a high voltage similar to that used in a
write operation.
 If ultraviolet light is used, all cells in the chip are
erased at the same time.
 When electrical erasure is used, however, the process
can be made selective.
 EEPROM
 An electrically erasable EPROM, often referred to as
EEPROM.
 However, the circuit must now include high voltage
generation.
 Some EEPROM chips incorporate the circuitry for
generating these voltages o the chip itself.
 Depending on the requirements, suitable device can
be selected.
 Flash memory:
 Has similar approach to EEPROM.
 Read the contents of a single cell, but write the
contents of an entire block of cells.
 Flash devices have greater density.
 Higher capacity and low storage cost per bit.
 Power consumption of flash memory is very low,
making it attractive for use in equipment that is battery-
driven.
 Single flash chips are not sufficiently large, so larger
memory modules are implemented using flash cards
and flash drives.
 Speed, Size and Cost
 A big challenge in the design of a computer system is
to provide a sufficiently large memory, with a
reasonable speed at an affordable cost.
 Static RAM: Very fast, but expensive, because a
basic SRAM cell has a complex circuit making it
impossible to pack a large number of cells onto a
single chip.
 Dynamic RAM: Simpler basic cell circuit, hence are
much less expensive, but significantly slower than
SRAMs.
 Magnetic disks: Storage provided by DRAMs is
higher than SRAMs, but is still less than what is
necessary. Secondary storage such as magnetic
disks provides a large amount of storage, but is much
slower than DRAMs.
 Cache memories
 Processor is much faster than the main memory.
 As a result, the processor has to spend much of its
time waiting while instructions and data are being
fetched from the main memory.
 This serves as a major obstacle towards achieving
good performance.
 Speed of the main memory cannot be increased
beyond a certain point.
 So we use Cache memories.
 Cache memory is an architectural arrangement which
makes the main memory appear faster to the
processor than it really is.
 Cache memory is based on the property of computer
programs known as “locality of reference”.
 Analysis of programs indicates that many
instructions in localized areas of a program are
executed repeatedly during some period of time,
while the others are accessed relatively less
frequently.
 These instructions may be the ones in a loop,
nested loop or few procedures calling each other
repeatedly. This is called “locality of reference”.
 Its types are:
 Temporal locality of reference: Recently
executed instruction is likely to be executed again
very soon.
 Spatial locality of reference: Instructions with
addresses close to a recently instruction are likely
to be executed soon.
 A simple arrangement of cache memory is as shown
above.
 Processor issues a Read request, a block of words is
transferred from the main memory to the cache, one word
at a time.
 Subsequent references to the data in this block of words
are found in the cache.
 At any given time, only some blocks in the main memory
are held in the cache. Which blocks in the main memory
are in the cache is determined by a “mapping function”.
 When the cache is full, and a block of words needs to be
transferred from the main memory, some block of words in the
cache must be replaced. This is determined by a “replacement
algorithm”.
 Cache hit:
 Existence of a cache is transparent to the processor.
The processor issues Read and Write requests in
the same manner. If the data is in the cache, it is
called a Read or Write hit.
 Read hit: The data is obtained from the cache.
 Write hit: Cache has a replica of the contents of the
main memory. Contents of the cache and the main
memory may be updated simultaneously. This is the
write-through protocol.
 Update the contents of the cache, and mark it as
updated by setting a bit known as the dirty bit or
modified bit. The contents of the main memory are
updated when this block is replaced. This is write-
back or copy-back protocol.
 Cache miss:
 If the data is not present in the cache, then a Read
miss or Write miss occurs.
 Read miss: Block of words containing this requested
word is transferred from the memory. After the block is
transferred, the desired word is forwarded to the
processor. The desired word may also be forwarded
to the processor as soon as it is transferred without
waiting for the entire block to be transferred. This is
called load-through or early-restart.
 Write-miss: Write-through protocol is used, then the
contents of the main memory are updated directly. If
write-back protocol is used, the block containing the
addressed word is first brought into the cache. The
desired word is overwritten with new information.
 Cache Coherence Problem:
 A bit called as “valid bit” is provided for each block. If
the block contains valid data, then the bit is set to 1,
else it is 0. Valid bits are set to 0, when the power is
just turned on.
 When a block is loaded into the cache for the first
time, the valid bit is set to 1. Data transfers between
main memory and disk occur directly bypassing the
cache. When the data on a disk changes, the main
memory block is also updated. However, if the data is
also resident in the cache, then the valid bit is set to 0.
 The copies of the data in the cache, and the main
memory are different. This is called the cache
coherence problem
 Mapping functions:
 Mapping functions determine how memory
blocks are placed in the cache.
 A simple processor example:
 Cache consisting of 128 blocks of 16 words
each.
 Total size of cache is 2048 (2K)words.
 Main memory is addressable by a 16-bit address.
 Main memory has 64K words.
 Main memory has 4K blocks of 16 words each.
 Three mapping functions can be used.
 Direct mapping
 Associative mapping
 Set-associative mapping.
Direct Mapping
◦ Block j of the main memory maps to j modulo 128 of the
cache. 0 maps to 0, 129 maps to 1.
◦ More than one memory block is mapped on to the same
position in the cache.
◦ May lead to contention for cache blocks even if the cache
is not full. Resolve the contention by allowing new block
to replace the old block, leading to a trivial replacement
algorithm.
◦ Memory address is divided into three fields:
 Low order 4 bits determine one of the16 words in a block.
 When a new block is brought into the cache, the next 7
bits determine which cache block this new block is placed
in.
 High order 5 bits determine which of the possible 32
blocks is currently present in the cache. These are tag
bits.
 Simple to implement but not very flexible
Associate Mapped Cache
 Associative mapped memory
 Main memory block can be placed into any cache
position.
 Memory address is divided into two fields:
 Low order 4 bits identify the word with in a block. High
order 12 bits or tag bits identify a memory block when
it is resident in the cache.
 Flexible, and uses cache space efficiently.
 Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
 Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Set Associative Memory Mapping
 Blocks of cache are grouped into sets. Mapping function
allows a block of the main memory to reside in any block of a
specific set.
 Divide the cache into 64 sets, with two blocks per set.
Memory block 0,64,128 etc. map to block 0, and they can
occupy either of the two positions.
 Memory address is divided into three fields:
 6 bit field determines the set number.
 High order 6 bit fields are compared to the tag fields of the
two blocks in a set.
 Set-associative mapping combination of direct and
associative mapping.
 Number of blocks per set is a design parameter. One
extreme is to have all the blocks in one set, requiring no set
bits (fully associative mapping).
 Other extreme is to have one block per set, is the same as
direct mapping
 Solved Problems:-
Problems:-
 A block set associative cache consists of a total of 64
blocks divided into 4 block sets. The MM contains 4096
blocks each containing 128 words.
 How many bits are there in MM address?
 How many bits are there in each of the TAG, SET & word
fields
 Solution:- Number of sets = 64/4 =16
 Set bits = 4(24 = 16) Number of words = 128
 Word bits = 7 bits (27 =128)
 MM capacity : 4096 x 128 (212 x 27 = 219)
 Number of bits in memory address = 19bits
 B) 8 4 7

TAG SET WORD

 TAG bits = 19 – (7+4) = 8 bits.
 Problem 2
 A computer system has a MM capacity of a total of 1M
16 bits words. It also has a 4K words cache organized
in the block set associative manner, with 4 blocks per
set & 64 words per block. Calculate the number of bits
in each of the TAG, SET & WORD fields of MM
address format.
 Solution: Capacity: 1M (220 = 1M) Number of words
per block = 64 Number of blocks in cache = 4k/64 =64
 Number of sets = 64/4 = 16
 Set bits = 4 (24 = 16)
 Word bits = 6 bits (26 = 64) Tag bits = 20-(6+4) = 10
bits
 MM address format: 10 tag bits, 6 word bits and 4 set
bits.
 Virtual Memory
 An important challenge in the design of a computer system is to
provide a large, fast memory system at an affordable cost.
 Cache memories were developed to increase the effective speed
of the memory system. Virtual memory is an architectural solution
to increase the effective size of the memory system.
 The addressable memory space depends on the number of
address bits in a computer.
 For example, if a computer issues 32-bit addresses, the
addressable memory space is 4G bytes.
 Physical main memory in a computer is generally not as large as
the entire possible addressable space.
 Physical memory typically ranges from a few hundred megabytes
to 1G bytes.
 Large programs that cannot fit completely into the main memory
have their parts stored on secondary storage devices such as
magnetic disks.
 Pieces of programs must be transferred to the main memory from
secondary storage before they can be executed.
 Virtual Memory
 Techniques that automatically move program and data
between main memory and secondary storage when they
are required for execution are called virtual-memory
techniques.
 Programs and processors reference an instruction or data
independent of the size of the main memory.
 Processor issues binary addresses for instructions and
data.
 These binary addresses are called logical or virtual
addresses.
 Virtual addresses are translated into physical addresses by
a combination of hardware and software subsystems.
 If virtual address refers to a part of the program that is
currently in the main memory, it is accessed immediately.
 If the address refers to a part of the program that is not
currently in the main memory, it is first transferred to the
main memory before it can be used.
Virtual Memory
 Memory management unit (MMU) translates virtual
addresses into physical addresses.
 If the desired data or instructions are in the main
memory they are fetched as described previously.
 If the desired data or instructions are not in the main
memory, they must be transferred from secondary
storage to the main memory.
 MMU causes the operating system to bring the data
from the secondary storage into the main memory.
 Address Translation
 Assume that program and data are composed of fixed-
length units called pages.
 A page consists of a block of words that occupy
contiguous locations in the main memory.
 Page is a basic unit of information that is transferred
between secondary storage and main memory.
 Size of a page commonly ranges from 2K to 16K
bytes.
 Pages should not be too small, because the access
time of a secondary storage device is much larger
than the main memory.
 Pages should not be too large, else a large portion of
the page may not be used, and it will occupy valuable
space in the main memory.
 Concepts of virtual memory are similar to the concepts of cache
memory.
 Cache memory: Introduced to bridge the speed gap between
the processor and the main memory. Implemented in hardware.
 Virtual memory: Introduced to bridge the speed gap between
the main memory and secondary storage. Implemented in part
by software.
 Each virtual or logical address generated by a processor is
interpreted as a virtual page number (high-order bits) plus an
offset (low-order bits) that specifies the location of a particular
byte within that page.
 Information about the main memory location of each page is kept
in the page table. Main memory address where the page is
stored.
 Current status of the page. Area of the main memory that can
hold a page is called as page frame. Starting address of the
page table is kept in a page table base register.
 Virtual page number generated by the processor is added to the
contents of the page table base register.
 This provides the address of the corresponding entry in the
page table. The contents of this location in the page table give
the starting address of the page if the page is currently in the
main memory.
 Page table entry for a page also includes some control
bits which describe the status of the page while it is in the
main memory.
 One bit indicates the validity of the page.
 Indicates whether the page is actually loaded into the
main memory. Allows the operating system to invalidate
the page without actually removing it.
 One bit indicates whether the page has been modified
during its residency in the main memory.
 This bit determines whether the page should be written
back to the disk when it is removed from the main
memory.
 Similar to the dirty or modified bit in case of cache
memory. Other control bits for various other types of
restrictions that may be imposed.
 For example, a program may only have read permission
for a page, but not write or modify permissions.
 The page table is used by the MMU for every read
and write access to the memory. Ideal location for the
page table is within the MMU.
 Page table is quite large.
 MMU is implemented as part of the processor chip.
Impossible to include a complete page table on the
chip.
 Page table is kept in the main memory. A copy of a
small portion of the page table can be accommodated
within the MMU. Portion consists of page table entries
that correspond to the most recently accessed pages.
 Secondary Storage:
Magnetic Disk Drives: Hard disk Drive organization:
 The modern hard disk drive is a system in itself. It contains
not only the disks that are used as the storage medium and
the read write heads that access the raw data encoded on
them, but also the signal conditioning circuitry and the
interface electronics that separate the system user from the
details & getting bits on and off the magnetic surface.
 The drive has 4 platters with read/write heads on the top
and bottom of each platter. The drive rotates at a constant
3600rpm.
 Platters and Read/Write Heads: -
 The heart of the disk drive is the stack of rotating platters
that contain the encoded data, and the read and write
heads that access that data.
 The drive contains five or more platters.
 There are read/write heads on the top and bottom of each
platter, so information can be recorded on both surfaces.
 All heads move together across the platters.
 The platters rotate at constant speed usually 3600 rpm.