Mecha Unit II
Mecha Unit II
ENGINEERING COLLEGE
(AUTONOMOUS)
RSM Nagar, Kavaraipettai – 601206
diagram
Introduction
A Microprocessor is an important part of a computer architecture
without which you will not be able to perform anything on your
computer.
It is a programmable device that takes in input perform some
arithmetic and logical operations over it and produce desired output.
In simple words, a Microprocessor is a digital device on a chip which
can fetch instruction from memory, decode and execute them and give
results.
Definition
A microcontroller is
• a small and low-cost microcomputer,
• designed to perform the specific tasks of embedded systems like
displaying microwave’s information, receiving remote signals, etc.
The general microcontroller consists of
• the processor
• the memory (RAM, ROM, EPROM)
• Serial ports
• peripherals (timers, counters), etc.
Microcontroller
Microcontroller Microprocessor
Microcontrollers are used to execute Microprocessors are used for big
a single task within an application. applications.
Its designing and hardware cost is Its designing and hardware cost is
low. high.
Easy to replace. Not so easy to replace.
It is built with CMOS
(Complementary Metal Oxide Its power consumption is high because
Semiconductor) technology, which it has to control the entire system.
requires less power to operate.
It doesn’t consist of RAM, ROM, I/O
It consists of CPU, RAM, ROM, I/O
ports. It uses its pins to interface to
ports.
peripheral devices.
Parts of a Microprocessor
How does a Microprocessor Work?
Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.
Arithmetic and logic unit
It performs arithmetic and logical operations like Addition, Subtraction, AND, OR,
etc. on 8-bit data.
General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is
like B-C, D-E & H-L.
8085 µP – Functional Units
Program counter
It is a 16-bit register used to store the memory address location of the next
instruction to be executed. Microprocessor increments the program whenever
an instruction is being executed, so that the program counter points to the
memory address of the next instruction that is going to be executed.
Stack pointer
It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
8085 µP – Functional Units
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1
depending upon the result stored in the accumulator.
These are the set of 5 flip-flops −
Sign (S)
Zero (Z)
Bit position
Auxiliary Carry (AC)
Parity (P) D7 D6 D5 D4 D3 D2 D1 D0
Carry (C) S Z AC P CY
8085 µP – Functional Units
Instruction register and decoder
It is an 8-bit register. When an instruction is fetched from memory
then it is stored in the Instruction register. Instruction decoder decodes
the information present in the Instruction register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform
operations. Following are the timing and control signals, which control
external and internal circuits −
Control Signals : READY, RD’, WR’, ALE
Status Signals : S0, S1, IO/M’
DMA Signals : HOLD, HLDA
RESET Signals : RESET IN, RESET OUT
8085 µP – Functional Units
Interrupt control
As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs, the
microprocessor shifts the control from the main program to process the incoming
request. After the request is completed, the control goes back to the main program.
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8085 µP – Pin Configuration
Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
Control and status signals
These signals are used to identify the nature of operation. There are 3 control signal and 3
status signals.
Three control signals are RD, WR & ALE.
RD − This signal indicates that the selected IO or memory device is to be read and is ready
for accepting data available on the data bus.
WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes down it
indicates data. 31
8085 µP – Pin Configuration
Three status signals are IO/M, S0 & S1.
IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it
is high indicates IO operation and when it is low then it indicates memory
operation.
S1 & S0
These signals are used to identify the type of current operation.
Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply
and VSS indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.
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8085 µP – Pin Configuration
Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST
7.5, RST 6.5, RST 5.5, and INTR.
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8085 µP – Pin Configuration
HOLD − This signal indicates that another master is requesting the use of the
address and data buses.
HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low
after the HOLD signal is removed.
Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.
SOD (Serial output data line) − The output SOD is set/reset as specified by the
SIM instruction.
SID (Serial input data line) − The data on this line is loaded into accumulator
whenever a RIM instruction is executed.
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Interrupts in 8085 µP
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task.
There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts.
By default, it is enabled until it gets acknowledged. In case of failure, it executes as
ISR and sends the data to backup memory. This interrupt transfers the control to
the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 003CH address.
35
Interrupts in 8085 µP
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 0034H address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can
be disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
The microprocessor checks the status of INTR signal during the execution of each
instruction.
When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
When instructions are received, then the microprocessor saves the address of the
next instruction on stack and executes the received instruction.
36
Interrupts in 8085 µP
Non-Vector interrupt
In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device
to perform interrupts. For example: INTR.
Maskable interrupt
In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
37
Interrupts in 8085 µP
Non-Maskable interrupt
In this type of interrupt, we cannot disable the interrupt by writing
some instructions into the program. For example: TRAP.
Software interrupt
In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts
in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
Hardware interrupt
There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
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Opcodes and Operands
39
Addressing Modes in 8085
These are the instructions used to transfer the data from one register to
another register, from the memory to the register, and from the register to
the memory without any alteration in the content. Addressing modes in
8085 is classified into 5 groups
40
Addressing Modes in 8085
41
Addressing Modes in 8085
42
Instruction Sets in 8085
Instruction sets are instruction codes to perform some task. It is classified into
five categories.
1. Data-transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branching instructions
46
Instruction Sets in 8085
Data-transfer instructions
Opcode Operand Meaning Explanation
The contents of register H are
exchanged with the contents of
Exchange H and Lregister D, and the contents of register
XCHG None
with D and E L are exchanged with the contents of
register E.
Example − XCHG
The instruction loads the contents of
the H and L registers into the stack
Copy H and Lpointer register. The contents of the H
SPHL None registers to the stackregister provide the high-order
pointer address and the contents of the L
register provide the low-order address.
Example − SPHL
47
Instruction Sets in 8085
Data-transfer instructions
Opcode Operand Meaning Explanation
The contents of the L register are exchanged
with the stack location pointed out by the
Exchange H
contents of the stack pointer register.
XTHL None and L with
The contents of the H register are exchanged
top of stack
with the next stack location (SP+1).
Example − XTHL
The contents of the register pair designated in
the operand are copied onto the stack in the
following sequence.
Push theThe stack pointer register is decremented and
register pairthe contents of the high order register (B, D, H,
PUSH Reg. pair
onto theA) are copied into that location.
stack The stack pointer register is decremented again
and the contents of the low-order register (C, E,
L, flags) are copied to that location.
Example − PUSH K
48
Instruction Sets in 8085
Data-transfer instructions
Opcode Operand Meaning Explanation
The contents of the memory location
pointed out by the stack pointer register
are copied to the low-order register (C, E,
L, status flags) of the operand.
Pop off stack to the
POP Reg. pair The stack pointer is incremented by 1
register pair and the contents of that memory location
are copied to the high-order register (B,
D, H, A) of the operand.
Example − POPK
Output the data from The contents of the accumulator are
8-bit port the accumulator to a copied into the I/O port specified by the
OUT operand.
address port with 8bit
address Example − OUT K9L
Input data to The contents of the input port designated
8-bit port accumulator from a in the operand are read and loaded into
IN the accumulator.
address port with 8-bit
address Example − IN5KL
49
Instruction Sets in 8085
Arithmetic instructions
Opcode Operand Meaning Explanation
The contents of the register or memory
Add register orare added to the contents of the
R
ADD memory, to theaccumulator and the result is stored in
M
accumulator the accumulator.
Example − ADD K.
The contents of the register or memory
Add register to the& M the Carry flag are added to the
R
ADC accumulator withcontents of the accumulator and the
M
carry result is stored in the accumulator.
Example − ADC K
The 8-bit data is added to the contents of
Add the immediatethe accumulator and the result is stored
ADI 8-bit data
to the accumulator in the accumulator.
Example − ADI 55K
50
Instruction Sets in 8085
Arithmetic instructions
Opcode Operand Meaning Explanation
The 8-bit data and the Carry flag are
Add the immediateadded to the contents of the accumulator
ACI 8-bit data to the accumulatorand the result is stored in the
with carry accumulator.
Example − ACI 55K
The instruction stores 16-bit data into
Reg. pair, Load the registerthe register pair designated in the
LXI
16bit data pair immediate operand.
Example − LXI K, 3025M
The 16-bit data of the specified register
Add the register
pair are added to the contents of the HL
DAD Reg. pair pair to H and L
register.
registers
Example − DAD K
51
Instruction Sets in 8085
Arithmetic instructions
Opcode Operand Meaning Explanation
The contents of the register or the
Subtract the
memory are subtracted from the
R register or the
SUB contents of the accumulator, and the
M memory from theresult is stored in the accumulator.
accumulator Example − SUB K
The contents of the register or the
memory & M the Borrow flag are
Subtract the source
R subtracted from the contents of the
SBB and borrow from
M accumulator and the result is placed in
the accumulator the accumulator.
Example − SBB K
The 8-bit data is subtracted from the
Subtract the
contents of the accumulator & the result
SUI 8-bit data immediate from the
is stored in the accumulator.
accumulator Example − SUI 55K
52
Instruction Sets in 8085
Arithmetic instructions
Opcode Operand Meaning Explanation
The contents of register H are exchanged
Subtract the
with the contents of register D, and the
immediate from the
SBI 8-bit data contents of register L are exchanged
accumulator with
with the contents of register E.
borrow
Example − XCHG
The contents of the designated register
Increment the
R or the memory are incremented by 1 and
INR register or the
M their result is stored at the same place.
memory by 1
Example − INR K
The contents of the designated register
Increment registerpair are incremented by 1 and their
INX R
pair by 1 result is stored at the same place.
Example − INX K
53
Instruction Sets in 8085
Arithmetic instructions
Opcode Operand Meaning Explanation
The contents of the designated register or
Decrement the
R memory are decremented by 1 and their
DCR register or the
M result is stored at the same place.
memory by 1
Example − DCR K
The contents of the designated register
Decrement thepair are decremented by 1 and their result
DCX R
register pair by 1 is stored at the same place.
Example − DCX K
The contents of the accumulator are
Decimal adjustchanged from a binary value to two 4-bit
DAA None
accumulator BCD digits.
Example − DAA
54
Instruction Sets in 8085
Logical instructions
Opcode Operand Meaning Explanation
Compare the
The contents of the operand (register or
R register or
CMP memory) are M compared with the
M memory with the
contents of the accumulator.
accumulator
Compare
The second byte data is compared with the
CPI 8-bit data immediate with
contents of the accumulator.
the accumulator
Logical AND The contents of the accumulator are
R register or logically AND with M the contents of the
ANA
M memory with the register or memory, and the result is placed
accumulator in the accumulator.
Logical AND The contents of the accumulator are
ANI 8-bit data immediate with logically AND with the 8-bit data and the
the accumulator result is placed in the accumulator.
55
Instruction Sets in 8085
Logical instructions
Opcode Operand Meaning Explanation
Exclusive OR The contents of the accumulator are
R register or Exclusive OR with M the contents of the
XRA
M memory with the register or memory, and the result is placed
accumulator in the accumulator.
Exclusive OR The contents of the accumulator are
XRI 8-bit data immediate with Exclusive OR with the 8-bit data and the
the accumulator result is placed in the accumulator.
Logical OR The contents of the accumulator are
R register or logically OR with M the contents of the
ORA
M memory with the register or memory, and result is placed in
accumulator the accumulator.
Logical OR The contents of the accumulator are
ORI 8-bit data immediate with logically OR with the 8-bit data and the
the accumulator result is placed in the accumulator.
56
Instruction Sets in 8085
Logical instructions
Opcode Operand Meaning Explanation
Each binary bit of the accumulator is
Rotate the rotated left by one position. Bit D7 is placed
RLC None
accumulator left in the position of D0 as well as in the Carry
flag. CY is modified according to bit D7.
Each binary bit of the accumulator is
Rotate the rotated right by one position. Bit D0 is
RRC None accumulator placed in the position of D7 as well as in the
right Carry flag. CY is modified according to bit
D0.
Each binary bit of the accumulator is
rotated left by one position through the
Rotate the
Carry flag. Bit D7 is placed in the Carry
RAL None accumulator left
flag, and the Carry flag is placed in the least
through carry
significant position D0. CY is modified
according to bit D7.
57
Instruction Sets in 8085
Logical instructions
Opcode Operand Meaning Explanation
Each binary bit of the accumulator is
Rotate the rotated right by one position through the
accumulator Carry flag. Bit D0 is placed in the Carry
RAR None
right through flag, and the Carry flag is placed in the
carry most significant position D7. CY is
modified according to bit D0.
Complement The contents of the accumulator are
CMA None
accumulator complemented. No flags are affected.
Complement The Carry flag is complemented. No other
CMC None
carry flags are affected.
STC None Set Carry Set Carry
58
Instruction Sets in 8085
Branching instructions
Opcode Operand Meaning Explanation
The program sequence is transferred
16-bit Jump
JMP to the memory address given in the
address unconditionally
operand.
Opcode Description Flag Status Opcode Description Flag Status
Jump on Jump on no
JC CY=1 JNZ Z=0
Carry zero
Jump on no Jump on
JNC CY=0 JPE P=1
Carry parity even
Jump on Jump on
JP S=0 JPO P=0
positive parity odd
Jump on
JM S=1 16-bit address Jump conditionally
minus
Jump on zero Z=1 The program sequence is transferred to the
JZ
memory address given in the operand
based on the specified flag of the PSW.
59
Instruction Sets in 8085
Branching instructions
Opcode Description Flag
Status
The program
CC Call on Carry CY=1 sequence is
CNC Call on no Carry CY=0 transferred to the
Call on positive memory address given
CP S=0 Uncondition
16-bit in the operand. Before
CM Call on minus S=1 al subroutine
address transferring, the
call
CZ Call on zero Z=1 address of the next
Call on no zero instruction after
CNZ Z=0
CALL is pushed onto
CPE Call on parity even P=1 the stack.
CPO Call on parity odd P=0
60
Instruction Sets in 8085
Branching instructions
Opcode Description Flag Status
RC Return on Carry CY=1
Return on no The program
RNC CY=0
Carry sequence is
RP Return on positive S=0 transferred from the
subroutine to the
RM Return on minus S=1 Return from calling program
RZ Return on zero Z=1 None subroutine based on the
conditionally specified flag of the
RNZ Return on no zero Z=0
PSW and the
Return on parity program execution
RPE P=1 begins at the new
even
Return on parity address.
RPO P=0
odd
61
Instruction Sets in 8085
Branching instructions
The contents of registers H & L are copied into
Load the program
the program counter. The contents of H are
PCHL None counter with HL
placed as the high-order byte and the contents
contents
of L as the low order byte.
Instruction Restart Address
RST 0 0000H
RST 0-7 Restart RST 1 0008H
RST 2 0010H
The RST instruction is used as RST 3 0018H
software instructions in a program
RST 4 0020H
to transfer the program execution to
one of the following eight locations. RST 5 0028H
RST 6 0030H
RST 7 0038H
62
Instruction Sets in 8085
Control instructions
Opcode Operand Meaning Explanation
No operation is performed, i.e., the
NOP None No operation
instruction is fetched and decoded.
The CPU finishes executing the current
Halt and enter instruction and stops further execution. An
HLT None
wait state interrupt or reset is necessary to exit from the
halt state.
Disable The interrupt enable flip-flop is reset and all
DI None
interrupts the interrupts are disabled except TRAP.
Enable The interrupt enable flip-flop is set and all
EI None
interrupts the interrupts are enabled.
This instruction is used to read the status of
Read interrupt
RIM None interrupts 7.5, 6.5, 5.5 and read serial data
mask
input bit.
Set interrupt This instruction is used to implement the
SIM None
mask interrupts 7.5, 6.5, 5.5, and serial data output.
63
Timing diagram of 8085 µP
one of the best way to understand to process of micro-processor/controller
step by step working of each instruction and its execution, etc.
It is the graphical representation of process in steps with respect to time.
The timing diagram represents
• the clock cycle and duration,
• delay,
• content of address bus and data bus,
• type of operation ie. Read/write/status signals.
Instruction cycle
This term is defined as the number of steps required by the CPU to complete the
entire process ie. Fetching and execution of one instruction. The fetch and execute
cycles are carried out in synchronization with the clock.
Machine cycle
It is the time required by the microprocessor to complete the operation of
accessing the memory devices or I/O devices. In machine cycle various operations
like opcode fetch, memory read, memory write, I/O read, I/O write are performed.
T-state
Each clock cycle is called as T-states.
64
Timing diagram of 8085 µP
No. of
Machine Machine Machine Machine
Instruction machine
cycle - 1 cycle - 2 cycle - 3 cycle - 4
cycles
MOV A,B 1 OF - - -
MVI A, 50H 2 OF MR - -
LDA 5000H 4 OF MR MR MR
STA 5000H 4 OF MR MR MW
IN 80H 3 OF MR IOR -
67
Timing diagram of 8085 µP
Opcode Fetch (OF)
In order to fetch the Opcode from memory, the first 3 T-states are used. The
remaining T-state is used for internal operations by the microprocessor.
68
Timing diagram of 8085 µP
Opcode Fetch (OF)
S. No T state Operation
The microprocessor places the higher order 8-bits of the memory
1 address on A15 – A8 address bus and the lower order 8-bits of
the memory address on AD7 – AD0 address / data bus.
The microprocessor makes the ALE signal HIGH and at the
2 T1
middle of T1 state, ALE signal goes LOW.
The status signals are changed as IO/𝑀’ = 0, S1 =1 and S0 = 1.
3 These status signals do not change throughout the OF machine
cycle.
The microprocessor makes the RD’ line LOW to enable memory
4
read and increments the Program Counter.
T2
The contents on D7 – D0 (i.e. the Opcode) are placed on the
5
address / data bus.
The microprocessor transfers the Opcode on the address / data
6
bus to Instruction Register (IR).
T3
The microprocessor makes the RD’ line HIGH to disable memory
7
read.
8 T4 The microprocessor decodes the instruction.
69
Timing diagram of 8085 µP
Memory Read Machine Cycle
The MR machine cycle takes 3 T-states.
70
Timing diagram of 8085 µP
Memory Read Machine Cycle
S. No T state Operation
The microprocessor places the higher order 8-bits of the memory
1 address on A15 – A8 address bus and the lower order 8-bits of the
memory address on AD7 – AD0 address / data bus.
The microprocessor makes the ALE signal HIGH and at the middle
2 T1
of T1 state, ALE signal goes LOW.
The status signals are changed as IO/𝑀’ = 0, S1 =1 and S0 = 0. These
3 status signals do not change throughout the memory read machine
cycle.
The microprocessor makes the RD’ line LOW to enable memory
4
read and increments the Program Counter.
T2
The contents on D7 – D0 (i.e. the data) are placed on the address /
5
data bus.
The data loaded on the address / data bus is moved to the
6
microprocessor.
T3
The microprocessor makes the RD’ line HIGH to disable the
7
memory read operation.
71
Timing diagram of 8085 µP
Memory Write Machine Cycle
The MW machine cycle takes 3 T-states.
72
Timing diagram of 8085 µP
Memory Write Machine Cycle
S. No T state Operation
The microprocessor places the higher order 8-bits of the memory
1 address on A15 – A8 address bus and the lower order 8-bits of the
memory address on AD7 – AD0 address / data bus.
T1 The microprocessor makes the ALE signal HIGH and at the middle
2
of T1 state, ALE signal goes LOW.
The status signals are changed as IO/𝑀’ = 0, S1 =0 and S0 = 1. These
3 status signals do not change throughout the memory write machine
cycle.
The microprocessor makes the 𝑊𝑅’ line LOW to enable memory
4
write.
T2
The contents of the specified register are placed on the address /
5
data bus.
The data placed on the address / data bus is transferred to the
6
specified memory location.
T3
The microprocessor makes the 𝑊𝑅’ line HIGH to disable the
7
memory write operation.
73
Timing diagram of 8085 µP
I/O Read Machine Cycle
The IOR machine cycle takes 3 T-states.
74
Timing diagram of 8085 µP
I/O Read Machine Cycle
S. No T state Operation
The microprocessor places the address of the I/O port specified in
1 the instruction on A15 – A8 address bus and also on AD7 – AD0
address / data bus.
The microprocessor makes the ALE signal HIGH and at the middle
2 T1
of T1 state, ALE signal goes LOW.
The status signals are changed as IO/𝑀’ = 0, S1 =1 and S0 = 0. These
3 status signals do not change throughout the I/O read machine cycle.
4 The microprocessor makes the 𝑅𝐷’ line LOW to enable I/O read.
T2 The contents on D7 – D0 (i.e. the data) are placed on the address /
5
data bus.
The data loaded on the address / data bus is moved to the
6 microprocessor ie., to the accumulator.
T3
The microprocessor makes the 𝑅𝐷’ line HIGH to disable the I/O read
7
operation.
75
Timing diagram of 8085 µP
I/O Write Machine Cycle
The IOW machine cycle takes 3 T-states.
76
Timing diagram of 8085 µP
I/O Write Machine Cycle
S. No T state Operation
The microprocessor places the address of the I/O port specified in
1 the instruction on A15 – A8 address bus and also on AD7 – AD0
address / data bus.
T1 The microprocessor makes the ALE signal HIGH and at the middle
2
of T1 state, ALE signal goes LOW.
The status signals are changed as IO/𝑀’ = 0, S1 =0 and S0 = 1. These
3 status signals do not change throughout the I/O write machine cycle.
4 The microprocessor makes the 𝑊𝑅’ line LOW to enable I/O write.
T2 The contents of the Accumulator are placed on the address / data
5
bus.
The data placed on the address / data bus is transferred to the
6
specified I/O port.
T3
The microprocessor makes the 𝑊𝑅’ line HIGH to disable the I/O
7
write operation
77
Microcontroller
A microcontroller is a small and low-cost microcomputer, which is
designed to perform the specific tasks of embedded systems like
displaying microwave’s information, receiving remote signals, etc.
The general microcontroller consists of the processor, the memory
(RAM, ROM, EPROM), Serial ports, peripherals (timers,
counters), etc.
Types of Microcontrollers
Microcontrollers are divided into various categories based on
1. Memory
2. Architecture
3. Bits
4. Instruction sets.
78
Microcontroller
General Structure of a Microcontroller
79
Types of Microcontroller
Based on Bits
8-bit microcontroller
This type of microcontroller is used to execute arithmetic and logical
operations like addition, subtraction, multiplication division, etc. For
example, Intel 8031 and 8051 are 8 bits microcontroller.
16-bit microcontroller
This type of microcontroller is used to perform arithmetic and
logical operations where higher accuracy and performance is
required. For example, Intel 8096 is a 16-bit microcontroller.
32-bit microcontroller
This type of microcontroller is generally used in automatically
controlled appliances like automatic operational machines, medical
appliances, etc.
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Types of Microcontroller
Based on Memory
External memory microcontroller
This type of microcontroller is designed in such a way that they do
not have a program memory on the chip. Hence, it is named as
external memory microcontroller. For example: Intel 8031
microcontroller.
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Types of Microcontroller
Based on Instruction Sets
CISC
CISC stands for complex instruction set computer. It allows the user
to insert a single instruction as an alternative to many simple
instructions.
RISC
RISC stands for Reduced Instruction Set Computers. It reduces the
operational time by shortening the clock cycle per instruction.
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Applications of Microcontroller
83
8051 Microcontroller
8051 microcontroller is designed by Intel in 1981
Features of 8051 Microcontroller are
4KB bytes on-chip program memory (ROM)
128 bytes on-chip data memory (RAM)
Four register banks
128 user defined software flags
8-bit bidirectional data bus
16-bit unidirectional address bus
32 general purpose registers each of 8-bit
16 bit Timers (usually 2, but may have more or less)
Three internal and two external Interrupts
Four 8-bit ports,(short model have two 8-bit ports)
16-bit program counter and data pointer
1 Microsecond instruction cycle with 12 MHz Crystal
84
Block Diagram of 8051 Microcontroller
85
Block Diagram of 8051 Microcontroller
The system bus connects all the support devices to the CPU.
The system bus consists of
• an 8-bit data bus
• a 16-bit address bus
• bus control signals
All other devices like
• program memory
• Ports
• data memory
• serial interface
• interrupt control
• Timers
• the CPU
are all interfaced together through the system bus.
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Pin Configuration of
8051 Microcontroller
• I/O operations are
done using four ports
and 40 pins.
• I/O operation port
reserves 32 pins
where each port has 8
pins.
• The other 8 pins are
designated as Vcc,
GND, XTAL1,
XTAL2, RST, EA
(bar), ALE/PROG
(bar), and PSEN
(bar).
87
Pin Configuration of 8051 Microcontroller
Pins 1 to 8
These pins are known as Port 1. This port doesn’t serve any other
functions. It is internally pulled up, bi-directional I/O port.
Pin 9
It is a RESET pin, which is used to reset the microcontroller to its initial
values.
Pins 10 to 17
These pins are known as Port 3. This port serves some functions like
interrupts, timer input, control signals, serial communication signals RxD
and TxD, etc.
Pins 18 & 19
These pins are used for interfacing an external crystal to get the system
clock.
Pin 20
This pin provides the power supply to the circuit.
88
Pin Configuration of 8051 Microcontroller
Pins 21 to 28
These pins are known as Port 2. It serves as I/O port. Higher order address
bus signals are also multiplexed using this port.
Pin 29
This is PSEN pin which stands for Program Store Enable. It is used to read
a signal from the external program memory.
Pin 30
This is EA pin which stands for External Access input. It is used to
enable/disable the external memory interfacing.
Pin 31
This is ALE pin which stands for Address Latch Enable. It is used to
demultiplex the address-data signal of port.
Pins 32 to 39
These pins are known as Port 0. It serves as I/O port. Lower order address
and data bus signals are multiplexed using this port.
Pin 40
This pin is used to provide power supply to the circuit.
89
8051 Microcontroller I/O Ports
Port 2
Port 2 occupies a total of 8 pins and can be used for both input and
output operations.
Just as P1 (Port 1), P2 also doesn't require external Pull-up resistors
because they are already connected internally.
It must be used along with P0 to provide the 16-bit address for the
external memory. So it is also designated as (A0–A7), as shown in the
pin diagram.
When the 8051 is connected to an external memory, it provides path for
upper 8-bits of 16-bits address, and it cannot be used as I/O.
Upon reset, Port 2 is configured as an input port.
91
8051 Microcontroller I/O Ports
Port 3
It is also of 8 bits and can be used as Input/Output.
This port provides some extremely important signals.
P3.0 and P3.1 are RxD (Receiver) and TxD (Transmitter) respectively
and are collectively used for Serial Communication.
P3.2 and P3.3 pins are used for external interrupts.
P3.4 and P3.5 are used for timers T0 and T1 respectively.
P3.6 and P3.7 are Write (WR) and Read (RD) pins.
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8051 Microcontroller Interrupt
8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI.
Each interrupt can be enabled or disabled by setting bits of the IE
register and the whole interrupt system can be disabled by clearing the
EA bit of the same register.
IE (Interrupt Enable) Register
This register is responsible for enabling and disabling the interrupt.
EA register is set to one for enabling interrupts and set to 0 for disabling
the interrupts. EA – External Access
Bit Sequence
93
8051 Microcontroller Interrupt
94
Applications of 8051 Microcontroller