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Analog Electronics

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3K views194 pages

Analog Electronics

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Analog Electronics

PEN-Drive / G-Drive Course / VOD & Tablet Users

Workbook

Electronics & Telecommunication Engineering

Electrical Engineering
Electrical & Electronics Engineering
Instrumentation Engineering

GATE / ESE / PSUs

Umesh Dhande Sir

Analog Electronics
PEN-Drive / G-Drive Course & LIVE Classroom Program

Workbook
ETC / EE / EEE / IN

Copyright © All Rights Reserved

GATE ACADEMY®

No part of this publication may be reproduced or distributed in any form or by any means, electronic,
mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without
the prior written permission of the publishers. The program listings (if any) may be entered, stored
and executed in a computer system, but they may not be reproduced for publication.

Printing of books passes through many stages - writing, composing, proof reading, printing etc. We
try our level best to make the book error- free. If any mistake has inadvertently crept in, we regret it
and would be deeply indebted to those who point it out. We do not take any legal responsibility.

Edition : AE-HPD-41022

GATE ACADEMY ®

Street - 04, Narsingh Vihar, Katulbod,

Bhilai - 490 022 (C.G.)
Phone : 0788 - 4034176
Help Desk No. - +91-97131-13156
For Feedback & Suggestions...
[email protected]
GATE Syllabus
Electronics & Communication (EC) : Small signal equivalent circuits of diodes, BJTs
and MOSFETs; Simple diode circuits: clipping, clamping and rectifiers; Single-stage
BJT and MOSFET amplifiers: biasing, bias stability, mid-frequency small signal analysis
and frequency response; BJT and MOSFET amplifiers: multi-stage, differential,
feedback, power and operational; Simple op-amp circuits; Active filters; Sinusoidal
oscillators: criterion for oscillation, single-transistor and op-amp configurations;
Function generators, wave-shaping circuits and 555 timers; Voltage reference
circuits; Power supplies: ripple removal and regulation.
Electrical Engineering (EE) : Characteristics of diodes, BJT, MOSFET; Simple diode
circuits: clipping, clamping, rectifiers; Amplifiers: Biasing, Equivalent circuit and
Frequency response; Oscillators and Feedback amplifiers; Operational amplifiers:
Characteristics and applications; Simple active filters, VCOs and Timers.
Instrumentation Engineering (IN) : Characteristics and applications of diode, Zener
diode, BJT and MOSFET; small signal analysis of transistor circuits, feedback
amplifiers. Characteristics of operational amplifiers; applications of Op-Amps:
difference amplifier, adder, subtractor, integrator, differentiator, instrumentation
amplifier, precision rectifier, active filters and other circuits. Oscillators, signal
generators, voltage controlled oscillators and phase locked loop.
Table of Contents

Sr. Chapter Pages

1. Clipper Circuit ……………….……………………………………………………………………. 1 - 10

2. Clamper Circuit…………….………………………………………………….…………………. 11 - 17

3. Diode Equivalent Circuit …………….………….…………………………………………. 18 - 24

4. Zener Diode As Regulator…………….…………………………..………..………………. 25 - 30

5. Rectifier & Filter (Only EC/IN) …..………………………….……………………………. 31 - 35

6. Operational Amplifier……………..…………………………………………….……………. 1 - 84

7. BJT Biasing …………..………………………………………………………….……..…………. 1 - 13

8. Region of BJT …………………………………………………………..…………………………. 1-6

9. Current Mirror Circuit ……………….…………………………………………….…...……. 1-4

10. BJT Regulator Circuit ………………………………………………………………………….. 1-3

11. Low Frequency BJT Amplifier ……………………………………………….……….……. 1 - 12

12. Feedback Amplifier ………………….………………………………………….……….……. 1-8

13. Frequency Response of the Amplifier ……………………..………….……….……. 1-8

14. MOSFET Amplifier (Only EC) ………………………………………..………….…………. 1-6

15. Oscillator …………….……………………...…………………………………………………….. 101-104

16. 555 - Timer……………………………………………………….….………………….…………. 105-108

Video Lecture Information
Sr. Lecture Name Duration
Chapter – 1
Lecture 01 Diode Family (Part 1) 2:52:51
Lecture 02 Diode Family (Part 2) 3:07:10
Lecture 03 Diode Family (Part 3) 4:14:17
Lecture 04 Diode Family (Part 4) 2:59:07
Lecture 05 Diode Family (Part 5) 2:43:20
Lecture 06 Diode Family (Part 6) 2:20:25
Lecture 07 Diode Family (Part 7) 2:30:26
Lecture 08 Diode Family (Part 8) 2:18:39
Lecture 09 Diode Family (Part 9) 2:50:30
Lecture 10 Diode Family (Part 10) 3:38:50
Lecture 11 Diode Family (Part 11) 2:46:18
Lecture 12 Diode Family (Part 12) 2:25:03
Chapter - 2
Lecture 01 Transistor Family (Part 1) 2:51:59
Lecture 02 Transistor Family (Part 2) 2:37:50
Lecture 03 Transistor Family (Part 3) 2:37:39
Lecture 04 Transistor Family (Part 4) 2:51:34
Lecture 05 Transistor Family (Part 5) 2:17:48
Chapter - 3
Lecture 01 Operational Amplifier (Part 1) 3:03:20
Lecture 02 Operational Amplifier (Part 2) 2:58:49
Lecture 03 Operational Amplifier (Part 3) 2:58:27
Lecture 04 Operational Amplifier (Part 4) 3:04:52
Lecture 05 Operational Amplifier (Part 5) 2:51:41
Lecture 06 Operational Amplifier (Part 6) 4:03:23
Lecture 07 Operational Amplifier (Part 7) 3:39:51
Lecture 08 Operational Amplifier (Part 8) 2:38:19
Lecture 09 Operational Amplifier (Part 9) 2:49:34
Lecture 10 Operational Amplifier (Part 10) 2:35:17
Lecture 11 Operational Amplifier (Part 11) 2:23:54
Lecture 12 Operational Amplifier (Part 12) 2:43:21
Lecture 13 Operational Amplifier (Part 13) 3:19:28
Lecture 14 Operational Amplifier (Part 14) 2:40:55
Lecture 15 Operational Amplifier (Part 15) 2:53:25
Lecture 16 Operational Amplifier (Part 16) 2:40:06
Lecture 17 Operational Amplifier (Part 17) 2:59:42
Lecture 18 Operational Amplifier (Part 18) 3:07:54
Lecture 19 Operational Amplifier (Part 19) 3:27:00
Lecture 20 Operational Amplifier (Part 20) 4:12:30
Lecture 21 Operational Amplifier (Part 21) 3:11:09
Lecture 22 Operational Amplifier (Part 22) 1:28:13
Chapter - 4
Lecture 01 Current Mirror Circuit (Part 01) 1:45:33
Lecture 02 Current Mirror Circuit (Part 02) 3:57:02
Chapter - 5
Lecture 01 BJT & MOSFET Amplifier (Part 1) 2:57:49
Lecture 02 BJT & MOSFET Amplifier (Part 2) 2:53:22
Lecture 03 BJT & MOSFET Amplifier (Part 3) 2:47:49
Lecture 04 BJT & MOSFET Amplifier (Part 4) 2:32:14
Lecture 05 BJT & MOSFET Amplifier (Part 5) 2:00:30
Lecture 06 BJT & MOSFET Amplifier (Part 6) 1:59:06
Lecture 07 BJT & MOSFET Amplifier (Part 7) 2:42:30
Lecture 08 BJT & MOSFET Amplifier (Part 8) 2:39:44
Lecture 09 BJT & MOSFET Amplifier (Part 9) 2:38:51
Lecture 10 BJT & MOSFET Amplifier (Part 10) 2:28:26
Lecture 11 BJT & MOSFET Amplifier (Part 11) 2:48:18
Lecture 12 BJT & MOSFET Amplifier (Part 12) 3:39:36
Lecture 13 BJT & MOSFET Amplifier (Part 13) 2:56:21
Lecture 14 BJT & MOSFET Amplifier (Part 14) 2:52:22
Lecture 15 BJT & MOSFET Amplifier (Part 15) 2:37:38
Lecture 16 BJT & MOSFET Amplifier (Part 16) 2:34:06
Lecture 17 BJT & MOSFET Amplifier (Part 17) 3:24:29
Lecture 18 BJT & MOSFET Amplifier (Part 18) 3:03:17
Lecture 19 BJT & MOSFET Amplifier (Part 19) 2:11:55
Lecture 20 BJT & MOSFET Amplifier (Part 20) 1:46:13
Lecture 21 BJT & MOSFET Amplifier (Part 21) 2:55:31
1 Clipper Circuit

Objective & Numerical Ans Type Questions : 1kW

Q.1 Assuming the diodes D1 and D2 of the D1

circuit shown in figure to be ideal ones, the Vi D2 V0
transfer characteristics of the circuit will be
Z 6.8 V
[GATE EE 2006, IIT Kharagpur]
D1 The maximum and minimum values of the
output voltage respectively are
2W D2 (A) 6.1 V,  0.7 V (B)0.7 V,  7.5 V
Vi RL = ¥ V0 (C) 7.5 V,  0.7 V (D)7.5 V,  7.5 V
10 V 5V Q.3 The equivalent circuits of a diode, during
forward biased and reverse biased
(A) V0 (B) V0
conditions, are shown in the figure.
0.7 V Rf
10

Vi Vi
10 5 Fig. (a)
(C) V0 (D) V0 10 kΩ

10 10
5 10sin wt V0 10 kΩ
5V
Vi Vi
5 10 10
Q.2 In the following limiter circuit, an input Fig. (b)
voltage Vi  10sin100 πt V is applied.
If such a diode is used in clipper circuit of
Assume that the diode drop is 0.7 V when it figure given above, the output voltage (V0 )
is forward biased. The Zener breakdown
of the circuit will be
voltage is 6.8 V.
[GATE EE 2008, IISc Bangalore]
[GATE EC 2008, IISc Bangalore]

0 p 2p wt 4.3
Vi
-5 V 4.3 10

(B) (C)
V0
+10 V

5.7
0 p 2p wt
-0.7
Vi
-5.7 V -0.7 5.7

10
+5.7 V

p wt -5.7
0 2p Vi
10
- 5.7
-10 V
Q.5 Two silicon diodes with a forward voltage
(D)
drop of 0.7 V are used in the circuit shown
in the figure. The range of input voltage Vi
+5.7 V for which the output voltage V0  Vi , is
[GATE EC 2014, IIT Kharagpur]
0 p 2p wt R

-5 V D1 D2
Vi V0
Q.4 A clipper circuit is shown below
-1V +- +
- 2V
1 kW

(A)  0.3 V  Vi  1.3V

D
(B)  0.3 V  Vi  2.0 V
Vi Vz = 10 V V0
(C)  1.0 V  Vi  2.0 V
5V (D) 1.7 V  Vi  2.7 V
Q.6 Assuming the diodes to be ideal in the
Assuming forward voltage drop of the figure, for the output to be clipped, the input
diodes to be 0.7 V, the input-output transfer voltage Vi must be outside the range
characteristics of the circuit is [GATE EE 2014, IIT Kharagpur]
(A) V0 10 kW

D1 D2

4.3 Vi 10 kW V0
1V 2V
Vi
4.3

the given sine wave input (Vin ) will be

[GATE EC 2015, IIT Kanpur]
 6V

0 0.5 T T Vin V out (A)

 6V
(A)
(B)
0 0.5 T T
-12 V
(B)
12 V
0 0.5 T T
(C)
(C) -6 V
0 0.5 T T
(D)
(D)
-6 V
0 0.5 T T Q.10 The output waveform for the given figure
Q.8 A voltage signal 10sin t is applied to the will be
circuit with ideal diodes, as shown in figure. Vi
The maximum and minimum values of the 20 V
output waveform Vout of the circuit are
respectively.[GATE EE 2003, IIT Madras] t
10 kΩ
20 V
D2
D1
1 k
Vin 4V Vout
4V 0.7 V D1 6.2 V
10 kΩ
Vi V0
0.7 V D2 15 V
(A) + 10 V and – 10 V
(B) + 4 V and – 4 V
(C) + 7 V and – 4 V
(D) + 4 V and – 7 V (A)
Q.9 For the circuit shown below, assume that the V0
Zener diode is ideal with a breakdown 15.7 V
voltage of 6 volts. The waveform observed
t
across R is
 6.9 V
[GATE EC 2006, IIT Kharagpur]

6.9 V
t 5.9
15.7 V
0 t
(C)
V0
Practice (objective & Num Ans) Questions :
6.9V
t Q.1 For a sinusoidal input of 50 V amplitude, the
circuit shown in below figure can be used as
2.5 kW
(D)
V0 5V
Vi V0
5V
t

15.7 V
(A) Regulated dc power supply
Q.11 The wave shape of V0 in figure is (B) Square wave generator
[GATE EC 1993, IIT Bombay] (C) Half wave rectifier
4.1V 4.1V
(D) Full wave rectifier
Q.2 The cut-in voltage of both zener diode DZ
and diode D shown in figure is 0.7 V, while
~ 10sin 314t 10 kW V0
break-down voltage of DZ is 3.3 V and
reverse break-down voltage of D is 50 V.
(A) V0 The other parameters can be assumed to be
the same as those of an ideal diode. The
5.9 values of the peak output voltage (V0 ) is
0 t 1 kW
- 5.9
Dz
(B) V0
10sin wt V0 1 kW
w = 314 rad/s D
4.1

0 t
(A) 3.3 V in the positive half cycle and 1.4 V
- 4.1 in the negative half cycle.
(C) V0 (B) 4 V in the positive half cycle and 5 V in
the negative half cycle.
4.1
(C) 3.3 V in both positive and negative half
0 t cycle.
- 4.1 (D) 4 V in both positive and negative half
cycle.
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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GATE ACADEMY® 5 Clipper Circuit
Q.3 For the circuit given in figure, assuming (A) Zero (B) 5.7 V
ideal diode, the output waveform V0 is (C) 6.9 V (D) 12.6 V
R Q.5 Consider the following circuit
10 kW

+ +
Vs  10 sin t V0 D1
5V D2
Vi 10 kW V0
10 V
(A) V0 – –

10 V For the circuit shown in the above figure,

t which one of the following is a correct
statement?
(A) D2 does not conduct for any value of Vi
(B) V0  10V , D2 does not conduct for any
(B)
V0 value of Vi  10V

5V
(C) V0  10V , D2 does conduct for any
value of Vi  20V
t
Vi
(D) V0  , D2 does not conduct for any
2
V0
value of Vi  15V
(C)
Q.6 In the circuit given below, D1 and D2 are
5V
ideal. Which one of the following represents
0 t the transfer characteristics of the circuit?
D1
 5V

6 k D2
Vi 4k V0
(D) V0
10 V 5V
5V
(A)
0 t V0

10V
10 V

Vi
Q.4 The output voltage V 0 in the circuit shown 10 V

in the given figure is (Assume cut in voltage (B)

of each diode to be 0.6 V) V0

1k
6.3V 5V
Vi = 13V V0
6.3V Vi
5V

Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 6 GATE ACADEMY®
(C) (D) (C) V0
V0 V0
10 V 10 V t
–VR
5V
Vi Vi
5 V 10 V 10 V (D) V0
Q.7 The cut-in voltage of Zener diode Dz and
t
diode D shown in the figure below is 0.7 V. –VR
Breakdown voltage of Dz is 3.3 V and
reverse breakdown voltage of D is 50 V. Q.9 The function of the following circuit if the
The other parameters can be assumed to be input is a sine wave
the same as those of an ideal diode. Then R
what are the values of the peak output + +
voltage V0 ? D1 D2
Vi V0
1 kW 8V 4V
– –
Dz (A) Transmits that part of sine wave, which
Vi = 10sin wt V0 1 kW
is above + 8 V and below + 4 V.
w = 314 rad/s D
(B) Transmits that part of sine wave, which
lies between + 4 V and + 8 V.
Positive Half Negative Half (C) Transmit that part of sine wave, which
cycle in V cycle in V lies above – 4 V and below + 8 V.
(A) 3.3 1.4 (D) Transmit that part of sine wave, which
(B) 4 5 lies below + 4 V and above – 8 V.
(C) 3.3 3.3 Q.10 The output waveform for the given circuit is
(D) 4 4 vi RS

Q.8 20 V + +
D1 D2
R t vi v0
- 20 V 5V 5V
– –
D
Vi V0 Assume silicon diode with cut-in voltage of
VR 0.6 V.
(A)
For a sinusoidal input of peak value Vp , the
output waveform V0 will be
(A)V0
VR
t
(B)
(B) V0
VR
t

(D)
V0
(D)
15V
0 t
 2 3
10 V

Q.12 For the circuit shown below, vi is a

sinusoidal voltage of 60 V.
Q.11 A triangular voltage of figure A is applied to
+ 20 k 15 k +
the biased clipper circuit of figure B. The D1 D2
wave shape of the output voltage v 0 is Vi V0
15 V 35 V
Vi
– –
35 V

0 
t Assuming ideal diodes, the output waveform
2 3
is given by
 35 V (A)
V0
60V
Fig. (A)
35 V
R 15V
t
+ +
D1 D2
Vi V0 6 0 V
15V 10 V
– – (B)
V0
Fig. (B) 60V
35 V
(A) V0
t
15V
t 6 0 V
0  2 3
15 V (C)
V0
60 V
(B) V0

t
10 V – 15 V
0 t
 2 3
10 V – 60 V

Vi V0
t 4V
– –
6 0 V

Q.13 For the circuit given in the figure assuming

V0
ideal diode, output waveform V0 is : (A) 12 V
R
4V
Vs = 10sin wt V0
5V t

V0
(A)
12 V
5V
t V0
(B)

4V
V0
(B) t
5V 4 V
t

V0 (D) None of these

(D)
10 V
Assignment (objective & Num Ans) Questions :
t Q.1 In the question a circuit and a waveform for
-5V the input voltage is given. The diode in
circuit has cutin voltage V  0. Choose the
Q.14 The output waveform V0 for a given below option for the waveform of output voltage
figure is v0 .
Vi
vi
12 V 20
2.2 kW

t t vi v0
5V
-5

12 V

-5 vi
20V
D1 ON D1 ON D1 OFF
D2 ON D2 OFF D2 OFF
vi
(C) (D) v0
20
10 V
0.5
5V
t vi
10V
D1 OFF D1 ON D1 OFF
vi D2 ON D2 ON D2 OFF
(D)
20 Q.3 Consider the circuit shown below assume
ideal diode
D
5
t
R
Vi V0
Q.2 For the circuit shown below, if
2V
vi  20sin ωt
The transfer characteristics of circuit will be
D1 10 k 10 k V0
D2
Vi 10 k V0
10 V

(A)  5 V Vi
5 V
The transfer characteristic plot is
v0
(A)
10 V0

0.5

vi
20V (B) Vi
D1 OFF D1 ON D1 ON 5 V 2V  5 V
D2 OFF D2 OFF D2 ON

8V
(A) vi
(C) Vi -8V
5 V 2V  5 V
-8V

v0
V0
8V

-8V
(B) vi
8V
(D) Vi
5 V 5 V -8V

v0
Q.4 Consider the circuit shown in the figure,
assume that the diodes has cutin voltage 0.6 6.8 V
V. The breakdown voltage of zener diode is (C) 6.8 V
vi
shown in circuit. The transfer characteristic - 6.8 V
of circuit is - 6.8 V

R D1 D2
Dz v0
vi v0
6.8 V 6.8 V
D4 D3 - 6.8 V
(D) vi
6.8 V
- 6.8 V

Answer Keys

Objective & Numerical Answer Type Questions

1. A 2. C 3. A 4. C 5. D
6. B 7. C 8. D 9. B 10. B
11. A
Practice (Objective & Numerical Answer) Questions
1. B 2. B 3. D 4. C 5. C
6. B 7. B 8. D 9. C 10. B
11. D 12. A 13. A 14. C
Assignment (Objective & Numerical Answer) Questions
1. D 2. A 3. C 4. B

Objective & Numerical Ans Type Questions : Q.3 The diodes and capacitors in the circuit
shown are ideal. The voltage v(t) across the
Q.1 The diodes D1 and D2 in the figure are diode D1 is
ideal and the capacitors are identical. The
[GATE EC /EE/IN 2012, IIT-Delhi]
product RC is very large compared to the
time period of the ac voltage. Assuming that C1
v(t ) D2
the diodes do not breakdown in the reverse
+
bias, the output voltage V0 (in volt) at the cos(wt ) D1 C2
steady state is ____________. -
[GATE EC 2016, IIT-Kanpur]
D1
(A) cos(t )  1 (B) sin(t )

10sin wt C (C) 1  cos(t ) (D) 1  sin(t )

V0
R Q.4 The circuit shown in the figure is best
ac C described as a
[GATE EC 2003, IIT Madras]
D2

Q.2 If the circuit shown has to function as a

Output
clamping circuit then which one of the Vi ~
following conditions should be satisfied for
the sinusoidal signal of period T ?
[GATE EC 2015, IIT Kanpur]
(A) bridge rectifier
C
(B) ring modulator
(C) frequency discriminatory
V ~ R
(D) voltage doubler
Q.5 In the figure, the ideal moving iron
(A) RC  T (B) RC  T voltmeter M will read
(C) RC  0.35T (D) RC  T [GATE EC 1993, IIT-Bombay]

Vs C Vc
Ideal diode
10sin 314t 100 mF

Q.8 In the circuit shown, assume that diodes D1

and D2 are ideal. In the steady-state
(A) 7.07 V (B) 12.24 V
(C) 14.214 V (D) 20.0 V condition, the average voltage Vab (in Volts)
Q.6 In the voltage doubler circuit shown in the across the 0.5 F capacitor is ______.
figure, the switch ‘S’ is closed at t = 0. [GATE EC 2015 (Set - 03), IIT-Kanpur]
Assuming diodes D1 and D2 to be ideal, load 1mF
resistance to be infinite and initial capacitor
voltages to be zero, the steady state voltage D1 D2
across capacitors C1 and C 2 will be [GATE 50sin(wt ) ~
0.5 mF
EE 2008, IISc-Bangalore]
vc1 a - + b
t=0 D2 Vab
+ _
S
C1
Q.9 What will be the voltage reading of DC
+ Voltmeter placed across the terminals of the
5 sin wt ~ D1 C2 _ vc 2 Rload
Diode in the circuit below,
 DC 
voltmeter
(A) vc1  10 V, vc 2  5 V
(B) vc1  10 V, vc 2   5 V
D1
(C) vc1  5 V, vc 2  10 V
Vi ( t) R L  50 
(D) vc1  5 V, vc 2  10 V
1: 2
Q.7 In the circuit shown, Vs is a 10 V square
wave of period, T = 4 ms with R = 500  having the following periodical input signal
and C = 10  F. The capacitor is initially Vi (t )
uncharged at t = 0. and the diode is assumed Vm
to be ideal. The voltage across the capacitor (  5.2 V)
( Vc ) at 3 ms is equal to _________ volts
(rounded off to one decimal place).
[GATE EC 2019, IIT Madras]  3/2 2
0
/2
Vs
10

0 Vm
t
T T (  5.2V)
2
10 (Assume cut-in voltage of the Diode = 0 V;
Forward resistance of the Diode = 2 )
t 0
[ISRO EC 2018]
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GATE ACADEMY® 13 Clamper Circuit
(A) 1.25 V (B) 2.5 V (A) 7.5 V and – 20.5 V
(C) 0 V (D) 0.1 V (B) 6.1 V and – 21.9 V
Q.10 The input voltage, Vi is 4  3sin t. (C) 7.5 V and – 21.2 V
Assuming all elements to be ideal. The (D) 6.1 V and – 22.6 V
average of the output voltage V0 in figure is
Practice (objective & Num Ans) Questions :
[GATE IN 1999, IIT-Bombay]
Q.1 Examine the following circuit and assume
that the diode is of correct PIV rating.
C
Vi D V0 C1 D2

Vi D1 C2 V0

(A)  3 V (B)  3 V
(C)  7 V (D)  7 V The above circuit acts like a
Q.11 In the figure, D1 is a real silicon p-n (A) Voltage doubler
junction diode with a drop of 0.7 V under (B) Voltage tripler
forward bias condition and D2 is a Zener (C) Voltage quardrupler
diode with breakdown voltage of  6.8V . (D) Clipper
The input Vin (t ) is a periodic square wave of Q.2 The primary function of a clamper circuit is
period T , whose one period is shown in the to
figure. (A) Suppress variation in signal voltage.
Vin (t ) (B) Raise positive half-cycle of the signal.
(C) Lower negative half-cycle of the signal.
14 V
(D) Introduce a DC level into a signal.
T t (sec) Q.3 The output voltage across the load RL is :
vi
– 14 V Vm
C

t vi RL

10 mF -Vm

(A)
D1 Vm
Vin (t ) 10 W Vout (t )
D2 t

-Vm

(B)
Assuming 10  T , where  is the time
2Vm
constant of the circuit, the maximum and
minimum values of the output waveform are Vm
respectively.
[GATE EC 2017, IIT Roorkee] t

C1
Output
(D) C2
t Vi D1

-Vm

- 2Vm (A) Vm , 2Vm (B) 2Vm , Vm

Q.4 The output voltage V0 for the clamper (C) 2Vm , 2Vm (D) 2Vm , Vm
circuit shown below is Q.6 Match List-I (Circuits) with List-II
Vi C (Characteristics/applications) and select the
15 V 1μF correct answer using the codes given below
Vin 100 kW V0 the lists :
t
t1 t2 t3 t4 4V List-I
- 25 V
(Circuits)
(A) V0 A. High-pass RC circuit
44 V B. Low-pass RC circuit
C. Clamping circuit
4V
D. Clipping circuit
t
t1 t2 t3 t4 List-II
(Characteristics/Applications)
(B) V0
1. Comparator
44 V 2. DC Restorer
4V 3. Integrator
t 4. Differentiator
t1 t2 t3 t4
5. Compensated Attenuator
(C) V0 Codes : A B C D
(A) 5 4 2 1
4V
(B) 4 3 1 2
t
t1 t2 t3 t4 t5 (C) 5 4 1 2
- 36 V (D) 4 3 2 1
Q.7 The circuit which is used to move the
(D) V0 positive or negative peak of input waveform
15 V to a desired level is :
(A) Comparator (B) Clipper
4V
(C) Clamper (D) None of these
t
t1 t2 t3 t4 Q.8 Vi is a pulse of 12 V & duration 5μs as
shown in the fig. (a) is applied to the circuit
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GATE ACADEMY® 15 Clamper Circuit
shown in the fig(b). Assume that the initial (B) - 2 V
voltage on 0 volt is waveform for V0 will be
-7V
8k

12 V D -12 V
Vi 30 k 1000 pF V0
5 msec
0V
Vi
(C) + 8 V
Fig. (a) Fig. (b)
+ 3V
(A) V0
-2V
5.18 V

(D) + 2 V

0 5
t (μsec) - 3V
(B) V0
-8V
5.18 V

Assignment (objective & Num Ans) Questions :

Q.1 Consider the following statements :
t (μsec)
0 5 A clamper circuit
(C) V0
1. Adds or subtracts a dc voltage to or from
5.18 V
a waveform.
2. Does not change the shape or slope of
the waveform.
t (μsec)
0 5 3. Amplifies the waveform.
(D) V0
of these statements
(A) 1 and 2 are correct
(B) 1 and 3 are correct
2.18 V
(C) 2 and 3 are correct
t (μsec)
0 5
(D) 1, 2 and 3 are correct
Q.9 Suppose an input sinusoidal waveform with
 5 V maximum and minimum position is Q.2 For an input of Vs  5sin t , (assuming
applied to the circuit below. ideal diode), circuit shown in the figure will
behave as a
C
D
Vi V0 0.1 mF

2V Vs V0
2V
The output voltage waveform is
(A) + 12 V (A) Clipper, since wave clipped at – 2 V
(B) Clamper, sine wave clamped at – 2 V
+7V
(C) Clamper, sine wave clamped at zero volt
+2V (D) Clipper, sine wave clipped at 2 V

Select the correct output (V0 ) wave-shape

for a given input (V i ) in the clamping The output Vdc from the above circuit is
network given above? (A) 12 2 (B) 12 / 
(A) (C) 24 /  (D) 12/ 2
V0
Q.7 Consider the below circuit, for
22 V
Vi  Vm sin t , the output voltage V0 for
RL   will be
2V
C
t

D
(B)
V0
Vi D RL C V0
18 V

t
-2V
(A) Zero (B) Vm
(C) (C) 2Vm (D) Vm
V0
t Q.8 A clamper circuit
-2V 1. Adds or subtracts a dc voltage to or from
a waveform
- 22 V 2. Does not change the shape of the
waveform
(D) Which of the above statements is/are
V0
correct?
2V (A) 1 only (B) 2 only
t (C) Both 1 and 2 (D) Neither 1 nor 2

-18 V

Answer Keys

Objective & Numerical Answer Type Questions

1. 0 2. D 3. A 4. D 5. B
6. D 7. 3.3 8. 100 9. A 10. A
11. A
Practice (Objective & Numerical Answer) Questions
1. A 2. D 3. B 4. D 5. A
6. D 7. C 8. B 9. A
Assignment (Objective & Numerical Answer) Questions
1. A 2. B 3. D 4. D 5. A
6. A 7. C 8. C



Objective & Numerical Ans Type Questions : (A) 0 mA (B) 0.5 mA

(C) 1 mA (D) 2 mA
Q.1 In the circuit shown below diodes has cut-in
voltage of 0.6 V. The diode in ON states are Q.4 The voltage V0 for the network given below
is
D1 12 6 D2 12 V

5.4V 18  5V
V  0.7 V Si Ge V  0.3V

(A) Only D1 (B) Only D2

V0
(C) Both D1 and D2 (D) None of these
2.2 k
Q.2 For the circuit shown is the assume ideal
diodes with zero forward resistance and zero
forward voltage drop. The current through (A) 11.7 V (B) 11.3 V
the diode D2 in mA is ___________. (C) 11 V (C) None of these
[GATE IN 2014, IIT-Kharagpur] Q.5 Assuming that the diodes in the given circuit
D1 D2
are ideal, the voltage V0 is
[GATE EE 2010, IIT-Guwahati]
200 W
10 kW
10 V 8V
10 V 10 kW
10 V V0 15 V
10 kW
Q.3 Assume that D1 and D2 in figure are ideal
diodes. The value of current I is
[GATE EE 2005, IIT-Bombay]
(A) 4 V (B) 5 V
D1 2 kΩ (C) 7.5 V (D) 12.12 V
1mA Q.6 In the circuit of in the figure is the current
(DC) ID through the ideal diode (zero cut-in
I
2 kΩ
D2 voltage and forward resistance) equals
[GATE EC 1997, IIT-Madras]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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GATE ACADEMY® 19 Diode Equivalent Circuit
ID 1Ω

4W 1Ω

10 V 4W 1W 2A D2

10 V D1 1Ω D3 5A

(A) 0 A (B) 4 A
(C) 1 A (D) None of these (A) D1ON, D 2 OFF, D3OFF
Q.7 In the circuit shown, Vs is a square wave of (B) D1OFF, D 2 ON, D3OFF
period T with maximum and minimum (C) D1ON, D 2 OFF, D3ON
values of 8 V and – 10 V, respectively.
(D) D1OFF, D 2 ON, D3ON
Assume that the diode is ideal and
Q.10 A dc current of 26 A flows through the
R1  R2  50  . The average value of VL
circuit shown. The diode in the circuit is
is_______ volts (rounded off to 1 decimal forward biased and it has an ideality factor
place). [GATE EC 2019, IIT-Madras] of one. At the quiescent point, the diode has
Vs a junction capacitance of 0.5 nF. Its neutral
region resistances can be neglected. Assume
8
that the room temperature thermal
0 t equivalent voltage is 26 mV.
T T
2
10
5sin(wt ) mV
100 W
R1
V


Vs R2 VL
For   2  106 rad/sec , the amplitude of the
 small-signal component of diode current (in
A , correct to one decimal place) is
Q.8 In the circuit below, the diode is ideal. The
______. [GATE EC 2018, IIT-Guwahati]
voltage V is given by
[GATE EC 2009, IIT-Roorkee] . Statement for Linked Answer Ques 11 & 12 .
V In the circuit shown below, assume that the voltage
drop across a forward biased diode is 0.7 V. The
1W 1W
thermal voltage VT  kT /q  25 mV . The small
Vi D 1A signal input voltage Vi  V p cos (t ) where
V p  100 mV .
9900 W

(A) min  Vi ,1 (B) max  Vi ,1

12.7 V
(C) min  Vi ,1 (D) max  Vi ,1 I DC + iac VDC + Vac

Q.9 What are the states of the three ideal diodes Vi

of the circuit shown in figure?
[GATE EE 2006, IIT-Kharagpur]

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Analog Electronics [Workbook] 20 GATE ACADEMY®
Q.11 The bias current I DC through the diodes is Q.15 In the figure, assume that the forward
(A) 1 mA (B) 1.28 mA voltage drops of the PN diode D1 and
(C) 1.5 mA (D) 2 mA Schottky diode D2 are 0.7 V and 0.3 V,
Q.12 The ac output voltage Vac is respectively. If ON denotes conducting state
of the diode and OFF denotes
(A) 0.25 cos(t ) mV
nonconducting state of the diode, then in the
(B) 1cos(t ) mV circuit, [GATE EC 2014, IIT Kharagpur]
(C) 2cos(t ) mV 1kW 20 kW
(D) 22cos(t ) mV
Q.13 The i-v characteristics of the diode in the 10 V D1 D2
circuit given below are
 0 v  0.7 V

i   v  0.7
(A) Both D1 and D2 are ON.
 500 A v  0.7 V
(B) D1 is ON and D2 is OFF.
1kW
i
(C) Both D1 and D2 are OFF.
10 V v
(D) D1 is OFF and D2 is ON.
Q.16 The diode in the circuit given below has
The current in the circuit is VON  0.7 V but is ideal otherwise. The
[GATE EC 2012, IIT Delhi] current (in mA) in the 4 kΩ resistor is
(A) 10 mA (B) 9.3 mA _______. [GATE EC 2015, IIT Kanpur]
(B) 6.67 mA (D) 6.2 mA 3kW
2 kW
Q.14 The diode in the circuit shown has D 1kW
Von  0.7 V but is ideal otherwise. If 1mA

Vi  5sin(t )V , the minimum and 4 kW 6 kW

maximum values of V0 (in Volts) are,
respectively, Practice (objective & Num Ans) Questions :
[GATE EC 2014, IIT Kharagpur]
Q.1 The reverse bias saturation current for a p-n
1kW junction diode is 1μA at 300 K. Its ac
Vi V0
R1 resistance at 150mV forward bias is
R2 1kW
(A) 51.4 
(B) 61.4 
+
- 2V (C) 71.4 
(D) 81.4 
Q.2 For the series diode configuration of below
(A) –5 and 2.7 (B) 2.7 and 5
figure. The value of I D is ___________mA.
(C) –5 and 3.85 (D) 1.3 and 5

3 k Ge

0.2V
+10 V V0
Si
I2 1k

0.7 V
Q.7 A diode whose V-I characteristics is shown
in figure (a) is connected to figure (b) as
shown find I0 .
Q.3 In the circuit shown in below figure. The I (mA)
D
value of impedance form AB is_______ k .
D1 0.2 I0
A 
10 V  92 k

D2 V (V)
0.7 0.9
10 V 10k Fig. (b)
Fig. (a)
5 k
(A) 1 mA (B) 100 mA
B
(C) 10 mA (D) 0.1 mA
Z AB Q.8 In the circuit shown below, D1 and D2 are
Q.4 In the circuit shown in below figure. The ideal diodes. The current i1 and i2 are
value of e0 is ____________V. respectively
D1 D1 i1 i2 D2

D2
500
5V 3V
D3
1.5 V +
- e3 5V
5V +
- e2
+
1V +
- e1 e0 (A) 0, 4 mA (B) 4 mA, 0
2V - (C) 0, 8 mA (D) 8 mA, 0
Q.5 In the circuit shown in below figure. The . Common data Questions 9 to 11 .
value of V0 is _____________V. Consider the circuit shown below. Assume
Si
diodes are ideal
V0 1
D1
v1

v2 v0
10 mA 2.2 kW I 1.2 kW 1 D2
9

(A) 8.21 V (B) 7.51 V Q.9 If v1  10 V and v2  5 V , then output

(C) 3.51 V (D) 12.21 V
voltage v0 is
Q.6 In the circuit shown in below figure. The
value of I2 is _______________mA. (A) 9 V (B) 9.474 V
(C) 0 V (D) 8.943 V
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Analog Electronics [Workbook] 22 GATE ACADEMY®
Q.10 If v1  v2  10 V , then output voltage v0 is Q.15 For the circuit shown below cut-in voltage
of diode is V  0.7 . What is the value of V
(A) 9 V (B) 9.474 V
(C) 4 V (D) 8.943 V and I?

Q.11 If v1   5V and v2  5 V then v0 is D1

+1 V
(A) 9.474 V (B) 8.943 V
(C) 4.5 V (D) 9 V +3 V V
D2
. Common data Questions 12 and 13 . I 2 kW

Consider the circuit shown below. Assume

diodes are ideal. –3 V

1W
D1 (A) 2.3 V, 2.65 mA (B) 2.65 V, 2.3 mA
v1
(C) 2 V, 0 mA (D) 0 V, 2.3 mA
v2 v0 Q.16 For the circuit in the figure below. The
1W D2
9W
values of I D and VD are
+8V +4V
5V
10 kW ID 10 kW

Q.12 If v1  v2  10 V , then output voltage v0 is

VD
(A) 0 V (B) 9.737 V 10 kW 10 kW
(C) 9 V (D) 9.5 V
Q.13 If v1   5V and v2  10 V , the output
(A) 0 A, 2.5 V (B) 2.5 mA, – 2 V
voltage v0 is
(C) 0 A, – 2 V (D) 4.5 mA, 2.5 V
(A) 9 V (B) 9.737 V
Q.17 For the circuit shown below each diode has
(C) 9.5 V (D) 4.5 V
V  0.6 V and rf  0 . Both diode will be
Q.14 Let cut-in voltage V  0.7 V for each diode
ON if
in the circuit shown below
D2 5 k
10 kW
+ 10 V v0
5k
D1 5 kW vs 500 
iD1 500 

-10 V
(A) vs  3.9 V (B) vs  4.9 V
The voltage v0 and current iD1 is
(C) vs  6.3V (D) vs  5.3V
(A) – 6.48 V, 2.1 mA
(B) – 3.57 V, 2.1 mA Q.18 The diodes in the circuit shown below has
parameters V  0.6 V and rf  0 . The
(C) – 3.57 V, 0 mA
(D) – 6.48 V, 0 mA current iD 2 is

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GATE ACADEMY® 23 Diode Equivalent Circuit
+10 V Q.1 If v2  0 , then output voltage v0 is
(A) 6.43 V (B) 9.43 V
9.5 kW
D2
(C) 7.69 V (D) 8.93 V
0.5 kW
0V Q.2 If v2  5 V , then v0 is
iD 2
v0
(A) 8.93 V (B) 12.63 V
+5 V
0.5 kW D1 D3 (C) 18.24 V (D) 10.56 V
Q.3 If v2  10 V , then v0 is
+5 V
(A) 10 V (B) 9.158 V
(A) 8.4 mA (B) 10 mA
(C) 8.43 V (D) 12.13 V
(C) 7.6 mA (D) 0 mA
. Common Data Questions 19 to 21 . . Common Data Questions 4 and 5 .
The diodes in the circuit shown below have The diodes in the circuit shown below has
linear parameter of V  0.6 V and rf  0. the non-linear terminal characteristic as
shown in figure. Let the voltage be
+10 V
vs  cos t V .
9.5 kW 100 a
D2
0.5 kW iD
v2 v0
vs
v1 100 vD
0.5 kW D1 2V
Q.19 If v1  10 V and v2  0 V , then v0 is
b
(A) 8.93 V (B) 7.82 V
iD (mA)
(C) 1.07 V (D) 2.18 V
Q.20 If v1  10 V and v2  5 V , then v0 is
4
(A) 9.13 V (B) 0.842 V
(C) 5.82 V (D) 1.07 V
Q.21 If v1  v2  0 , then output voltage v0 is
vD (V)
(A) 0.964 V (B) 1.07 V 0. 5 0.7

(C) 10 V (D) 0.842 V Q.4 The current iD is

Assignment (objective & Num Ans) Questions : (A) (5  9.09 cos t ) mA
(B) (5  4.65cos t ) mA
. Common Data Questions 1 to 3 .
The diodes in the circuit shown below have (C) (1  9.09 cos t ) mA
linear parameters of V  0.6 V and rf  0 . (D) (4  4.65cos t ) mA

500 W
D2 Q.5 The voltage vD is
v2
(A) (0.5  0.9 cos t ) V
+10 V v0 (B) (0.5  0.045cos t ) V
500 W
D1
9.5 kW (C) (0.5cos t ) V
(D) (0.5  0.45cos t ) V

resistances are equal, R1  R2  100 k . Assume V  0.7 V for the diode.

(A)  0.38 V (B)  4.4 V
R1 D1 VD1 (C) 2.6 V (D) None of these
5 kV Q.8 The output voltage V0 is

R2 D2 VD 2 ID V   0.7V

(A) VD1  2500 V, VD 2  2500 V 10 mA 2.2 k 1.2 k V0

(B) VD1  2250 V, VD 2  2750 V
(C) VD1  2750 V, VD 2  2250 V (A) 21.7 V (B) 15 V
(D) VD1  2000 V, VD 2  3000 V (C) 7.51 V (D) 4.32 V
Q.7 The value of v0 for the circuit given below
is

Answer Keys

Objective & Numerical Answer Type Questions

1. C 2. 10 3. A 4. A 5. B
6. C 7. –3 8. A 9. A 10. 6.4
11. A 12. B 13. D 14. C 15. A
16. 0.6
Practice (Objective & Numerical Answer) Questions
1. D 2. 3.32 3. 10 4. 5 5. B
6. 9.133 7. D 8. A 9. A 10. B
11. C 12. B 13. C 14. C 15. A
16. C 17. A 18. C 19. C 20. C
21. D
Assignment (Objective & Numerical Answer) Questions
1. D 2. A 3. B 4. A 5. B
6. C 7. A 8. C



Objective & Numerical Ans Type Questions : (A) 1.2 kohms (B) 80 ohms
(C) 50 ohms (D) 0 ohms
Q.1 A 12 V, 5 to 50 mA Zener diode is used as
voltage regulator as shown in figure. Load Q.4 The Zener diode shown in the circuit has a
current varies from 5 to 40 mA. The suitable reverse breakdown voltage of 10 V. The
range of series resistance RS is power dissipated in RS will be

(A) 181   RS  222  [GATE EC 1994, IIT-Kharagpur]

(B) 281   RS  222 

(C) 181   RS  333 
(D) 381   RS  333 
Q.2 For the circuit shown the range of I L such
that Zener diode is in break down condition
is ______________ mA. (Assume I Z max  (A) 0.5 W (B) 1 W
32 mA) (C) 0 W (D) 2 W
1k Q.5 A Zener diode in the circuit shown in the
R figure is has a knee current of 5 mA and a
IL
maximum allowed power dissipation of 300
50 V
10 V RL mW. What are the minimum and maximum
load currents that can be drawn safely from
the circuit, keeping the output voltage V0
Q.3 The 6 V Zener diode shown in the given
constant at 6 V?
figure has zero Zener resistance and a knee
[GATE EC 1996, IISc-Bangalore]
current of 5 mA. The minimum value of R
50 
so that the voltage across it does not fall
below 6 V is [GATE EC 1992, IIT-Delhi]
L
50 O
9V 6V A V0
– D
+ R
10 V
–
(A) 0 mA, 180 mA (B) 5 mA, 110 mA
(C) 10 mA, 55 mA (D) 60 mA, 180 mA
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 26 GATE ACADEMY®
Q.6 The current through the Zener diode is (C) 282.5  Vin  393.75
[GATE EE 2004, IIT-Delhi]
(D) 162.5  Vin  393.75
2.2kΩ

IZ Q.10 The sinusoidal AC source in the figure has

RZ  0.1k 20
an rms value of V . Considering all
10 V RL 3.5 V 2
VZ  3.3V
possible values of RL , the minimum value
of Rs in  to avoid burnout of the Zener
(A) 33 mA (B) 3.3 mA
diode is _________.
(C) 2 mA (D) 0 mA
Q.7 In the voltage regulator shown in figure, the [GATE EE 2014, IIT-Kharagpur]
load current can vary from 100 mA to 500 Rs
mA. Assuming that a Zener diode is ideal
(i.e. the Zener knee current is negligibly
20 5V
small and Zener resistance is zero in the V RL
2 1/4 W
breakdown region), the value of R is
[GATE EC 2004, IIT-Delhi]
R
Q.11 In the circuit shown, the breakdown voltage
and maximum current of Zener diode are 20
12 V 5V Variable 100
V and 60 mA, respectively. The values of
to 500 mA R1 and RL are 200 Ω and 1 kΩ ,
respectively.
(A) 7  (B) 70 
R1
(C) 70 / 3 (D) 14

. Common Data Questions 8 and 9 . Vi +_ RL

A 50 V, 5 to 40 mA Zener diode is used as
shown in the regulator circuit.
RS What is range of Vi that will maintain the
IL Zener diode in ‘on state’?

Vin  200 V [GATE EC 2019, IIT Madras]

RL
(A) 18 V to 24 V (B) 20 V to 28 V
(C) 22 V to 34 V (D) 24 V to 36 V
Q.8 The value of RS to allow voltage regulation
Q.12 The Zener diode in the regulator circuit
from I L  0 to I L max shown in the figure has a Zener voltage of
Q.9 If RS is set as found in above and I L is 5.8 volts and a Zener knee current of 0.5
mA. The maximum load current drawn from
fixed at 25 mA then what is the permissible
this circuit ensuring proper functioning over
range of Vin for Zener diode to act as a
the input voltage range between 20 volts and
voltage regulator. 30 volts, is
(A) 262.5  Vin  393.75
[GATE EC 2005, IIT Bombay]
(B) 162.5  Vin  493.75
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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GATE ACADEMY® 27 Zener Diode As Regulator
1kW 150 W

V = 15 V
Vin = (20 V -30 V) VZ = 5.8 V Load 50 V +
- z 75W
Rz = 0

(A) 23.7 mA (B) 14.2 mA (A) 1 W (B) 1.5 W

Practice (objective & Num Ans) Questions :

Q.5 The Q-point for the zener diode in figure is,
11kW
Q.1 The Zener diode shown in figure may be
assumed to require a minimum current of 25
Vz = 4 V
mA for satisfactory operation. The value of 20 V +
- 3.6 kW
R required for satisfactory voltage Rz = 0
regulation of the circuit is
R (A) (0.34 mA, 4 V) (B) (0.34 mA, 4.93 V)
(C) (0.94 mA, 4 V) (D) (0.94 mA, 4.93 V)
+
20 V Vz = 10 V 100 W Q.6 In the voltage regulator circuit in figure the
–
power rating of zener diode is 400 mW. The
value of RL that will establish maximum
(A) 20  (B) 40 
power in zener diode is,
(C) 60  (D) 80 
222 W
Q.2 A Zener diode has an equivalent resistance
of 20  . If the voltage across the diode is V = 10 V
20 V +
- z RL
5.2 V at I Z  1 mA . Determine the voltage Rz = 0

across the diode at I Z  10 mA .

(A) 5.2 V (B) 5.18 V (A) 5 k (B) 2 k
(C) 5.38 V (D) 6.2 V (C) 10 k (D) 8 k
Q.3 In the voltage regulator circuit in figure the Q.7 The maximum power rating of the Zener
maximum load current iL that can be drawn diode shown in circuit is 260 mW. It
is, maintains a constant voltage when current
through diode does not fall below 90 % of
15 kW
maximum permissible current. Find the
iL
range of I Z for which Zener diode
Vz = 9 V
30 V +
- RL maintains constant voltage.
Rz = 0

(A) 1.4 mA (B) 2.3 mA

(C) 1.8 mA (D) 2.5 mA
Q.4 In the voltage regulator circuit in figure the (A) (5 - 50) mA (B) (30 - 40) mA
power dissipation in the zener diode is, (C) (35 - 50) mA (D) (40 - 50) mA
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 28 GATE ACADEMY®
Q.8 A 6 V Zener diode voltage regulator circuit (C) 109   RL  300 
as shown in figure operates from a source (D) 109   RL  600 
that varies from 10 to 14 V, the series
resistance is 100 , and the load draws a Q.11 If RL  1 k, Rs  300 , then the range of
current that varies from 0 to 30 mA. The Vs is
power dissipation in the Zener diode under (A) 3.3V  Vs  11.4 V
worst-case conditions (i.e., the highest
(B) 4.65 V  Vs  11.4 V
power dissipation) is
(C) 3.3V  Vs  16.8 V
100 W
(D) 4.65 V  Vs  16.8 V
Vs 6V RL
Q.12 The zener diode voltage regulator circuit is
shown in figure, the breakdown voltage is 9
V. Suppose that the diode has a resistance of
(A) 0.18 W (B) 0.24 W
100 in the breakdown state and the diode
(C) 0.36 W (D) 0.48 W
is to operate with a reverse current between
Q.9 A 5 V zener diode voltage regulator circuit
is as shown in figure operates from a source 10 mA to 100 mA. The range of Vs is
that varies from 10 to 14 V. The load current Rs = 200 W
varies from 0 to 10 mA. The value of the
Vs RL = 600 W
series resistance so that the minimum
magnitude of the zener diode current is 5
mA, is
(A) 15.33 V to 45.33 V
Rs (B) 10.33 V to 40.33 V
Vs 5V RL
(C) 5.33 V to 35.33 V
(D) 20.33 V to 50.33 V
. Common Data Questions 13 and 14 .
(A) 333.33  (B) 600
Consider the shunt regulator circuit shown
(C) 166.66  (D) 300  in figure with Rs  0.75 k, RL  1k,
. Common Data Questions 10 and 11 . Vs  15 V zener breakdown voltage Vz  9 V
A 6 V zener diode voltage regulator circuit , rated power of zener diode PZM  25 mW .
is shown in figure has maximum current
Rs
rating of 50 mA. Knee current of zener
diode is 5 mA. Vs VZ RL VL

Vs 6V RL Q.13 The load voltage VL is

(A) 8.57 V (B) 9 V
(C) 9.57 V (D) 10.57 V
Q.10 If Vs  24 V, Rs  300  then the range of
Q.14 If RL is change to 1.25k then power
RL is
dissipated in zener diode is
(A) 218   RL  300  (A) 1.2 mW (B) 7.2 mW
(B) 218   RL  600  (C) 13.2 mW (D) 19.2 mW
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GATE ACADEMY® 29 Zener Diode As Regulator

Assignment (objective & Num Ans) Questions : Determine

(i) The output voltage for no load when
Q.1 Figure shows an electronic voltage
supply is 10 V.
regulator. The zener diode may be assumed
to require a minimum current of 25 mA for (ii) Change in output voltage at no load due
satisfactory operations. The value of R to supply variation of 1V .
required for satisfactory voltage regulation (iii) Change in output voltage when
of the circuit is RL  2 k .
R (iv) Output voltage at nominal supply when
R  RL .
20 V 100 W
10 V
(v) Minimum value of RL for which Zener
operates in breakdown region.
Q.2 Determine V0 for the circuit shown in figure Q.5 A Zener diode regulates at 50 V over a
range of diode circuits from 5 mA to 40 mA.
where Vz is the Zener voltage of the Zener
Supply voltage V = 200 V.
diode.
(i) Calculate the value of R to allow voltage
5 kW regulation from a load current I L  0
20 V 5 kW Vz = 12 V V0 upto I max , the maximum possible value
of I L .
(ii) What is I max ?
Q.3 In the circuit shown below, the zener diode
is ideal. The minimum value of RL up to Q.6 (1) The avalanche diode regulates at 50 V
over a range of diode currents from 5 to
which the output voltage remains constant is
40 mA. The supply voltage V = 200 V.
27 ohms
Calculate R to allow voltage regulation
i
from a load current I L  0 upto I max , the
24 V 15 V RL maximum possible value of I L . What is
I max ?
(2) If R is set as in part (1) and the load
(A) 27 ohms (B) 45 ohms
(C) 15 ohms (D) 24 ohms current is set at I L  25 mA , what are
Q.4 A Zener regulator circuit is shown below in the limits between which V may vary
which the nominal supply voltage is 10 V without loss of regulation in the circuit ?
but can vary by 1 V . The ratings of Zener +
R IL
are : Vz  6.8 V, I z  5 mA, rz  20  and
+ VL RL
V
I zk  0.2 mA . –

R = 0.5 kW –
+ +

Vi = 10 ± 1 V RL V0

Answer Keys

Objective & Numerical Answer Type Questions

1. A 2. 8 – 40 3. B 4. D 5. C
6. C 7. D 8. 3.75 9. D 10. 200-301
11. D 12. C
Practice (Objective & Numerical Answer) Questions
1. D 2. C 3. A 4. D 5. A
6. B 7. A 8. D 9. A 10. D
11. C 12. A 13. A 14. B
Assignment (Objective & Numerical Answer) Questions
1. 80 2. 10 3. B 4. * 5. *
6. *

4. (i) 6.827 V (ii)  38.46 mV (iii)  68 mV (iv) 5 V (v) 1.5 k

5. (i) 3.75 k (ii) 5 mA
6. (i) 3.75 k, 35 mA (ii) 162.5 V to 293.75 V



Objective & Numerical Ans Type Questions : (B)

Q.1 In a full-wave rectifier using two ideal

diodes, Vdc and Vm are the dc and peak

Input
values of the voltage respectively across a

Output
resistive load. If PIV is the peak inverse
voltage of the diode, then the appropriate
relationships for this rectifier are
[GATE EC 2004 - Delhi]
(C)
Vm
(A) Vdc  , PIV  2Vm

Vm
(B) Vdc  2 , PIV  2Vm
Input

Output
Vm
(C) Vdc  2 , PIV  Vm

Vm
(D) Vdc  , PIV  Vm
 (D)
Q.2 The correct full wave rectifier circuit is
[GATE EC 2007, IIT Kanpur]
(A)
Input

Output
Input

Output

Q.3 The figure shows a half-wave rectifier. The

diode D is ideal. The average steady state
current (in Amp) through the diode is
approximate _________.

Q.8 The primary function of a rectifier filter is to

10 V 475 F VC I0  1 A (A) Suppress old harmonics
(B) Remove ripples
(C) Stabilize the output d.c. level
(D) Minimize the input a.c. variations
Vi
Q.9 The major advantages of a bridge rectifier is
 10 V that
(A) No centre tap transformer is required
0V t (B) The required peak inverse voltage of
each diode is half of that for a full-wave
10 V rectifier.
VC (C) The peak inverse voltage of each diode
u is half of that for a full wave rectifier
(D) The output is more smooth.
0V t Q.10 The ripple frequency for a full wave rectifier
The value of the ripple u (in volts) is ____. is
Q.5 Consider a full wave bridge rectifier. The (A) equal to the supply frequency
capacitor C  20.3 F is connected in (B) twice the supply frequency
parallel to a resistor, R  10 k . The input (C) thrice the supply frequency
voltage, vs  50sin(2(60)t ) . Assume the (D) none of these
diode turn-on voltage, V  0.7 V . Calculate Practice (objective & Num Ans) Questions :
the value of the ripple voltage.
Q.1 The ideal characteristics of a stabilizer is
Q.6 Consider a full wave center – tapped
rectifier. The capacitor is connected in (A) Constant output voltage with low
parallel to a resistor, R  2.5 k . The input internal resistance.
voltage has a peak value of 120 V with a (B) Constant output current with low
frequency of 60 Hz. The output voltage internal resistance.
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GATE ACADEMY® 33 Rectifier & Filter
(C) Constant output voltage with high (A) 1 V (B) 0.5 V
internal resistance. (C) 2 V (D) 5 V
(D) Constant internal resistance with Q.8 The peak input-voltage to a full-wave bridge
variable output voltage. rectifier is 1000 V at 50 Hz. The dc output
. Common Data for Questions 2 and 3 . voltage and ripple are respectively
(A) 318 V and 50 Hz
A full-wave rectifier circuit is fed from a
(B) 318 V and 100 Hz
transformer having a centre-tapped
(C) 636 V and 50 Hz
secondary winding. The rms voltage from
(D) 636 V and 100 Hz
either and if secondary to centre tap is 30 V.
Q.9 Draw the output waveform for the circuit
If the diode forward resistance is 2 and
shown in the figure will be
that of the half secondary is 8 for a load
of 1k .
Q.2 The percentage regulation at full load is
(A) 97% (B) 98%
(C) 99% (D) 100%
Q.3 Efficiency of rectification is
(A) 80.2% (B) 80.5%
(C) 80.9% (D) 90%
Q.4 A full-wave rectifier with a centre-tapped
transformer supplies a dc current of 100 mA
to a load resistance of R  20  The
secondary resistance of transformer is 1 . (A)
Each diode has a forward resistance of
0.5 . The voltage regulation is
(A) 2.5% (B) 5%
(C) 7.5 % (D) None of these
(B)
. Common Data for Questions 5 and 6 .
A diode has an internal resistance of 20 
& load resistance of 1k is supply from a
110V rms source of supply.
Q.5 The value of dc voltage across the load is (C)
(A) 40 V (B) 50 V
(C) 60 V (D) 70 V
Q.6 The percentage regulation from no load to
full load is
(A) 1 % (B) 2 % (D)
(C) 3 % (D) 4 %
Q.7 A full-wave rectifier delivers 50 W to a load
of 200 . If ripple factor is 2 %, the a.c.
ripple voltage across the load is
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Analog Electronics [Workbook] 34 GATE ACADEMY®
Q.10 A half wave rectifier uses a diode with a . Common Data for Questions 17 to 19 .
forward resistance R f , the voltage is A bridge rectifier is driving a load resistance
Vm sin ωt and the load resistance is RL . The of 100  . It is driven by a source voltage of
DC current is given by : 230 V, 50 Hz. Neglecting diode resistances.
Vm Vm Q.17 The average dc voltage is
(A) (B)
2RL  ( R f  RL ) (A) 106.9 V (B) 96.9 V
2Vm Vm (C) 86.9 V (D) 206.9 V
(C) (D)
 RL Q.18 The average direct current is
. Common Data for Questions 11 to 13 . (A) 1.06 A (B) 2.06 A
(C) 3.06 A (D) 4.06 A
In a full wave bridge rectifier, the
transformer secondary voltage is 100 sin t . Q.19 The frequency of output waveform is
The forward resistance of each diode is (A) 25 Hz (B) 50 Hz
25  and the load resistance is 950  . (C) 100 Hz (D) 200 Hz
Q.11 The value of dc output voltage is . Common Data for Questions 20 to 22 .
(A) 59.85 V (B) 49.85 V A diode with VF  0.7 V is connected as a
(C) 39.85 V (D) 29.85 V half wave rectifier. The load resistance is
Q.12 The ripple factor is 600 Ω and the (rms) ac input is 24 V .
(A) 0.48 (B) 0.38 Q.20 The peak output voltage is
(C) 1.21 (D) 2.21
(A) 11.24 V (B) 22.24 V
Q.13 The efficiency of rectification is
(C) 33.24 V (D) 44.24 V
(A) 87 % (B) 77 %
Q.21 The peak load current is
(C) 67 % (D) 57 %
(A) 55.4 mA (B) 65.4 mA
. Common Data for Questions 14 to 16 .
(C) 75.4 mA (D) 85.4 mA
In a full wave rectifier, the input is from a Q.22 The diode reverse voltage is
30 – 0 – 30 V transformer. The load and
(A) 22.9 V (B) 33.9 V
diode forward resistance are 100  and
(C) 43.9 V (D) 53.9 V
10  respectively.
Q.14 The average voltage is
(A) 14.55 V (B) 24.55 V
(C) 34.55 V (D) 44.55 V
Q.15 The rectification efficiency is
(A) 83.7 % (B) 73.7 %
(C) 63.7 % (D) 53.7 %
Q.16 The percentage regulation is
(A) 5 % (B) 10 %
(C) 15 % (D) 20 %

Answer Keys

Objective & Numerical Answer Type Questions

1. B 2. C 3. 0.1 4. 2.105 5. 2
6. 20.6 7. 13.33 8. B 9. C 10. B
Practice (Objective & Numerical Answer) Questions
1. A 2. A 3. A 4. C 5. B
6. B 7. C 8. D 9. D 10. B
11. A 12. A 13. B 14. B 15. B
16. B 17. D 18. B 19. C 20. C
21. A 22. B



Objective & Numerical Ans Type Questions :

Q.1 The Op-Amp of figure shown below has a very poor open loop voltage gain of 45 but is otherwise ideal.
The gain of the amplifier equals [GATE EC 1990, IISc-Bangalore]
8 kW

2 kW

Vout
Vin

(A) 5 (B) 20 (C) 4 (D) 4.5

Q.2 Assume that the operational amplifier in figure is ideal the current I through the 1 k resistor is
_____________. [GATE EC 1992, IIT-Delhi]
2 kW

2 mA 1 kW
2 kW

Q.3 The approximate input impedance of the Op - Amp circuit shown in given figure is [IES EC 1993]
100 kW

10 kW

V0
Vi
10 kW

(A) Infinite (B) 120 k (C) 110 k (D) 10 k

Q.4 In the circuit shown in the figure, the expression for I 0 / I i is [IES EE 1993]

RL
V0
I0
Ii
R

R0 Rf
(A) (B)
RL  R RL
Rf Rf
(C) 1  (D) 1 
RL RL
Q.5 The input resistance of the Op-Amp circuit shown in figure is [GATE IN 1994, IIT-Kharagpur]
100 kW

1 kW
Vi
V0

(A) 100 k (B) 99 k

(C) 1 k (D) 101 k
Q.6 Let the magnitude of the gain in the inverting Op-Amp amplifier circuit shown in be x with switch S 1
open. When the switch S 1 is closed, the magnitude of gain becomes
[GATE EE 1996, IISc-Bangalore]
S1
R R
R _
V1
V0
+

(A) x / 2 (B)  x (C) 2x (D) 2x

Q.7 In the Op-Amp circuit shown in figure the output voltage V0 is equal to [GATE IN 1997, IIT-Delhi]

100 kW
10 kW

(A) 11 V (B) –10 V (C) 9 V (D) 1 V

5 kW

V0
2V

100 kW
10 kW

(A) – 4 V (B) 6 V (C) 5 V (D) – 5.5 V

Q.9 The transfer gain for the circuit shown in the figure is given by [IES EE 1997]
R2 R3

R4
R1
Vi
V0

 R2 R3   R3 R4 
 R2  R3  R   R  R  R2 
(A)   4
 (B)   3 4

 R1   R1 
   

 R2 R4   R3 R4 
 R  R  R3   R  R  R2 
(C)   2 4
 (D)   3 4

 R 1   R 1 
   
Q.10 In the circuit shown in the given figure, the output voltage will be [IES EE 1998]
100 W

V0
100 mA 1W

(A) 9 V (B) – 10 V (C) 11 V (D) 12 V

5
Q.11 The open-loop gain of an operational amplifier is 10 . An input signal of 1 mV is applied to the inverting
input with the non-inverting connected to the ground. The supply voltage ± 10V. The output of the
amplifier will be [IES EE 1998]
(A) + 100 V (B) – 100 V
(C) +10 V (approximately) (D) – 10 V (approximately)
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 4 GATE ACADEMY®
Q.12 The output voltage V0 of the given circuit [IES EC 1999]
1kW

1 mA

RL
90 kW

10 kW

(A) –100 V (B) –100 mV (C) 10 V (D) –10 mV

Q.13 In an inverting amplifier, the two input terminals of an ideal Op-Amp are at the same potential because
[IES EE 1999]
(A) The two input terminals are directly shorted internally.
(B) The input impedance of the Op-Amp is infinity.
(C) CMRR is infinity.
(D) The open-loop gain of the Op-Amp is infinity.
Q.14 The feedback factor for the circuit shown in figure is [GATE EE 2000, IIT-Kharagpur]
+
100 W

+ _
VS 90 W 1k
_
10 W

(A) 9 / 100 (B) 9 / 10 (C) 1 / 9 (D) 1 / 10

Q.15 The circuit shown in figure uses an ideal Op-Amp working with +5 V and – 5 V power supplies. The
output voltage V0 is equal to [GATE EE 2000, IIT-Kharagpur]
1 kW

+5V

V0
1 mA
-5V

(A) +5 V (B) –5 V (C) + 1 V (D) –1 V

Q.16 The ideal Op-Amp has the following characteristics [GATE EC 2001, IIT-Kanpur]
(A) Ri  , A  , R0  0 (B) Ri  0, A  , R0  0
(C) Ri  , A  , R0   (D) Ri  0, A  , R0  
Q.17 The inverting Op-Amp shown in the figure has an open-loop gain of 100. The closed-loop gain V0 / Vs is
[GATE EC 2001, IIT-Kanpur]

R1 = 1 kW
_
Vs Vi
+ V0

(A) – 8 (B) – 9 (C) – 10 (D) – 11

Q.18 In the circuit shown in the given figure, the current I through the resistance R is [IES EC 2001]
10 kW 10 kW
2V
_
741 V0
+
1 kW 1 kW

I R

(A) 100 A (B) 100 A (C) 1 mA (D) 2 mA

Q.19
+
VS
_
I0 RL

An Op-Amp is used in the circuit as shown in the above figure. The current I 0 is [IES EE 2001]
VS RL VS VS  1 1 
(A) (B) (C) (D) VS   
RS ( RL  RS ) RS RL  RS RL 
Q.20 A circuit with Op-Amp is shown in the below figure. The voltage V0 is [IES EE 2001]
2R

R
VS2
V0
VS1

(A) 3VS1  6VS2 (B) 2VS1  3VS2 (C) 2VS1  2VS2 (D) 3VS1  2VS2
Q.21 In a circuit, if the open loop gain is 106 and output voltage is 10 volt, the differential voltage should be
[IES EC 2002]
(A) 10 V (B) 0.1 V (C) 100 V (D) 1 V
Q.22 An operational amplifier possesses [IES EC 2002]
(A) Very large input resistance and very large output resistance.
(B) Very small input resistance and very small output resistance.
(C) Very large input resistance and very small output resistance.
(D) Very small input resistance and very large output resistance.
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 6 GATE ACADEMY®

Q.23 Assuming the operational amplifier to be ideal, the gain Vout / Vin for the circuit shown in the given figure
is [GATE EE 2003, IIT-Madras]
10 kW 10 kW
1 kW

1 kW _
Vin
Vout
+

(A) –1 (B) – 20 (C) – 100 (D) – 120

Q.24 The Op-Amp and the 1 mA current source in the circuit of below figure are ideal. The output of the Op-
Amp is [GATE IN 2003, IIT-Madras]

(A) – 1.5 mA (B) – 1.5 V (C) – 7.5 V (D) + 1.5 V

Q.25 Consider the following statements with reference to an ideal voltage follower circuit as shown below

1. Unity gain and no phase shift. [IES EE 2003]

2. Infinite gain and 1800 phase shift.
3. Very high input impedance and very low output impedance.
4. It is a buffer amplifier.
Which of these statement are correct ?
(A) 1 and 3 (B) 2 and 4 (C) 1, 3 and 4 (D) 1, 2, 3 and 4
Q.26 In the Op-Amp circuit as shown below, the current iL is [IES EE 2003]
ZL
iL
R1

(A) Vi / Z L (B) Vi / ( Z L || R1 ) (C) Vi / R1 (D) Vi ( R1  Z L )

R1
Vi _
+ V0

R2
R2
iL RL

Vi Vi
(A)  (B)
R2 R2
Vi Vi
(C)  (D)
RL R1
Q.29 The input resistance RIN (  Vx / ix ) of the circuit in figure is [GATE EE 2004, IIT-Delhi]
R1 = 10 kΩ R2 = 100 kW

_
Vy
+

Vx
ix R3 = 1 MW

(A) 100 k (B) 100 k (C) 1 M (D) 1 M

Q.30 The value of V0 in the circuit, shown in below figure is [GATE IN 2004, IIT-Delhi]

(A) – 5 V (B) – 3 V (C) + 3 V (D) + 5 V

V 
Q.31 The gain  0  of the amplifier circuit shown in below figure is [GATE IN 2004, IIT-Delhi]
 Vi 
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 8 GATE ACADEMY®

R 3R
_

+ RL
+
RL V0
R 4R _
_
Vi
+

3R L
(A) 8 (B) 4 (C) – 4 (D)
R
Q.32 What is the load current I L in the circuit below? [IES EC 2004]
1kW 1kW
10 V
+ 15 V

-15 V
Vb
1kW IL 1kW

200 W

(A) – 5 mA (B) – 10 mA (C) 25 mA (D) 50 mA

Q.33 Consider the following circuit : [IES EE 2004]
Vs

I0
RL

Which one of the following is the correct expression for the current I 0 ?
VS RL VS
(A) (B)
RS ( RL  RS ) RS

VS  1 1 
(C) (D) VS   
RL  RL RS 

10 kW _
V0
+ +
Vi _
~

(A) 30/4 k (B) 10 k (C) 40 k (D) 

Q.35 Consider the inverting amplifier, using an ideal operational amplifier shown in the figure. The designer
wishes to realize the input resistance seen by the small-signal source to be as large as possible, while
keeping the voltage gain between –10 and –25. The upper limit on RF is 1M . The value of R1 should
be [GATE EE 2005, IIT-Bombay]
RF
R1
Vin _

+ Vout

(A)  (B) 1 M (C) 100 k (D) 40 k

Q.36 For the circuit given below, what is I L equal to? [IES EC 2005]
R R
V
+ VCC

- VCC
Vb
R IL R

V V V V
(A) (B) (C) (D)
RL R R  RL 2 R  RL
Q.37 What is the output voltage V0 of the below circuit? [IES EC 2007]
100 kW
470 kW
10 kW 22 kW
47 kW
2.2 kW

1 mV V0

(A) –1.1 V (B) 1.1 V (C) 1.0 V (D) 10 V

R1
Vin
Vout

(A)  (B) 1M (C) 100 k (D) 40 k

Q.39 The nature of feedback in the Op-Amp circuit shown is [GATE EE 2009, IIT-Roorkee]
+ 6V
1kW 2 kW
-
Vout
+
- 6V
Vin ~

(A) Current - Current feedback (B) Voltage - Voltage feedback

(C) Current - Voltage feedback (D) Voltage - Current feedback
Q.40 The input resistance of the circuit shown in the figure, assuming an ideal Op-Amp is
[GATE IN 2009, IIT-Roorkee]
2R

R 3R

Vi
_

+ V0

R 2R 4R
(A) (B) (C) R (D)
3 3 3
Q.41 Assuming the Op-Amp to be ideal, the voltage gain of the amplifier shown below is
[GATE EC 2010, IIT-Guwahati]
R1
_
V0
R2 +
Vi +
_

R2 R3  R || R   R  R3 
(A)  (B)  (C)   2 3  (D)   2 
R1 R1  R1   R1 
Q.42 Given that the Op-Amp is ideal, the output voltage V0 is [GATE EE 2010, IIT-Guwahati]
2R

R _ +10V

V0
+ _10V
+2 V

(A) 4 V (B) 6 V (C) 7.5 V (D) 12.12 V

Q.43 Consider the following Op-Amp circuit [IES EC 2011]
470 kW

V1 = 40 mV 47 kW
+ 12 V
V2 = 20 mV 4.7 kW
–

+ V0
-12 V

What is the output voltage for the above circuit?

(A)  4.8V (B)  1.2 V (C)  2.4 V (D)  2.4 V
Q.44 Virtual ground property of operational amplifier indicates that [IES EE 2012]
(A) inverting and non-inverting terminals are connected to ground.
(B) inverting and non-inverting terminals are at the same potential.
(C) system is at rest.
(D) any one terminal is connected to ground.
Q.45 In the circuit shown below the Op-Amps are ideal. Then Vout in Volts is
[GATE EC/EE/IN 2013, IIT-Bombay]
1 kW 1 kW
-2V
+15 V
+15 V
–

+ Vout

1 kW -15 V
-15 V

+ 1V 1 kW
1 kW

(A) 4 (B) 6 (C) 8 (D) 10

V1 –
R V0
2R V2 +
R

5 5 3 7 11
V1  3V2
(A) (B) 2V1  V2 (C)  V1  V2 (D) 3V1  V2
2 2 2 2 2
Q.47 The amplifier in the figure has gain of – 10 and input resistance of 50 k . The values of Ri and R f are
[GATE IN 2014, IIT-Kharagpur]
Rf

Ri
–
V0
Vin + +
–

(A) Ri  500k, R f  50k (B) Ri  50k, R f  500k

(C) Ri  5k, R f  10k (D) Ri  50k, R f  200k
V0
Q.48 Assuming an ideal Op-Amp in linear range of operation, the magnitude of the transfer impedance in
i
MΩ of the current to voltage converter shown in the figure is ________.
[GATE IN 2014, IIT-Kharagpur]
R1 = 45 kW R2 = 5 kW

R3 = 55.5 kW
Vi –
V0
+

Q.49 Assuming that the Op-Amp in the circuit shown below is ideal, the output voltage V0 (in volts) is ____.
[GATE EC 2015 (Set-02), IIT-Kanpur]
2 kΩ

+12 V
1 kΩ -
V0
+

1V -12 V

- +
V0

250(1 - d)Ω 250(1+d)Ω

100W 50W

Q.51 In the circuit shown, assume that the Op-Amp is ideal. If the gain (V0 / Vm ) is 12, the value of R
(in k ) is ______. [GATE EC 2015 (Set-03), IIT-Kanpur]
10 kW 10 kW

R
Vin
10 kW V0

Q.52 For the circuit shown below, taking the op-amp as ideal, the output voltage Vout in terms of the input
voltages V1, V2 and V3 is [GATE EE 2016 (Set - 02), IISc Bangalore]
9W

+ VCC
1W
V3
1W Vout
V1

V2 4W
-VSS

(A) 1.8V1  7.2V2  V3 (B) 2V1  8V2  9V3

Vi
V0

[IES EE 2016]
The operational amplifier circuit shown in figure having a voltage gain of unity has
(A) High input impedance and high output impedance.
(B) High input impedance and low output impedance.
(C) Low input impedance and low output impedance.
(D) Low input impedance and high output impedance.
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 14 GATE ACADEMY®
Q.54 For the circuit shown below, assume that the Op-Amp is ideal.
R

R R

R
–
+ v0
2R
vs
2R
Which one of the following is TRUE? [GATE EE 2017 (Set - 02), IIT Roorkee]
(A) v0  vs (B) v0  1.5 vs (C) v0  2.5 vs (D) v0  5 vs

Q.55 The output V0 shown in the figure, in volt, is close to [GATE IN 2017, IIT Roorkee]
2 kW

+ 15 V
1 kW

V0
10 V
-15 V

(A) 20 (B) 15 (C)  5 (D) 0

Q.56 If an input impedance of op-amp is finite, the which one of the following statements related to virtual
ground is correct? [IES EC 2017]
(A) Virtual ground condition may exist.
(B) Virtual ground condition cannot exist.
(C) In case of op-amp, virtual ground condition always exists.
(D) Cannot make a valid declaration
Q.57 In the Op-Amp circuit shown in the output would be [IES EC 1991]
10 kW

1 kW
10 mV
1 kW V0
30 mV

10 kW

(A) 400 mV (B) 300 mV (C) 200 mV (D) 100 mV

Q.58 Given figure, shows a non-inverting Op-Amp summer with V1  2 V and V2   1V the output voltage
V0  ______________. [GATE EE 1994, IIT-Kharagpur]

R V

R V0
V
2V
R
-1V

Q.59 The output voltage (V0 ) of the circuit shown in below figure is [GATE IN 1995, IIT-Kanpur]
100 kW

10 kW
2V
10 kW V0
5V

100 kW

(A) – 20 V (B) 20 V (C) – 30 V (D) 30 V

Q.60 A non-inverting Op-Amp amplifier is shown in figure. The output voltage V0 is
[GATE EE 1996, IISc-Bangalore]
2R
R _

R
V0
_2V
+
R
(2 + sin(100t )) V

(A) (3 / 2) sin(100t) (B) 3sin(100t)

(C) 2 sin(100t) (D) None of these
Q.61 A non-inverting Op-Amp summer is shown in the figure. The output voltage V0 is [IES EE 1997]
R 2R

R V0
- 3V
R
3 + sin100t

3
(A) sin100t (B) sin100t (C) 2 sin100t (D) 3sin100t
2
Q.62 The expression for the output voltage V0 in terms of the input voltage V1 and V2 in the circuit shown in
the figure, assuming the operational amplifier to be ideal is [IES EE 1997]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 16 GATE ACADEMY®
100 kW

10 kW
V2
V0
V1
11kW
99 kW

V0  AV1 1  A2V2 . The value of A1 and A2 would be respectively.

(A) 9 and –10 (B) 9.9 and –10 (C) – 9 and 10 (D) – 9.9 and 10
Q.63 The output voltage of the circuit shown in the given figure is [IES EE 1998]
2R

R A

R V0
B
+2V
R
-1V

(A) 1.0 V (B) 1.5 V (C) 2.0 V (D) 2.5 V

Q.64 The V0 of the Op-Amp circuit shown in the given figure is [IES EC 1999]
10 kW

1kW

Vi V0

1kW
10 kW

(A) 11Vi (B) 10 Vi (C) Vi (D) Zero

Q.65 In the circuit shown in the figure, the value of output V0 is [IES EE 1999]
12 kW

4 kW
+1V
V0
+2 V
6 kW

(A) + 3 V (B) – 3 V (C) – 7 V (D) + 7 V

Q.66 A non-inverting Op-Amp is shown below (Assume ideal Op-Amp). The output voltage V0 for an input
Vi   2  sin(100t ) V is [IES EC 2002]
2R

_
R
V0
_2 V
+
R
Vi
R
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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GATE ACADEMY® 17 Operational Amplifier (Questions)
3
(A) sin(100t ) V (B) 3sin(100t ) V
2
1
(C) 2sin(100t ) V (D) [3sin(100t )  ] V
2
Q.67 If an Op-Amp in the figure is ideal, the output voltage Vout will be equal to
[GATE EC 2003, IIT-Madras]
5 kW

1kW
2V _
Vout
+
3V
1kW
8 kW

(A) 1 V (B) 6 V (C) 14 V (D) 17 V

Q.68 In the circuit shown in below figure, the Op-Amps used are ideal. The output V 0 is
[GATE IN 2003, IIT-Madras]

(A) 3.0 V (B) 1.5 V (C) 1.0 V (D) 0.5 V

Q.69 In the Op-Amp circuit shown above (assuming ideal Op-Amp). The voltage V0 is [IES EC 2003]
22 kW

2.2 kW

V0
Vi = 0.5 V
2.2 kW
22 kW

(A) V0   5 V (B) V0  5 V (C) V0  0 (D) V0   2 V

Q.70 The output of the Op-Amp in the circuit of below figure is [GATE IN 2004, IIT-Delhi]

(A) 0 V (B) – 3 V (C) + 1.5 V (D) + 3 V

10 kW
2V
V0
1V
10 kW
100 kW

What is the output voltage V0 in the above Op-Amp circuit?

(A) 10V (B) – 10V (C) 11 V (D) – 11 V
Q.72 Consider the following circuit : [IES EC 2004]
10 kW 22 kW
V-
R1 R2

1.5 kW V0
V+
R3
R4

What is the value of R4 in the below in the circuit, if the voltage V and V are to be amplified by the
same amplification factor?
(A) 7 k (B) 22 k (C) 3.3 k (D) 35 k
Q.73 Consider the following circuit [IES EE 2004]
1 kW 1 kW
1V
2 kW
1V
3 kW
1V

1 kW V0
1V
1 kW
1V
1 kW
1V
What is the output voltage V0 in the above circuit?
(A) 9.5 V (B) 3 V (C) 32.2 V (D) 1 V
Q.74 For the Op-Amp circuit shown in the figure. The voltage V 0 is [GATE EC 2007, IIT-Kanpur]
2 kW

1kW _
1V V0
1kW +

1kW

(A) – 2 V (B) – 1 V (C) – 0.5 V (D) 0.5 V

Va _
50 kW
+
Vb +
50 kW V0
50 kW –

(A) 5Va  2.5Vb (B) 5Va  3Vb (C) 2.5Va  2.5Vb (D) 2.5Va  3Vb
Q.76 Consider the following Op-Amp circuit [IES EE 2010]
3R

R V0
-4V
R
(4 - 2 cos wt )

The value of V0 is
(A)  0.75 V (B) 2 cos t V (C)  8cos t V (D) 16 V
Q.77 [IES EE 2011]

In the given circuit magnitude of the voltage V0  3V1  2V2  7V3 , then the values of R1 , R2 , R3 and R4
are
1 1 7
(A) 3 k, 2 k, 7 k and 1 k (B) k, 6 k, k and 12 k
4 6 12
12 1 1 1
(C) 4 k, 6 k, k and 12 k (D) k, 6 k, k and 12 k
7 3 2 7
Q.78 In the circuit shown, V0  V0 A for switch SW in position A and V0  V0 B for SW in position B. Assume
V0 B
that the Op-Amp is ideal. The value of is ______. [GATE EC 2015 (Set-02), IIT-Kanpur]
V0 A

5V 1 kΩ
-

V0
1 kΩ
B A +
SW 1 kΩ
1V 1 kΩ

Q.79 In the circuit below, the operational amplifier is ideal. If V1  10 mV and V2  50 mV , the output voltage
(Vout ) is [GATE EE 2019, IIT Madras]
100 kΩ

10 kΩ
V1
V2 Vout
10 kΩ
100 kΩ

(A) 500 mV (B) 100 mV (C) 600 mV (D) 400 mV

Q.80 An op-amp based circuit is implemented as shown below. [GATE EC 2018, IIT Guwahati]
31 kW

1 kW +15V
–
+ A
v0
1V +
– +
–15V –

In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place)
at node A, connected to the negative input of the op-amp as indicated in the figure is _______.
Q.81 If the input to the circuit of figure is a sine wave the output will be [GATE EC 1990, IISc-Bangalore]
Input
Output

(A) A half-wave rectified sine wave

(B) A full-wave rectified sine wave
(C) A triangular wave
(D) A square wave
Q.82 Given that the open-loop gain of the Op-Amp shown in the figure is 100000 ( 105 ) , the approximate
output voltage (V0 ) will be [IES EC 1991]

10 mV
V0
12 mV
10 kW
-12 V

(A) +12 V (B) – 12 V (C) – 2 V (D) – 0.2 V

Q.83 The circuit shown in the figure is that of [GATE EC 1996, IISc-Bangalore]
Vin
V0

R1
R2

(A) a non-inverting amplifier (B) an inverting amplifier

(C) an oscillator (D) a Schmitt trigger
Q.84 One input terminal of high gain comparator circuit is connected to ground and a sinusoidal voltage is
applied to the other input. The output of comparator will be [GATE EC 1998, IIT-Delhi]
(A) A sinusoid (B) A full rectified sinusoid
(C) A half rectified sinusoid (D) A square wave
Q.85 If the input to the ideal comparator shown in the figure is a sinusoidal signal of 8V (peak to peak)
without any DC component, then the output of the comparator has a duty cycle of
[GATE EC 2003, IIT-Madras]

Input
Output
Vref = 2 V

1 1 1 1
(A) (B) (C) (D)
2 3 6 12
Q.86 The voltage comparator shown in fig. can be used in the analog-to-digital conversion as
[GATE EE 2004, IIT-Delhi]
V1 +
V0
V2 _

(A) a 1-bit quantizer (B) a 2-bit quantizer

(C) a 4-bit quantizer (D) a 8-bit quantizer
Q.87 Given the ideal operational amplifier circuit shown in the figure indicate the correct transfer
characteristics assuming ideal diodes with zero cut-in voltage. [GATE EC 2005, IIT-Bombay]

0.5 kΩ

2 kΩ

V0 V0
+ 10 V +10 V

(A) –8 V +5 V
Vi (B) –5 V +8V
Vi

–10 V –10 V
V0
+5 V V0
+ 10 V

–10 V –5V
Q.88 An operational-amplifier circuit is shown in the figure. [GATE EE 2014, IIT-Kharagpur]
R

R
+Vsat
+Vsat –
Vi –
V0
+
+ -Vsat
-Vsat

R2
R1

The output of the circuit for a given input vi is

R   R 
(A)   2  vi (B)  1  2  vi
 R1   R1 
 R 
(C)  1  2  vi (D) Vsat or Vsat
 R1 

_
Vi
V0
+
10 k

10 k _ 15 V

A triangular wave which goes from – 12 V to 12 V is applied to the inverting input of the Op-Amp.
Assume that the output of the Op-Amp swings from – 15 V to + 15 V.
The voltage at the non-inverting input switches between
(A) – 12 V and + 12 V (B) – 7.5 V and + 7.5 V (C) – 5 V and + 5 V (D) 0 V and 5 V
Q.90 An ideal Op-Amp circuit and its input waveform are shown in the figures. The output waveform of this
circuit will be [GATE EE 2009, IIT-Roorkee]
+6 V
1 kW
Vin
3
Vin -
Vout
2
1 + 2 kW
t 4 t5 t6
0 t t2 t3 t –3 V
–1 1
–2
–3 1 kW

(A) Vout (B) Vout

6 6

t3 t6 t3 t6
0 t 0 t

–3 –3

Vout
(C) (D) Vout
6 6

t6
0 t t
t2 t4 0 t2 t4 t6
–3
–3
Q.91 For the circuit shown below, [GATE EE 2011, IIT-Madras]
R

+12 V
R +12 V
–
Vi R –
+ vx V0
+
–12 V
R –12 V

R R

+12 V +12 V

+6V +6V Vi
Vi
(A) –6 V (B) –6V

–12 V – 12 V

V0 V0

+12 V +12 V

– 12 V – 12 V

Q.92 In the Op-Amp circuit shown below the input voltage Vin is gradually increased from – 10 V to + 10 V.
Assuming that the output voltage Vout saturates at – 10 V and + 10 V, Vout will change from
[GATE IN 2008, IISc-Bangalore]
Vin _
Vout
+

9 kW
1 kW

(A) – 10 V to + 10 V when Vin = – 1 V (B) – 10 V to + 10 V when Vin = + 1 V

(C) + 10 V to – 10 V when Vin = – 1 V (D) + 10 V to – 10 V when Vin = + 1 V
Q.93 The circuit of a Schmitt trigger is shown in the figure. The Zener diode combination maintains the
output between  7 V . The width of the hysteresis band is _______V.
[GATE IN 2017, IIT-Roorkee]
+ 15 V
Vi 1 kW
V0

VZ
-15 V
10 kW
VZ

0.5 kW

+2V

5 kW

+ 3V
–

(A) + 5 V and  5V (B) + 7 V and  3V

(C) 3V and  7 V (D) +3 V and  3V
Q.95 If the inverting input terminal of an operational amplifier is grounded and a sinusoidal voltage waveform
is applied at the non-inverting input terminal, the output will be [IES EC 2015]
(A) Square wave (B) Triangular wave
(C) Half-wave rectified sine wave (D) Full-wave rectified sine wave
Q.96 A comparator circuit is used to [IES EE 2012]
(A) mark the instant when an arbitrary waveform attains some reference level.
(B) switch off a circuit when output becomes zero.
(C) switch on and off a circuit alternately at a particular rate.
(D) mark the instant when the input voltage becomes constant.
Q.97 In the bistable circuit shown, the ideal Op-Amp has saturation levels of  5 V . The value of R1
(in k  ) that gives a hysteresis width of 500 mV is _____. [GATE EC 2015 (Set-02), IIT-Kanpur]
R2 = 20 kΩ

R1
+
V0
Vi +
- -

Q.98 In the Schmitt trigger circuit shown in fig. Find upper threshold point. [GATE EE 2004, IIT-Delhi]
+12
Vi _
+ V0

-12

10 kW
2 kW

(A) 1 V (B) 2 V (C) 4 V (C) 3 V

3 kW
+2 V
(A) 5 V in the positive slope only. (B) 5 V in the negative slope only.
(C) 5 V in the positive and negative slopes. (D) 3 V in the positive and negative slopes.
. Statement for Linked Answer Questions 100 and 101 .
In the Schmitt trigger circuit shown below, the Zener diodes have VZ (reverse saturation voltage) = 6 V
and VD (forward voltage drop) = 0.7 V. [GATE IN 2006, IIT-Kharagpur]
+12 V

+ - R
Vi +
- + Vo
R1 -
-12 V

+1.5 V

R1
Q.100 If the circuit has the input lower trip point (LTP) = 0 V, then value of is given as
R2
(A) 0.223 (B) 2.67 (C) 4.67 (D) 
Q.101 The input upper trip point (UTP) of the Schmitt trigger is
(A) 1.5 V (B) 2.1 V (C) 2.42 V (D) 6.7 V
Q.102 The components in the circuit shown below are ideal. If the op-amp is in positive feedback and the input
voltage Vi is a sine wave of amplitude 1 V, the output voltage V0 is
[GATE EC 2020, IIT Delhi]
1k

1V 1k 5V
0 Vi
1V V0

5 V

(A) a constant of either +5V or –5V. (B) a non-inverted sine wave of 2 V amplitude.
(C) an inverted sine wave of 1 V amplitude. (D) a square wave of 5 V amplitude.
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
https://www.gateacademy.shop/ Live class room: https://play.google.com/store/apps/details?id=com.gateacademy1 http://onlinetestseries.gateacademy.co.in
GATE ACADEMY® 27 Operational Amplifier (Questions)
Q.103 Figure shows a Schmitt trigger circuit and the corresponding hysteresis characteristics. The values of
VTL and VTH are [GATE IN 2004, IIT-Delhi]
+ 10 V + 10 V
_
V0
+
- 10 V
5 kW
- 10 V
Vi + 10 kW
–
VTL VTH

(A) VTL  3.75 V, VTH  3.75 V (B) VTL  1 V, VTH  5 V

(C) VTL  5 V, VTH  1 V (D) VTL  5 V, VTH  5 V
Q.104 The input-output characteristic of a Schmitt trigger has a hysteresis band of  0.1 V. If the input voltage
is 5sin(1000 t ), the delay between the corresponding zero cross-over points of the output and input
signals is [GATE IN 2005, IIT-Bombay]
(A) 6.37 s (B) 0.02 s (C) 63.7 s (D) 2.0 s
Q.105 The circuit shown in figure is that of a waveform generator. Assuming ideal devices, and  12 V
supply, the output V0 is [GATE IN 2003, IIT-Madras]
10 kW

+ 12 V
500 W
V0
1mF
-12 V
6V

10 kW
10 kW 6V

(A) triangular wave of period 120 ms and amplitude  6V

(B) square wave of period 60 ms and amplitude  6V
(C) square wave of period 22 ms and amplitude  6V
(D) square wave of period 60 ms and amplitude  12V
Q.106 An oscillator circuit using ideal Op-Amp and diodes is shown in the figure.
R

+5V
V0
C -5V
D1
3kW

1kW

D2
1kW

The value of e RC
will be ________. [GATE EE 2014, IIT-Kharagpur]
Q.107 The saturation voltage of the ideal Op-Amp shown below is ±10 V. The output voltage V0 of the
following circuit in the steady-state is [GATE EE 2015 (Set-02), IIT-Kanpur]
1 kW

+10 V
0.25 mF
V0
2 kW
-10 V

2 kW

(A) Square wave of period 0.55 ms (B) Triangular wave of period 0.55 ms
(C) Square wave of period 0.25 ms (D) Triangular wave of period 0.25 ms
Q.108 The switch S in the circuit of the figure is initially closed. It is opened at time t = 0. You may neglect the
Zener diode forward voltage drops. What is the behavior of Vout for t > 0 ?
[GATE EE 2007, IIT-Kanpur]
+10 V +10 V
_
1 kΩ
Vout
S + + 10 kΩ 5.0 V
0.01
mF –10 V 5.0 V
100 kΩ

–10 V
(A) It makes a transition from – 5 V to + 5 V at t  12.98μs
(B) It makes a transition from – 5 V to + 5 V at t  2.57 μs
(C) It makes a transition from + 5 V to – 5 V at t  12.98μs
(D) It makes a transition from + 5 V to – 5 V at t  2.57 μs
Q.109 A hysteresis type TTL inverter is used to realize an oscillator in the circuit shown in the figure.
[GATE EE 2014, IIT-Kharagpur]
10 kW

+5 V

0.1 mF

(A) 5.00 ms (B) 8.75 ms (C) 10.00 ms (D) 13.75 ms

Q.111 In the circuit shown in the figure the input voltage Vi is a symmetrical saw-tooth wave of average value
zero, positive slope and peak-to-peak value 20 V. The average value of the output, assuming an ideal
operational amplifier with peak-to-peak symmetrical swing of 30 V, is [GATE IN 2005, IIT-Bombay]
Vi
V0

10 kW
5 kW

(A) 5 V (B) 10 V (C) – 5 V (D) 7.5 V

Q.112 In the circuit shown below, all Op-Amps are ideal. The current I  0 A when the resistance R 
________ k . [GATE IN 2019, IIT-Madras]
R
3kW
12 kW
3kW
- 3kW
I =0 -
+
+
3kW

1V +
-

Q.113 The circuit given uses ideal opamps. The current I (in  A ) drawn from the source vs is (up to two
decimal places) ______. [GATE IN 2018, IIT-Guwahati]
10.1kW

20.0 kW
20.0 kW

Vs = 1V - 20.0 kW
I 10 kW -

10 kΩ

Vi V0
10 kΩ

(A) remain constant at + 1 (B) remain constant at – 1

Q.116 In the circuit given below, the OP-AMP is ideal. The output voltage V0 in volt is ________.

[GATE IN 2016, IISc Bangalore]

20 kW

20 kW
10 kW
2V
V1 V0
20 kW
10 kW

Q.117 In the circuit given below, the OP-AMP is ideal. The value of current I L in microampere is ______

[GATE IN 2016, IISc Bangalore]

100 kW

1V
10 kW
10 kW
IL
RL

Q.118 In the circuit of the figure, V0 is [GATE EC 2000, IIT-Kharagpur]

+15 V

V0
+1V
R -15 V

R
(A) – 1 V (B) 2 V (C) + 1 V (D) + 15 V
Q.119 The Op-Amp of the circuit shown in the below figure has a unity gain frequency of 1 MHz.
The cut-off frequency of the feedback amplifier is [IES EC 1995]

Vin V0

90 kW
10 kW 10 kW

(A) 100 kHz (B) 1 MHz (C) 10 MHz (D) 90 MHz

Q.120 In the circuit shown in below figure, if Vi  sin t , the voltage V0 is [GATE IN 1996, IISc-Bangalore]
10 kW 10 kW

V0
100 kW

Vi 10 mF

  1  
(A) 2 sin  t   (B) sin  t  
 4 2  4
1    
(C) sin  t   (D) 2 sin  t  
2  4  4
Q.121 If the input signal ei applied to the Op-Amp of the circuit shown in the given figure is sinusoidal of
maximum value 1 mV and of 1 kHz frequency, then the magnitude of the peak value of the output
voltage waveform would be [IES EE 1996]
100 kW

1 mF e0

(A) 1.59 mV (B) 6.28 mV (C) 159 mV (D) 628 mV

1 MW
Vin
V0

(A) + 20 V (B) + 10 V (C) – 10 V (D) – 20 V

Q.123 The voltage gain versus frequency of an Op-Amp is shown in the given figure. The gain bandwidth of
the Op-Amp is [IES EC 1999]
Voltage gain
80 dB

– 20 dB/decade

0 dB Frequency
20 Hz
(A) 200 Hz (B) 200 MHz (C) 200 KHz (D) 2 MHz
Q.124 Assume that the Op-Amp of the figure is ideal. If V i is a triangular wave, then V 0 will be
[GATE EC 2000, IIT-Kharagpur]
R

C
Vi
V0

(A) square wave (B) triangular wave (C) parabolic wave (D) sine wave
Q.125 In the circuit shown in the given figure, V0 is given by [IES EC 2001]
10 kW 4.14 kW

1MW V0
sin t

1mF

   
(A) sin  t   (B) sin  t   (C) sin t (D) cos t
 4  4
Q.126 In the figure, assume the Op-Amp to be ideal. The output V0 of the circuit is
[GATE EC 2001, IIT-Kanpur]

10 W
–
100 W
–
Vs = 10 cos(100t ) +
+ V0

t
(A) 10 cos(100t ) (B) 10  cos(100 ) d 
0
t
d
(C) 104  cos(100 )d (D) 10 4 cos(100 )
0
dt
Q.127 For the circuit shown, with an ideal operational amplifier, the maximum phase shift of the output Vout
with reference to the input Vin is [GATE EE 2003, IIT-Madras]

R1
R1
_
Vin Vout
+
R
C

(A) 00 (B) 900 (C)  900 (D)  1800

Q.128 The circuit in figure is a [GATE EC 2004, IIT - Delhi]

_
R R V0
Vi +

C C

(A) Low-pass filter (B) High-pass filter

1 1
(A) band-pass filter with lower cut-off l  and higher cut-off H  .
R1 C1 R2 C2

(A) High pass, 1000 rad/sec. (B) Low pass, 1000 rad/sec.
(C) High pass, 10000 rad/sec. (D) Low pass, 10000 rad/sec.
. Statement for Linked Answer Questions 131 and 132 .
Consider the Op-Amp circuit shown in the figure. [GATE EC 2007, IIT-Kanpur]
R

R _
Vi V0
+
C
R

Q.131 The transfer function V0 (s) / Vi (s) is

1  sRC 1  sRC
(A) (B)
1  sRC 1  sRC
1 1
(C) (D)
1  sRC 1  sRC
Q.132 If Vi  V2 sin(t ) and V0  V2 sin(t  ) , then the minimum and maximum values of  (in radians) are
respectively
  
(A) and (B) 0and
2 2 2

(C)   and 0 (D) and 0
2

(A) High pass filter (B) Low pass filter

(C) Band pass filter (D) Band reject filter
. Statement for Linked Answer Questions 134 and 135 .
A general filter circuit is shown in the figure. [GATE EE 2008, IISc-Bangalore]
R2

R1 C
_
Vi V0
R3 +

Q.134 If R1  R2  RA and R3  R4  RB , the circuit acts as a

(A) All pass filter (B) Band pass filter
(C) High pass filter (D) Low pass filter
Q.135 The output of the filter is given to the circuit shown in below figure

The gain vs frequency characteristic of the output (V0 ) will be

(A) (B)

Gain Gain
0 w 0 w

(A) Low pass filter with a maximum gain of 1 (B) Low pass filter with a maximum gain of 2
(C) High pass filter with a maximum gain of 1 (D) High pass filter with maximum gain of 2
Q.137 The circuit shown in the figure is [GATE IN 2009, IIT - Roorkee]
R

R _
Vi V0
+
C
R

(A) an all-pass filter (B) a band-pass filter (C) a high-pass filter (D) a low-pass filter
Q.138 An active filter is shown in the adjoining figure. The dc gain and the 3 dB cut-off frequency of the filter
respectively, are, nearly [GATE IN 2010, IIT-Guwahati]
C1

R2 R1 = 15.9 kW,
R2 = 159 kW
R1
Vi _ C1 = 1.0 nF
V0
+

(A) 40 dB, 3.14 kHz (B) 40 dB, 1.00 kHz

(C) 20 dB, 6.28 kHz (D) 20 dB, 1.00 kHz
Q.139 The circuit shown below implement a filter between the input current ii and the output voltage V 0 .
Assume that the Op-Amp is ideal. The filter implemented is a [GATE EC 2011, IIT-Madras]
L1

R1
ii
–
+ +
V0
–

C R1 +5V
+ - +
Input Output
- + -
-5V

1 1
(A) low pass filter with f 3dB  rad/s (B) high pass filter with f 3dB  rad/s
( R1  R2 ) C R1 C
1 1
(C) low pass filter with f 3dB  rad/s (D) high pass filter with f 3dB  rad/s
R1 C ( R1  R2 ) C
Q.142 [IES EE 2011]
R

R
–
Vi V0
+
R

The circuit shown is

(A) A low pass filter (B) A high pass filter
(C) A comparator (D) An all-pass filter
Q.143 In the circuit shown, the need of the resistor RF is [IES EC 2012]
RF

Ri CF
Vi
V0

R1 10 nF
Vi
1kΩ V0

Q.146 In the figure shown, assume the Op-Amp to be ideal. Which of the alternatives gives the correct bode
V ()
plots for the transfer function 0 ? [GATE EE 2014, IIT-Kharagpur]
Vi ()

1kΩ + VCC
Vi +
V0
1mF –
- VCC

æ V (w) ö
20 log ç 0 ÷ f
(A) ç V (w)
è i
÷
ø

3 2 3
0 10 0 10 10
1 10 10
2
w 1 10 w
–10 -p/ 4
–20 -p/ 2
–30

æ V (w) ö
20 log ç 0 ÷ f
(B) ç V (w)
è i
÷
ø p/2
p/4
0 103 0
1 10 102 w 1 10 10
2
10
3 w
–10 -p/ 4
–20 -p/ 2
–30

æ V (w) ö
20 log ç 0 ÷ f
(C) ç V (w)
è i
÷
ø p/2
p/4
2 2 3
0 10 0 10 10
1 10 10 3 w 1 10 w
–10 -p/ 4
–20 -p/ 2
–30

æ V (w) ö
20 log ç 0 ÷ f
(D) ç V (w)
è i
÷
ø p/2
p/4
0 0
1 10 102 103 w 1 10 102 103 w
–10 -p/ 4
–20 -p/ 2
–30

Q.147 In the circuit shown using an ideal Op-Amp, the 3-dB cut-off frequency (in Hz) is _____.
[GATE EC 2015 (Set-03), IIT-Kanpur]
Vi
10 kW 10 kW V0
0.1 mF
10 kW 10 kW

Q.148 Consider the circuit shown in the figure. In this circuit R  1k, and C  1F. The input voltage is
sinusoidal with a frequency of 50 Hz, represented as a phasor with magnitude Vi and phase angle 0
radian as shown in the figure. The output voltage is represented as a phasor with magnitude V0 and
phase angle δ radian. What is the value of the output phase δ (in radian) relative to the phase angle of the
input voltage? [GATE EE 2015 (Set-01), IIT-Kanpur]

C
-
vi = Vi Ð0 v0 = V0 Ðd
+
C
R

(A) 0 (B)  (C)  / 2 (D)   / 2

Q.149 The Op-Amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step-
voltage Vi  1mV is applied at the input at time t = 0 as shown. Assuming that the operational amplifier
is not saturated, the time constant (in millisecond) of the output voltage V0 is
[GATE EE 2015 (Set-01), IIT-Kanpur]
C

1mF
R
-
1kW
+
1mV + Vi +
- V0
A = 1000
-
t = 0s

(A) 1001 (B) 101 (C) 11 (D) 1

Q.150 The operational amplifier shown in the figure is ideal. The input voltage (in Volt) is
Vi  2sin(2 2000t ) .The amplitude of the output voltage V0 (in Volt) is _______.
[GATE EE 2015 (Set-02), IIT-Kanpur]
0.1mF

1 kW
1 kW
Vi -
V0
+

Q.151 The filters F1 and F2 having characteristics as shown in figure (a) and (b) are connected as shown in
figure (c). [GATE EE 2015 (Set-02), IIT-Kanpur]
F1 F2
V0 V0
Vi Vi
Vi V0 Vi V0

f f
f1 f2

(a) (b)

The cut-off frequencies of F1 and F2 are f1 and f 2 respectively. If f1  f 2 , the resultant circuit exhibits
the characteristic of a
(A) Band-pass filter (B) Band-stop filter (C) All pass filter (D) High-Q filter
s 2  bs  c
Q.152 The filter whose transfer function is of the form G( s)  2 is
s  bs  c
[GATE IN 2015, IIT-Kanpur]
(A) A high-pass filter (B) A low-pass filter
(C) An all-pass filter (D) A band-reject filter
104
Q.153 An op-amp has ideal characteristics expect that its open loop gain by the expression Av ( s)  .
(1  103 s)
This op-amp is used in the circuit shown in the figure. The 3-dB bandwidth of the circuit, in rad/s, is
Vi
AV V0
9 kW

1 kW

(A) 10 2 (B) 103 (C) 10 4 (D) 10 6

Q.154 For the circuit shown in the figure, R1  R2  R3  1 , L  1 H and C 1H . If the input
Vin  cos(106 t ) , then the overall voltage gain ( Vout / Vin ) of the circuit is __________.
[GATE EC 2016 (Set - 03), IISc Bangalore]
R1 R3

L
R2 C

Vout

Vin

+15 V
R1
Vin
Vout

-15 V
(A) low pass filter (B) band pass filter (C) high pass filter (D) notch filter
Q.156 The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-
amp), and has an open-loop voltage gain, A0  105 V/V and an open-loop cut-off frequency, f C  8 Hz.
[GATE EC 2017 (Set - 01), IIT Roorkee]
R2 = 79 kW

R1 = 1 kW

Vin

The voltage gain of the amplifier at 15 kHz, in V/V, is __________ .

Q.157 Assuming the Op-Amp shown in the figure to be ideal, the frequency at which the magnitude of V0 will
be 95% of the magnitude of Vin is _______kHz. [GATE IN 2017, IIT Roorkee]
10 kW

Vin 10 nF
1 kW
1 kW

Q.158 For the given low pass circuit shown in the figure, the cut-off frequency in Hz will be___________.
[GATE IN 2014, IIT-Kharagpur]
0.47μF

22 kW 22 kW
+
V0
0.47μF –
Vin

91kW
82 kW

(A) 0 Hz (B) 50 Hz (C) 2 kHz (D) 50 kHz

Q.160 Consider the circuit shown below [GATE IN 2007, IIT-Kanpur]

The correct frequency response of the circuit is

(A) V / V (B) V / V
0 i 0 i

4 dB 0 dB
1 dB -3 dB

20 dB/decade 40 dB/decade

f f
21.9 kHz 21.9 kHz

40 dB/decade 20 dB/decade

f f
21.9 kHz 21.9 kHz

Q.161 For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0 the switch S
is closed. The voltage VC across the capacitor at t  1msec is [GATE EC 2006, IIT - Kharagpur]

In the figures shown the OP-AMP is supplied with  15 V .

(A) 0 V (B) 6.3 V (C) 9.45 V (D) 10 V
Q.162 An Op-Amp has an open-loop gain of 105 and open loop upper cutoff frequency of 10 Hz. If this Op-
Amp is connected as an amplifier with a closed-loop gain of 100, then the new upper cutoff frequency
[GATE EE 2000, IIT-Kharagpur]
(A) 10 Hz (B) 100 Hz (C) 10 kHz (D) 100 kHz
Q.163 The Op-Amp in the below circuit shown a unity- gain bandwidth of 1 MHz and a dominant pole at
10 Hz. The bandwidth of the non-inverting amplifier will be [IES EE 1999]
40 kW

10 kW

(A) 10 MHz (B) 1 MHz (C) 250 kHz (D) 200 kHz
Q.164 With the ideal operational amplifier, the circuit shown in figure. The output voltage V0 is
[GATE EE 1991, IIT-Madras]
100 mF
20 kW
10 kW
10 kW

V1 5 kW V0
4 kW

V2
V3

(A) V0  2  V1dt  4V2  5V3 (B) V0  2  V1dt  2V2  4V3

(C) V0  2  V1dt  3V2  5V3 (D) V0    V1dt  4V2  5V3

Q.165 The following circuit has R 10k, C  10F The input voltage is a sinusoidal at 50Hz with an rms
value of 10 V. under ideal conditions, the current is from the source is
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
https://www.gateacademy.shop/ Live class room: https://play.google.com/store/apps/details?id=com.gateacademy1 http://onlinetestseries.gateacademy.co.in
GATE ACADEMY® 45 Operational Amplifier (Questions)
[GATE EE 2009, IIT-Roorkee]
R
10 kW
iS
+
OPAMP Vo
~ -
10 kW
C R
10 mF

(A) 10 mA leading by 900 (B) 20 mA leading by900

(C) 10 mA leading by 900 (D) 10 mA lagging by900
d 2V dV
Q.166 In the following circuit, the output ‘V’, follows an equation of the form 2
 a  bV  f (t ) . The
dt dt
value of a, b and f (t ) are respectively [GATE EE 1992, IIT-Delhi]
C
C
R
R

V
R
R

R
et

1 1 1  1  t
(A) a  , b  2 2 , f (t )  2 2 1  e
2 RC 2R C 2 R C  RC 
1 1 1  1  t
(B) a  , b  2 2 , f (t )  2 2  1  e
2 RC 2R C R C  RC 
1 1 1  1  t
(C) a  , b  2 2 , f (t )  2 2 
1 e
RC 2R C 2 R C  RC 
1 1 1  1  t
(D) a  , b  2 2 , f (t )  2 2 1  e
2 RC 2R C 2 R C  RC 
Q.167 The circuit of given figure, uses an ideal Op-Amp for small positive values of Vin the circuit works as
[GATE EC 1992, IIT-Delhi]

R
Vin _

Vout
+

(A) A half-wave rectifier (B) A differentiator

(C) A logarithmic amplifier (D) An exponential amplifier
Q.168 The Op-Amp circuit shown in the below figure can be used for [IES EC 1996]

Vin
Vout

(A) addition (B) subtraction

(C) both addition and subtraction (D) multiplication
Q.169 In the Op-Amp circuit shown below, Vi  0 and i  I 0e . The output V0 will be proportional to
kV

[IES EE 2002]

(A) Vi (B) Vi (C) e kVi (D) ln( kVi )

Q.170 In the Op-Amp circuit shown, assume that the diode current follows the equation I  I s exp (V / VT ). For
Vi  2 V, V0  V01 , and for Vi  4 V, V0  V02 . The relationship between V01 and V02 is
[GATE EC 2007, IIT-Kanpur]

2 kW
Vi _
V0
+

(A) V02  2 V01 (B) V02  e2 V01

Vi = -1 V _
100 kW V0
+

For an input voltage Vi  1V, the output voltage V 0 is

(A) 0 V (B) 0.1 V (C) 0.7 V (D) 1.1 V
Q.172 In the circuit shown below what is the output voltage (Vout ) if a silicon transistor Q and an ideal
Op-Amp are used? [GATE EC/EE/IN 2013, IIT-Bombay]

+15 V
Q
1 kW
–
Vout
+
5V
-15 V

(A) – 15 V (B) – 0.7 (C) + 0.7 V (D) + 15 V

Q.173 The approximate transfer characteristic for the circuit shown below with an ideal operational amplifier
and diode will be [GATE EE 2017 (Set - 01), IIT Roorkee]
Vss
Vin +

D
–Vss
V0

(A) V0 (B) V0 (C) V0 (D) V0

Vin Vin Vin Vin

Q.174 The transfer characteristic of the Op-Amp circuit shown in figure is

[GATE EE 2014, IIT-Kharagpur]

R +Vsat R
Vi –
R +Vsat
–
+
-Vsat + V0
R -Vsat
R

V0 V0

(A) (B)
-1 1

Vi Vi

1
-1

Q.175 In the circuit given below, the diodes D1 and D2 have a forward voltage drop of 0.6 V. The OP-AMP
used is ideal. The magnitude of the negative peak value of the output V0 in volt is ________
[GATE IN 2016, IISc Bangalore]
16 kW

10 kW D1

V0
1 sin (3000t)v

Q.176 The transfer characteristic for the precision rectifier circuit shown below is (assume ideal Op-Amp and
practical diodes) [GATE EC 2010, IIT-Guwahati]
+ 20 V R

4R D2
Vi _
R V0
+ D1

(A) V0 (B) V0

Vi Vi
– 10 – 5 0 – 10 – 5 0

Vi Vi
0 5 0 5

Q.177 The block diagrams types of half wave rectifiers are shown in the figure. The transfer characteristics of
the rectifiers are also shown within the block. [GATE EE 2008, IISc-Bangalore]
P Q

v0 v0
vin v0 vin v0
0
vin
0 vin

It is desired to make full wave rectifier using above two half-wave rectifiers. The resultant circuit will be
(A) R (B) R

Vin R
Vin R _ P
_
P
V0 V0
R
R + QP +
Q R

Q.178 The Circuit shown in the given figure can be used as a [IES EC 1994]

V0
Vi

R2
(A) For Vi  0, V0   Vi (B) For Vi  0, V0  0
R1
R2
(C) Vi  0, V0   Vi (D) Vi  0, V0  0
R1
Q.180 The cut-in voltage of diodes in the rectifier of figure shown is 0.6 V. Identify the correct output and
input characteristic ( V0 vs Vi ) [GATE IN 1993, IIT-Bombay]
10 kW

20 kW V0

10 kW D1 D2
Vi

(A) V0 (B) V0
Slope 2 Vi

Vi Slope = – 1

Vi Slope = –1
0.6 V
Q.181 In the circuit shown below, the input voltage Vin is positive. The current ( I ) - voltage (V )
V

characteristics of the diode can be assumed to be I  I 0e VT

under the forward bias condition, where VT is
the thermal voltage and I 0 is the reverse saturation current. Assuming an ideal op- amp, the output
voltage Vout of the circuit is proportion to [GATE IN 2019, IIT-Madras]

I
Vin 
 Vout

V
V 
in

(A) log e  in  (B) 2Vin (C) e VT (D) Vin2

 2VT 
Q.182 In the circuit shown in the figure, assuming ideal diode characteristics with zero forward resistance and
0.7 V forward drop, the average value of V0 when the input waveform as shown, is
[GATE IN 2005, IIT-Bombay]
Vin
D2
+1
2 kW
T
1 kW D1
0
2 T
t Vin _
V0
+
–1

(A) – 0.7 V (B) – 1.0 V (C) – 2.0 V (D) – 2.7 V

Q.183 Assuming base-emitter voltage of 0.7 V and   99 of transistor Q1. The output voltage V0 in the ideal
Op-Amp circuit shown below is [GATE IN 2011, IIT-Madras]
5V

33kW
Q1 100 W
+ 5V
–
–
V0
+
1V +
–

(A) – 1 V (B) – 1/3.3 V

(C) 0 V (D) 2 V
Q.184 In the circuit shown, the Zener diode has ideal characteristics and a breakdown voltage of 3.2 V. The
output voltage V0 for an input voltage Vi   1 V is closest to [GATE IN 2009, IIT-Roorkee]
10 kW

10 kW

1 kW _
Vi
V0
+

6 VDC

(A) 24 V (B) 28 V (C) 30 V (D) 32 V

Q.186 The output voltage of the regulated power supply shown in figure is [GATE EC 2003, IIT-Madras]
+
1 kW
15 V DC +
_
Unregulated
Power supply Vz = 3 V
40 kW Regulated
20 kW DC output
_

(A) 3 V (B) 6 V
(C) 9 V (D) 12 V
Q.187 In the voltage regulator circuit shown in the figure, the Op-Amp is ideal. The BJT has VBE  0.7 V and
  100 and the zener voltage is 4.7 V . For a regulated output of 9 V, the value of R (in  ) is
___________. [GATE EC 2014, IIT-Kharagpur]
VI = 12 V V0 = 9 V

1kΩ 1kΩ

R
Vz = 4.7 V

Q.188 For the voltage regulator circuit shown, the input voltage (Vin ) is 20 V  20% and the regulated output
voltage (Vout ) is 10 V. Assume the Op-Amp to be ideal. For a load RL drawing 200 mA, the maximum
power dissipation in Q1 (in Watts) is ______. [GATE EC 2015 (Set-02), IIT-Kanpur]
Vin Q1 Vout
4V
Vref +
R1 RL
-

R2 = 10 kΩ

. Statement for Linked Answer Questions 189 and 190 .

A regulated power supply, shown in figure below, has an unregulated input (UR) of 15 volts and
generates a regulated output Use the component values shown in the figure.
[GATE EC 2006, IIT - Kharagpur]
15 V (UR) Q1 +
1kW V0
+ 12 kW
12 kW –
_

6V 24 kW

Q.189 The power dissipation across the transistor Q1 shown in the figure is
(A) 4.8 Watts (B) 5.0 Watts
(C) 5.4 Watts (D) 6.0 Watts
Q.190 If the unregulated voltage increases by 20%, the power dissipation across the transistor Q1 is
(A) increase by 20% (B) increase by 50%
(C) remains unchanged (D) decreases by 20%
Q.191 The following signal Vi of peak voltage 8 V is applied to the non-inverting terminal of an ideal op-amp.
The transistor has VBE  0.7 V,   100, VLED  1.5 V, VCC  10 V and  VCC   10 V .
[GATE EC 2016 (Set - 01), IISc Bangalore]
10 V 10 V

100 W
8 kW + VCC

2 kW Vi 15 kW

- VCC

Vi
6V
4V
2V
t

–2V
–4V
–6V

The number of times the LED glows is ________.

Q.192 Consider the constant current source shown in the figure below. Let  represent the current gain of the
transistor. [GATE EC 2016 (Set - 01), IISc Bangalore]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 54 GATE ACADEMY®
+ VCC

Vref

R2
I0

R1 RL

The load current I 0 through RL is

   1  Vref    Vref
(A) I 0    (B) I 0   
   R   1  R

   1  Vref    Vref
(C) I 0    (D) I 0   
   2R    1  2R
Q.193 Which one of the following conditions would give V0  0 in the circuit shown in the figure?

[IES EC 1993]
R2

R1
I
V0

I
R

(A) R  R1  R2 (B) R  R2 / R1 (C) R  R2  R1 (D) R  R1 || R2

Q.194 The Op-Amp in the amplifier circuit shown in below figure has an offset voltage of 10 mV and it is ideal
otherwise. If Vi is zero, the output voltage V0 is [GATE IN 1999, IIT-Bombay]

10 kW

1kW
Vi
V0

1kW

(A) 0 (B) 10 mV (C) 100 mV (D) 110 mV

R1
Vi
V0

The resistance Rg is chosen as R1  R2 is order to

(A) increase gain (B) reduce offset voltage
(C) reduce offset current (D) increase CMRR
Q.196 In the circuit shown, the Op-Amp has finite input impedance, infinite voltage gain and zero input offset
voltage. The output voltage Vout is [GATE EC 2014, IIT-Kharagpur]
R2

R1 I1
Vout
I2

(A)  I 2 ( R1  R2 ) (B) I 2 R2
(C) I1R2 (D)  I1 ( R1  R2 )
Q.197 For the Op-Amp shown in the figure, the bias currents are I b1  450 nA and I b 2  350 nA .The values of
the input bias current ( I B ) and the input offset current ( I f ) are [GATE IN 2014, IIT-Kharagpur]
Ib1
–

+
Ib2

(A) I B  800 nA, I f  50nA

(B) I B  800 nA, I f  100nA

(C) I B  400 nA, I f  50nA

(D) I B  400 nA, I f  100nA

Q.198 An Op-Amp has a finite open loop voltage gain of 100. Its input offset voltage Vios ( 5 mV) is modeled
as shown in the circuit below. The amplifier is ideal in all other respects, Vinput is 25 mV.

A0 = 100

Vios = 5 mV

Vinput

The output voltage (in millivolts) is ______________. [GATE EC 2016 (Set - 02), IISc Bangalore]
Q.199 In the circuit given below, each input terminal of the OP-AMP draws a bias current of 10 nA. The effect
due to these input bias currents on the output voltage V0 will be zero, if the value of R chosen in kilo-
ohm is_________ [GATE IN 2016, IISc Bangalore]
60 kW

30 kW
V0

Q.200 The Op-Amp used in the inverting amplifier shown in below figure has an equivalent input offset
voltage Vios of 5 mV. The output offset voltage is [GATE IN 2003, IIT-Madras]

(A) 5 mV (B) 280 mV (C) 285 mV (D) 560 mV

Q.201 In the circuit shown in the following figure, the op amp has input bias-current I b  10 nA, and input
offset voltage Vi 0  1mV . The maximum dc error in the output voltage is
[GATE IN 2006, IIT - Kharagpur]

(A) 1.0 mV (B) 2.0 mV (C) 2.5 mV (D) 3.0 mV

C R
V1
V0
V2
C R
10 R

(A) 0 (B) 2 mV (C) 11 mV (D) 22 mV

Q.203 In the case of the circuit shown in the figure, Vi 0  10 mV dc maximum, the maximum possible output
offset voltage V00 caused by the input offset voltage Vi 0 with respect to ground is [IES EC 1997]
R1 R2
1kW + 10 V 10 kW

V00

-10 V
Vi 0 RL = 10 kW

(A) 60 mV dc (B) 110 mV dc (C) 130 mV dc (D) 150 mV dc

Q.204 The CMRR of the differential amplifier of the figure shown below is equal to
[GATE EC 1990, IISc-Bangalore]
90 kW

1 kW
V1
1 kW V0
V2

100 kW

(A)  (B) 0 (C) 1000 (D) 1800

Q.205 If a differential amplifier has a gain of 20,000 and CMRR = 80 dB, its common mode gain is
[IES EC 1992]
(A) 2 (B) 1 (C) 1/2 (D) 0
Q.206 If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48 dB
and 2 dB respectively, then its common mode rejection ratio is [GATE EC 2003, IIT-Madras]
(A) 23 dB (B) 25 dB (C) 46 dB (D) 50 dB
Q.207 An Op-Amp has a differential gain of 103 and a CMRR of 100. The output voltage of the Op-Amp with
inputs of 120μV and 80μV will be [IES EE 2003]
(A) 26 mV (B) 41 mV (C) 100 mV (D) 200 mV
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 58 GATE ACADEMY®

Q.208 For a given Op-Amp, CMRR  105 and differential gain  105 . What is the common mode gain of the
Op-Amp? [IES EC 2005]
(A) 1010 (B) 2  105 (C) 105 (D) 1
Q.209 A differential amplifier shown below has a differential mode gain of 100 and a CMRR of 40dB. If
V1  0.55V and V2  0.45V , output V0 is [GATE IN 2008, IISc - Bangalore]
V1
V0
V2

(A) 10 V (B) 10.5 V (C) 11 V (D) 15 V

Q.210 Statement I : An ideal Op-Amp when used to make an inverting amplifier, has both input terminal at
the same potential. [IES EC 2013]
Statement II : CMRR of the Op-Amp is low.
Codes :
(A) Both statement (I) and statement (II) are individually true and statement (II) is the correct
explanation of statement (I).
(B) Both statement (I) and statement (II) are individually true but statement (II) is NOT the correct
explanation of statement (I).
(C) Statement (I) is true but statement (II) is false.
(D) Statement (I) is false but statement (II) is true.
Q.211 An ideal OP-AMP is used to realize a difference amplifier circuit given below having a gain of 10. If
x  0.025, the CMRR of the circuit in dB is ________ [GATE IN 2016, IISc Bangalore]
100(1 + x) kW

10(1 - x)kW
V1
10(1 + x) kW V0
V2

100(1 - x) k W

Q.212 The output of an Op-Amp whose input is a 2.5 MHz square wave is shown in below figure. The slew
rate of the Op-Amp is [GATE IN 2003, IIT-Madras]
V0

-4V
0.4 ms

(A) 0.8 V/ μs (B) 8.0 V/ μs (C) 20.0 V/ μs (D) 40.0 V/ μs

Q.213 The operational amplifier shown in the circuit below has a slew rate of 0.8 Volts/ s . The input signal is
0.25 sin(t ) . The maximum frequency of input in kHz for which there is no distortion in the output is
[GATE IN 2013, IIT-Bombay]

22 kΩ
-

0.25sin wt +
V0

(A) 23.84 (B) 25.0 (C) 50.0 (D) 46.60

Q.214 An amplifier using an Op-Amp with a slew-rate SR  1 V/ sec has a gain of 40 dB. If this amplifier has
to faithfully amplify sinusoidal signals from 10 to 20 kHz, without introducing any slew-rate induced
distortion, then the input signal level must not exceed. [IES EC 2014]
(A) 795 mV (B) 395 mV (C) 79.5 mV (D) 39.5 mV
Q.215 The Slew rate is the rate of change of output voltage of an operational amplifier when a particular input
is applied. What is that input? [IES EC 2016]
(A) Sine wave input (B) Ramp input (C) Pulse input (D) Step input
Q.216 An operational amplifier has a slew rate of 2 V/sec. If the peak output is 12 V, what will be the power
bandwidth? [IES EE 2016]
(A) 36.5 kHz (B) 26.5 kHz (C) 22.5 kHz (D) 12.5 kHz
Q.217 An Op-Amp having a slew rate of 62.8 V/ μs ec , is connected in a voltage follower configuration. If the
maximum amplitude of the input sinusoidal is 10 V, then the minimum frequency at which the slew rate
limited distortion would set in at the output is [GATE EE 2001, IIT-Kanpur]
(A) 1.0 MHz (B) 6.28 MHz (C) 10.0 MHz (D) 62.8 MHz
Q.218 An operational amplifier is connected in voltage follower configuration. Input given to this circuit is
3sin103t . The slew rate of operational amplifier is [IES EE 2013]
(A) 6π×103 V/μ sec (B) 3π×103 V/μ sec
(C) 15π×103 V/μ sec (D) π×103 V/μ sec
Q.219 An Op-Amp has slew rate of 5 V/ sec . The largest sine wave output voltage possible at a frequency of
1 MHz is [IES EE 2013]
5 5
(A) 10π V (B) 5 V V (D) V(C)
π 2π
Q.220 An Op-Amp with a slew rate of 1 V/μ sec has been used to build an amplifier of gain +10. If the input
to the amplifier is a sinusoidal voltage with peak amplitude of 1 V , the maximum allowable frequency
of the input signal for undistorted output is [GATE IN 2000, IIT-Kharagpur]
(A) 830 Hz (B) 15.92 kHz (C) 31.84 kHz (D) 1.0 MHz
Q.221 The slew rate of an Op-Amp is 0.5 V/micro sec. The maximum frequency of a sinusoidal input of 2V
rms that can be handled without excessive distortion is [IES EE 2001]
(A) 3 kHz (B) 30 kHz (C) 200 kHz (D) 2 MHz
Q.222 An opamp that is powered from a ± 5V supply is used to build a non-inverting amplifier having a gain of
15. The slew rate of the opamp is 0.5  10 6 V/s. For a sinusoidal input with amplitude of 0.3 V, the
maximum frequency (in kHz) up to which it can be operated without any distortion is (up to 1 decimal
place) ______. [GATE IN 2018, IIT-Guwahati]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 60 GATE ACADEMY®
Q.223 The transient response rise time (unity gain) of an Op-Amp is 0.05 s. The small signal bandwidth is
[IES EC 2016]
(A) 7 kHz (B) 20 kHz
(C) 7 MHz (D) 20 MHz
Q.224 Consider the following statement. Dominant-pole frequency compensation in an Op-Amp.
1. Increases the slew-rate of the Op-Amp
2. Increases the stability of the Op-Amp
3. Reduces the bandwidth of the Op-Amp
4. Reduces the CMRR of the Op-Amp
Which of the statements given above are correct? [IES EC 2008]
(A) 1 and 3 only (B) 1, 2 and 4
(C) 1 and 2 only (D) 2 and 3 only
Q.225 Consider the following circuit [IES EC 2004]
V0
RF
D1
R
Vi
D2

What is the function of diode D2 in the above circuit?

(A) To avoid saturation of the Op-Amp
(B) To provide negative feedback when the input is positive
(C) To reduce reverse breakdown voltage of D1
(D) As a buffer
Q.226 The output voltage V0 in the circuit in below figure is [GATE IN 2004, IIT-Delhi]
+V

R2
R1 R1

_ _
V0
+ R (1 + d ) R +

R2 R2 R2 R2
(A) V (B) V (C) V (D) V
R R1 R1 R 1   
Q.227 An integrator circuit is shown in below figure. The Op-Amp is of type 741 and has an input offset
current ios of 1 μA . C is 1μF and R is 1 M  . If the input Vi is a 1 kHz square wave of 1 V peak to
peak, the output V0 , under steady state condition, will be [GATE IN 2003, IIT-Madras]

C
R
Vi
iOS V0

(A) a square wave of 1 V peak to peak (B) a triangular wave of 1 V peak to peak
(C) positive supply voltage + Vcc (D) negative supply voltage – Vcc
Q.228 If the value of the resistance R in the following figure is increased by 50 %, then voltage gain of the
amplifier shown in the figure will change by [GATE IN 2006, IIT-Kharagpur]
10 kW

1 kW
Vi -
V0
+

(A) 50 % (B) 5 % (C) – 50 % (D) negligible amount

Q.229 For the below circuit what will be the output for the sinusoidal input shown at the input terminal?
[IES EE 2009]
+V
R
Vin

-V RL Vout
R

(A) Vout (B) Vout

t t

(C) Vout (D) Vout

t t

Q.230 Assuming ideal opamp, the RMS voltage (in mV) in the output V0 only due to the 230 V, 50 Hz
interference is (upto one decimal place) _________. [GATE IN 2018, IIT Guwahati]

230 V, 50 Hz

0.3 pF
1.3 pF 3 pF 50 kW

–
Vdc = 1V 10 kW
+ V0

Q.231 For a given sinusoidal input voltage, the voltage waveform at point P of the clamper circuit shown in
figure will be [GATE EE 2006, IIT-Kharagpur]

+12V
Vin C _
RL
t + P
+
_ Vin
~
-12V

V V
(A) (B) t

V V
(C) (D)
12 V 0.7 V
t

t
-0.7 V -12 V

Q.232 A relaxation oscillator is made using Op-Amp as shown in below figure. The supply voltages of the Op-
Amp are 12 V. The voltage waveform at point P will be [GATE EE 2006, IIT-Kharagpur]
R1

R2
C

+12 V
_

+
-12 V
D2
2 kΩ
P
10 kΩ
10 kΩ
D1

6 10
t t
-6
-10

Q.233 For the given sinusoidal input to the circuit as shown in the figure below, the voltage waveform at point
P of the clamper circuit is [IES EE 2010]

+ VCC
C

P RL

Vin
- VCC

(A) (B)

–0.7 V –VCC

Q.234 The differential amplifier, shown in the figure, has a differential gain of Ad  100 and common mode
gain of Ac  0.1. If V1  5.01 V and V2  5.00 V , then V0 in volt (up to one decimal place) is ______.

[GATE IN 2017, IIT Roorkee]

Differential
amplifier
V2
V0
V1


Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Operational Amplifier

Instrumentation Amplifier :
1. Instrumentation amplifiers are used for amplifying the musical instrument. An instrumentation
amplifier is a type of difference amplifier that has been outfitted with input buffers which eliminate
the need for input impedance matching and thus make the amplifier particularly for suitable for
using measurement and test equipment.
2. Instrumentation amplifier is used where great accuracy and stability of circuit both short and long
terms are required. Fig. (a) shows a three Op-Amp instrumentation amplifier.
3. The Op-Amps A1 and A2 are the non-inverting amplifiers forming the input or first stage of the
instrumentation amplifier. The Op-Amp A3 is the normal difference amplifier forming an output
stage of the amplifier.
4. This circuit provides high input resistance for accurate measurement of signals from transducers. In
this circuit, a non-inverting amplifier is added to each of the basic difference amplifier inputs.
R2

V1 + V01 R1
Non-inverting A1 -
Amplifier - Rf A3 V0
R1
+

RG
R2

Rf
Non-inverting -
Amplifier A2 Difference Amplifier
V2 V02
+

Fig.(a) Three op-amp instrumentation amplifier

Operation :
V1 +
1. Calculation for A1 : A1 V01
V01  I R f  V1 .…. (i) -
I Rf
V V
I 1 2 .…. (ii) V1
RG
I RG
 V V 
V01   1 2  R f  V1 .…. (iii)
 RG  V2
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Analog Electronics [Workbook] 65 GATE ACADEMY®

2. Calculation for A2 :
V1  IRG  V2 .…. (iv)
V V
I  2 02 .…. (v)
Rf
V1
 V V 
V1   2 02  RG  V2 .…. (vi) I RG
 R 
 f 
V2 RG V02 RG V2
V1    V2 I Rf
Rf Rf -
V02 RG VR A2 V02
 V2  V1  2 G V2 +
Rf Rf
Rf
V02  V2  V1   V2 .…. (vii)
RG
3. Calculation of A3 : R2
Rf
V01  V1  V2   V1 R1
RG V01 -
Rf A3 V0
V02  V2  V1   V2 R1
RG V02 +
R2
V0  V02  V01  R2
R1
R2  Rf Rf 
V0  V2  V1   V2  V1  V2   V1 
R1  RG RG 
R2  2 R f 
V0   V2  V1   V2  V1 
R1  RG 
 2Rf 
R2
V0  1   V  V1 
R1 RG  2
This is the overall gain of the circuit.
The gain of Op-Amp Instrumentation amplifier can be easily obtained by varying RG , because it is
dependent on value of RG .
Requirements of a good instrumentation Amplifier :
The instrumentation amplifiers are used to amplify the low level differential signals very precisely, in
presence of the large common mode noise and interference signals. Hence a good instrumentation
amplifier has to meet the following specifications :
1. Finite, accurate and stable gain : As very low level signals are required to be amplified by the
instrumentation amplifiers, high and finite gain is the basic requirement. It is usually in the range of
1 to 100. The gain has to be accurate and closed loop gain must be stable in nature.
2. Easier gain adjustment : Not only finite and stable gain is required but a variable gain over the
prescribed range is also required. The gain adjustment must be easier and precise. Generally such
gain adjustment is done continuously using a potentiometer or is done digitally with the help of
switches, which are JFET or MOSFET switches.
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GATE ACADEMY® 66 Operational Amplifier
3. High input impedance: To avoid the loading of input sources, input impedance of the
instrumentation amplifier must be very high (ideally infinite). The differential mode input
impedance Z id is the equivalent impedance between the two input terminals. The common mode
input impedance Zic is the equivalent impedance between each input terminal and ground.
4. Low output impedance: Extremely low output impedance (ideally zero) to avoid the loading on
the immediate stage.
5. High CMRR : The output of transducer, when transmitted with long transmission lines has presence
of large common mode noise voltages. The instrumentation amplifier must amplify only the
differential input, completely rejecting the common mode input component. Thus it must have
ideally infinite CMRR.
6. Low power consumption : The power consumption of an instrumentation amplifier should be as
low as possible.
7. Low thermal and time drifts : The parameters of the instrumentation amplifier should not drift
with temperature or time.
8. High slew rate : The slew rate of the instrumentation amplifier must be as high as possible to
provide maximum undistorted output voltage swing.
Advantages :

1. The gain variations easy and precise.

2. The CMRR value is completely independent of the setting of resistance. Hence with the precision
ratios for R2 /R1 , the gain can be changed degrading the performance of the amplifier.

3. The resistance R3 is separate from the accurately matched resistances R1 , R2 which are required for
symmetric arrangement.

Objective & Numerical Ans Type Questions :

Q.1 Under what condition will the instrumentation amplifier circuit given in the figure possess highest
CMRR? ( Rs1 and Rs2 are source resistances). [IES EC 1994]

R1
–
R3 V0
+

Rs1 Rs2
R4
Vs1 +
_ Vs2 +
_

R1 R3 Rs1  R1 Rs2  R3
(A)  (B) 
R2 R4 R2 R4
Rs1  R2 Rs2  R4 Rs1 Rs2
(C)  (D) 
R1 R3 R2 R4

Q.2 V1 and V2 are the input voltages of an instrumentation amplifier. The output of the instrumentation
amplifier is found to be 100 V1  V2   104 V1  V2  . The gain and the common mode rejection ratio
(CMRR) of the instrumentation amplifier respectively are [GATE IN 2004, IIT-Delhi]
(A) (50, 60 dB) (B) (50, 120 dB) (C) (100, 60 dB) (D) (100, 120 dB)
Q.3 In the instrumentation amplifier shown in the figure if the switch SW is changed from position A to B,
the values of the amplifier gain G before and after changing the switch respectively are
[GATE IN 2005, IIT-Bombay]
+
_
50 kW 500 kW
SW
V1
100 kW _
A B

22.2 kW 10.53 kW + G. (V2 - V1 )

V2
100 kW 50 kW
_

+
500 kW

(A) 45, 95 (B) 50, 100 (C) 100, 200 (D) 90, 180
Q.4 A dual op amp instrumentation amplifier is shown below. The expression for the output amplifier is
given by [GATE IN 2006, IIT-Kharagpur]
V1 +
V0
-
R2
R1
R1
-
R2
+ V2

 R   2R 
(A) V0   1  2  (V2  V1 ) (B) V0  1  2  (V2  V1 )
 R1   R1 

2 R2  2R 
(C) V0  (V2  V1 ) (D) V0  1  1  (V2  V1 )
R1  R2 
Q.5 Of the four characteristics given below, which are the major requirements for an instrumentation
amplifier? [GATE EE 2015 (Set-01), IIT-Kanpur]
P. High common mode rejection ratio
Q. High input impedance
R. High linearity
S. High output impedance
(A) P, Q and R only (B) P and R only
(C) P, Q and S only (D) Q, R and S only
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GATE ACADEMY® 68 Operational Amplifier

Answer Keys :

1 B 2 D 3 C 4 A 5 A

Solutions :

Sol.1 (B)
Sol.2 (D)
Given :
(i) Output of amplifier,
V0  100 (V1  V2 )  10 4 (V1  V2 )
V V 
V0  100 (V1  V2 )  2  104  1 2  …(i)
 2 
Since, output of differential amplifier is given by,
V0  Ad Vd  Acm Vcm
 V V 
V0  Ad (V1  V2 )  Acm  1 2  …(ii)
 2 
On comparing equations (i) and (ii),
Ad  100 and Acm  2  10 4
Therefore differential gain of the Op-Amp is,
Ad  100
CMRR of differential amplifier is given by,
A 100
CMRR  d   5  105
Acm 2  104
CMRR (in dB)  20 log10 (5  105 )
CMRR (in dB)  114 dB
Hence, the correct option is (D).
Sol.3 (C)
V0 can be obtained by using superposition theorem and taking switch connected to resistance R.
For switch at postion A, R  22.2 k
For switch at postion B, R  10.53 k
(i) Consider only V1 :
V1 +
(I)
_
R1 R2 500 kW
SW
100 kW V01 50 kW _ R3
(III)
R R1 + V03 '

100 kW 50 kW
_
(II) R2
+ V02
R3 500 kW

100 kW 50 kW
_
(II) R2
+ V02
V2
R3 500 kW

 R1  R 
V01  V2 and V02  1  1  V2 … (ii)
R  R
R3
V03"  (V02  V01 )
R2
R3  R1 R1 
V03"  1    V2
R2  R R
R3  2 R1 
V03"  1   V2
R2  R 
Total output voltage is
V0  V03 '  V03"
 R3  2 R1  R3  2 R1 
V0  1   V1  1   V2
R2  R  R2  R 
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GATE ACADEMY® 70 Operational Amplifier
From equation (ii),
R3  2 R1 
V0  1   (V2  V1 )
R2  R 
Comparing with given output,
V0  G (V2  V1 )
R3  2 R1 
Gain AV  G  1  
R2  R 
Output of instrumentation amplifier.
Case (A) : If switch S is connected to point A,
R3  500 k, R2  50 k,
R1  100 k, R  22.2 k
V0 500  2 100 
AV   1  
V2  V1 50  22.2 
AV  100.09  100 V
Case (B) : If switch S is connecte d to point B,
R3  500 k, R2  50 k,
R1  100 k, R  10.53 k
V0 500  2 100 
AV   1  
V2  V1 50  10.53 
AV  199.9  200 V
Hence, the correct option is (C).
Sol.4 (A)
Given circuit is shown below,
V1 +
V0
-
VB R2
R1
VA VC
R1
-
R2
+ V2

From virtual ground concept,

V1  VA and V2  VC
Applying KCL at node A,
V1 V1  VB
 0
R2 R1
 R  R2  VB
V1  1 
 R1 R2  R1

 R  R2 
VB  V1  1 
 R2 
Applying KCL at node C,
V2  VB V2  V0
 0
R1 R2
 R  R2  V0 VB
V2  1  
 R1 R2  R2 R1
V2 ( R1  R2 ) R1
 V0  VB … (ii)
R2 R2
From equation (i) and (ii),
V2 ( R1  R2 ) R1  R  R2 
 V0   1  V1
R2 R2  R2 
V2 ( R1  R2 )  V1 ( R1  R2 )  R1V0

 R   R 
V0  1  2  V2  1  2  V1
 R1   R1 
 R 
V0  1  2  (V2  V1 )
 R1 
Hence, the correct option is (A).
Sol.5 (A)
An instrumentation amplifier is a type of differential amplifier that has been outfitted with input buffer
amplifier, which eliminate the need for input impedance matching.
Circuit of instrumentation amplifier is shown below,
V1 R2 R3

Rgain Vout

V2 R2 R3

Fig. Instrumentation amplifier

Major requirements of an instrumentation amplifier is given below,
(i) High common mode rejection ratio
(ii) High input impedance
(iii)High linearity
(iv) Low output impedance
(v) Very low DC offset
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GATE ACADEMY® 72 Operational Amplifier
(vi) Low drift
(vii) Low noise
(viii) Very high open loop gain
Hence, the correct option is (A).


Sample and Hold Circuit :

Introduction :
Sample and hold circuits are widely used as analog to digital converter. A analog signal is time
varying and it is required to hold the input signal constant during conversion.
The sample and hold circuit, which serves this purpose, basically samples the input signal and
holds on the last sampled value.
1. The Schematic diagram of basic sample and hold circuit :
Switch ‘S’ V0
+ + Input, Vi

Vi Chold V0 Sample
Hold
- - t
Fig. (a)
The Switch ‘S’ is connected in series with the input, and the hold capacitor ‘ Chold ’ is connected across
the output as shown in figure (a).
 When switch ‘S’ closed,
V0  Vin [This mode of operation is called Sample Mode]
 When switch ‘S’ open,
V0  Voltage across hold capacitor [This mode of operation is called Hold Mode]
In this case, the voltage across the capacitor is equal to the input voltage at the time of opening the
switch and is held constant till the switch ‘S’ is closed again.
Simply we analyze by transfer function for below circuit,
Ri S
+

+
Vi Chold V0
-

-
1
V0 ( s ) Chold ( s )
 
Vi ( s ) R  1
i
Chold ( s )
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Analog Electronics [Workbook] 74 GATE ACADEMY®

V0 ( s)  Vi ( s) [Due to source resistance Ri ]

Disadvantages of Sample and hold circuit ( V0 ( s)  Vi ( s) )
1
V0 ( s)  Vi ( s) When Ri 
Cs
2. Sample and hold circuit using Op-Amp (Switching device as MOSFET) :
Buffer Circuit
Buffer Circuit (Voltage follower)
(Voltage follower)

D Q1 S V' A2 V0
A1
Vi

G
Chold fclk ® (Voltage pulse train)
fclk
(control gate)

fclk

V0 = Vi Hold V0 = Vi Hold V0 = Vi Hold V0 = Vi Hold V0 = Vi

V ' = V0
(Voltage follower)

ts tH
ts ® Sample period,
Sample state Hold state
(follows same t H ® Hold period
(follows previous
as input) amplitude)

Fig. (b)
If clk  ‘1’  V ' follows Vi .
If clk  ‘0’  V ' remains constant having a value equal to Vi at the instance clk went low.
 The Sample and hold circuit uses two Op-Amp ( A1 and A2 ) and one MOSFET ( Q1 ).
 The MOSFET work as a switch and is controlled by the controlled gate and the capacitor stores the
charge.
 Both the Op-Amp ideal and used as Buffer (Voltage follower)
In ideal Op-Amp
Input Resistance, ( Ri )   , Output Resistance, ( R0 )  0 , Open loop gain, ( AOL )  

 The output of first Op-Amp is applied to the drain of MOSFET Q1 .

 In sample mode clk is positive, Q1 turns ON and capacitor charges instantaneously to Vi and
the output voltage of Op-Amp A2 follows the input as shown in figure (b).
 In hold mode clk is zero, Q1 turns OFF. The capacitor is disconnected from the input and
cannot discharge as it faces the high input impedance of the voltage follower A2 . So, it holds the
charge as it is.
Points about Switch :
Switch may be
(i) Relay (for very slow waveforms).
(ii) A sampling diode-bridge gate.
(iii) A bipolar transistor switch.
VCC VCC

RL RL
V0 V0 Transistor is in cut-off Region
Rin
Vin (VB < 0.7 V, I C = 0)
VB (Switch open)

0V 0V

 The input and base are grounded (0 V).

 Base-Emitter voltage VBE  0.7 V .
 Base-Emitter Junction reverse biased and Base-Collector Junction reverse biased.
 Transistor is “Fully-OFF” (cut-off region), so I C  0 .
 Vout  VCE  VCC  ‘1’
 Transistor operates as an open switch.
VCC VCC

RL RL
V0 V0 Transistor is in
Rin saturation region
Vin
VB (Switch closed) (VB > 0.7 V, I C = max)

0V 0V

 The input and base are connected to VCC .

 Base-Emitter voltage VBE  0.7 V .
 Base-Emitter Junction forward biased and Base-Collector Junction forward biased.
 Transistor is “Fully-ON” (saturation region), so I C  maximum .
 Vout  VCE  ‘0’
 Transistor operates as an closed switch.
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Analog Electronics [Workbook] 76 GATE ACADEMY®
(iv) A MOSFET controlled by gating signal. [see figure (b)]
The MOSFET makes an excellent chopper because of its offset voltage. When ON ( ~ 5 V its
offset voltage) which is much smaller than that of a bipolar junction transistor.
The hold capacitor has dielectric of either Polycarbonate, Polyethylene or Teflon.
Factors Influence the operation of circuit.
 Aperture time ( tap ) : It is the delay between the time at which the pulse is applied to the switch
and the actual time the switch is closed.
Ideally as soon as the hold command is given to sample and hold circuit, the circuit should stop
following any changes taking place in the input and hold the latest sampled value. But
practically, the sample and hold circuit will follow the changes in input voltages for short period
of time, even after receiving the hold command. This period is called as aperture time.
It is due to propagation delays of the driver and the switch.
Sample

Hold Hold

tap

droop tac
 Acquisition time : It is the time required by the hold capacitor to charge to the input signal (with
specified error band around the final value)
Vin

t
Vout

4V 3.9 V
4 - 3.9 = 0.1 Volt (around the final value)

fclk

1V Impulse train

t
Ts 2Ts 3Ts 4Ts 5Ts 6Ts 7Ts

Acquisition time (ms)

As Chold tcharging Acquisition
RChold time (ms)

Hold capacitance, Chold (pF)

 Droop rate : It is the change in the output voltage per unit time while the sample and hold
circuit is in the hold mode.
Ideally we say hold capacitor voltage will not decrease means doesn’t discharge ideally but
practically as time increases, Chold discharges.
How much it is going to be discharge w.r.t. time is called droop rate.
Droop rate mainly originates because of leakage from the hold capacitor and this leakage mainly
contribute for the switch leakage current as well as bias currents.
Droop rate given by the equation :
dV0 I (pA)  Leakage Current
 L
dT CHold (pF) 
 Hold Capacitor Value

As, Chold  
 Droop rate 

3. Monolithic Sample and Hold (S/H) Circuit :

Introduction :
Monolithic sample and hold circuit can obtain ultra high DC accuracy with fast acquisition of signal
and low droop rate. Operating as a unity gain follower.
A bipolar input stage is used to achieve low offset voltage and wide bandwidth.
Rf

D1 D2
Switch ‘S’
A2 V0 (Output)
A1
(Input) Vi

Chold
Logic input
S/H Logic ref.
Switch
driver

 When S/H pulse is received during the sampling interval the switch is closed. The capacitor starts
charging and hence V0 follows Vi .
 At the end of sampling interval the driver opens the switch.
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Analog Electronics [Workbook] 78 GATE ACADEMY®

 The purpose of D1 and D2 is to prevent A1 from saturating when in the hold mode.
 The purpose of the A1 is to provide high input impedance and A2 prevent discharge of Chold from
the load.
 The requirement of Chold are low leakage and low dielectric absorption.
Applications and features monolithic sample and hold circuit :
 Features :
 Low input offset
 Wide bandwidth
 High supply rejection ratio in sample and hold.
 Low output noise in hold mode.
 Applications :
 Ramp generators with variables reset level.
 Integrator with programmable reset level.
 Synchronous correlators.
 Staircase generators.

Objective & Numerical Ans Type Questions :

Q.1 For the sample and hold circuit shown in figure both the Op-Amps have bias current of 1 nA. The
maximum leakage current through the switch is 0.5 nA. The worst case droop rate during the hold
operation is __________mV/msec. [GATE IN 1995, IIT-Kanpur]
10 kW

S
Vi
CH = 100 nF

Q.2 The most commonly used amplifier in sample and hold circuits is [GATE EC 2000, IIT-Kharagpur]
(A) a unity gain inverting amplifier (B) a unity gain non-inverting amplifier
(C) an inverting amplifier with a gain of 10 (D) an inverting amplifier with a gain of 100
Q.3 A sample and hold circuit have two buffers one at input and other at the output. The primary
requirements for the buffers are [GATE IN 2001, IIT-Kanpur]
(A) The input buffers should have high slew rate and output buffer should have low bias current
(B) The input buffer should have low bias current and output buffer should have high slew rate
(C) Both the buffers should have low bias currents
(D) Both the buffers should have high slew rate
. Common Data Question for Questions 4 and 5 .
The figure shows a sample-and-hold circuit using a MOSFET as a switch. The threshold voltage of the
MOSFET is +2 V. It has zero leakage current in the off state. Assume that the capacitor is ideal.
[GATE IN 2009, IIT-Roorkee]
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GATE ACADEMY® 79 Operational Amplifier

Vg +12 V

V0
Vi -12 V
C = 1 nF
Vsub

Q.4 The input voltage Vi ranges from –5 V to +5 V. Appropriate values of Vsub , of Vg during sampling, and
of Vg during hold are, respectively,
(A) +12 V, Vg  7 V and  3 V (B) 12 V, Vg  3 V, and  7 V
(C) 12 V, Vg  3 V, and  7 V (D) 12 V, Vg  7 V, and  3 V
Q.5 The circuit is used at a sampling rate of 1 kHz, with an A/D converter having a conversion time of
200 s . The op amp has an input bias current of 10 nA. The maximum hold error is
(A) 1 mV (B) 2 mV (C) 5 mV (D) 10 mV
Q.6 For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then
[GATE EC 2014 (Set - 04), IIT-Kharagpur]
(A) Droop rate decreases and acquisition time decreases
(B) Droop rate decreases and acquisition time increases
(C) Droop rate increases and acquisition time decreases
(D) Droop rate increases and acquisition time increases

Answer Keys :

1 5  10  3 2 B 3 C 4 D 5 B
6 B

Solutions :

Sol.1 (5  10  3 )
Given :
(i) Bias current of Op-Amp  1 nA
(ii) Leakage current through the switch  0.5 nA
Total current  1  0.5  1.5 nA
Buffer circuit
(Voltage follower)

1.5nA V0

Chold = 100 nF Non-inverting Op-Amp

MOSFET V0
Vi

Chold Non-inverting Op-Amp

Control
gate
Buffer is used in sample and hold circuit. Generally a buffer is a unity gain non-inverting amplifier, (i.e.
Voltage follower circuit).
Hence, the correct option is (B).
Sol.3 (C)
Sample and hold circuit with two buffers is shown in figure below,
Buﬀer circuit
Buﬀer circuit (Voltage follower)
(Voltage follower)

MOSFET V0

Vi
Chold
Control
gate

The DC error output voltage is minimized, if the bias current of buffers used are minimum. Hence, the
prime requirements for the buffers are that both the buffers should have law bias currents.
So, the correct option is (C).
 Key Point
Important characteristics of sample and hold circuit :
Acquisition time : It is the time required by the hold capacitor to charge upto input signal.
Acquisition time is mainly a function of capacitor charging current, time constant of the circuit and the
slew rate of buffer circuit.

Acquisition time (ms)

Hold capacitance, Chold (pF)

As Chold tcharging Acquisition

time (ms)

Droop rate : It is the change in the output voltage per unit time while the sample and hold circuit is in
the hold mode.
How much it is going to be discharged with respect to time, is called droop rate.
Droop rate mainly originates because of leakage from the hold capacitor and this leakage mainly
contribute for the switch leakage current as well as bias currents.
Droop rate is given by,
dV0
Droop rate 
dt
Leakage current I (pA)
Droop rate   L
Hold capacitance Chold (pF)
1
Hence, droop rate 
Chold
Therefore, as hold capacitance C hold will increase, droop rate will decrease.
Sol.4 (D)
The given MOSFET is N type therefore for MOSFET should be ON when Vg  VT and Vsub is 12 .
Therefore, Vgs  2 V
Vg  Vs  2 V
Vg  Vi  2 V
If Vi  5 V, Vg  5  2
Vg  7 V
If Vi   5 V, Vg  5  2
Vg   3
Hence, during sampling (i.e. when MOSFET is ON, Vg  7 V , Vsub  12 V )
During holding MOSFET must be OFF. Therefore gate source voltage is less than threshold voltage.
Vgs  2 V [cut-off]
Vg  Vi  2 V

MOSFET V0
Vi
Chold
Control
gate
Acquisition time : It is the time required by the hold capacitor to charge upto input signal.
Acquisition time is mainly a function of capacitor charging current, time constant of the circuit and the
slew rate of buffer circuit.
Acquisition time (ms)

Hold capacitance, Chold (pF)

As Chold tcharging Acquisition

time (ms)

Droop rate : It is the change in the output voltage per unit time while the sample and hold circuit is in
the hold mode.
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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GATE ACADEMY® 83 Operational Amplifier
How much it is going to be discharged with respect to time, is called droop rate.
Droop rate mainly originates because of leakage from the hold capacitor and this leakage mainly
contribute for the switch leakage current as well as bias currents.
Droop rate is given by,
dV0
Droop rate 
dt
Leakage current I (pA)
Droop rate   L
Hold capacitance Chold (pF)
1
Hence, droop rate 
Chold
Therefore, as hold capacitance Chold will increase, droop rate will decrease.
Hence, the correct option is (B).



Objective & Numerical Ans Type Questions :

Q.1 The circuit using a BJT with   50 and VBE  0.7 V is shown in the figure. The base current I B and
collector voltage VC are respectively [GATE EC 2005, IIT-Bombay]

(A) 43 μA and 11.4 V (B) 40 μA and 16 V

(C) 45 μA and 11 V (D) 50 μA and 10 V

Q.2 The biasing circuit of a silicon transistor is shown below. If   80, then what is VCE for the transistor?

[GATE IN 2006, IIT-Kharagpur]

VCC = +12 V

RC = 2 kW
RB = 100 kW

VCE

(A) – 6.08 V (B) 0.2 V

(C) 1.2 V (D) 6.08 V
Q.3 In the given circuit, the silicon transistor has β = 75 and a collector voltage VC  9 V . Then the ratio of
RB and RC is [GATE EE 2015 (Set - 01), IIT-Kharagpur]

RC
RB
VC

Q.4 In the following circuit, the transistor is in active mode and VC  2 V. To get VC  4 V, we replace RC
with RC' . Then the ratio RC' / RC is ________. [GATE EE 2015 (Set - 01), IIT-Kharagpur]
+ 10 V

RC
RB VC

Q.5 In the circuit shown in the figure, it is found that VBE  0.7 and VE  0 V . If dc  99 for the transistor,
then the value of RB in kilo ohms is ________. [GATE IN 2015, IIT-Kanpur]
10 V

VE = 0 V
1kW
-10 V

Q.6 Assume that the  of the transistor is extremely large and VBE  0.7 V, IC and VCE in the circuit shown
in figure are [GATE EC 2004, IIT-Delhi]
5V

4 kW IC 2.2 kW

+
VCE
–
1kW 300 W

(A) I C  1mA, VCE  4.7 V (B) I C  0.5 mA, VCE  3.75 V

(C) I C  1mA, VCE  2.5 V (D) I C  0.5 mA, VCE  3.9 V
Q.7 In the circuit shown below, the silicon npn transistor Q has a very high value of  . The required value
of R2 in k to produce IC  1 mA is [GATE EC/EE 2013, IIT-Bombay]
VCC = 3V

IC
R1 60 kW

R2
RE 500 W

(A) 20 (B) 30 (C) 40 (D) 50

Q.8 For the given circuit  is very high and it is given that VBE  0.7 V . Calculate value of VCE .
[GATE EE 2011, IIT-Madras]
+ 12 V

8 kW 1kW

2 kW
200 W

(A) 2 V (B) 1.8 V (C) 2.5 V (D) 2.8 V

Q.9 In the amplifier circuit shown in figure, the values of R1 and R2 are such that the transistor is operating
at VCE  3V and I C  1.5 mA when its  is 150. For a transistor with  of 200, the operating point
(VCE , IC ) is [GATE EC 2003, IIT-Madras]

VCC = 6 V
R2
R1
V0
Vi

(A) (2 V, 2 mA) (B) (3 V, 2 mA) (C) (4 V, 2 mA) (D) (4 V, 1 mA)

Q.10 In the circuit shown below, assume that the transistor has hfe  99 and VBE  0.7 V . The value of
collector current I C of the transistor is approximately. [GATE EE 2003, IIT-Madras]

IC 3.3kW

12 V
33 kW

4V 3.3kΩ

(A) [3.3/3.3] mA (B) [3.3/(3.3 + 0.33)] mA

(C) [3.3/33] mA (D) [3.3/(33 + 3.3)] mA
Q.11 If the transistor in figure has high value of  and VBE of 0.65 the current I flowing through the 2 k
resistance will be __________mA. [GATE EC 1992, IIT-Delhi]
I
6.5 kW 2 kW

1.85 kW 10 V

1.65 kW
1 kW

Q.12 In the circuit shown below, the value of the base current I B will be [GATE EE 2000, IIT-Kharagpur]
5V

5 kW

IB β = 50
+
0.7 V _
1 kW
_ 10 V

(A) 0.0 A (B) 182 A

(C) 26.7 A (D) 40.0 A
Q.13 In the circuit of the figure, assume that the transistor is in active region. It has a large β and its base-
emitter voltage is 0.7 V. The value of I C is [GATE EC 2000, IIT-Kharagpur]
15 V

10 kΩ RC
IC

5 kΩ 430 W

(A) Indeterminate since RC is not given (B) 1 mA

(C) 5 mA (D) 10 mA
Q.14 A transistor having   0.99 and VBE  0.7 V , is used in the circuit of the figure, is the value of the
collector current will be [GATE EC 1997, IIT-Madras]
+12 V
1 kW

1 kW
10 kW

1 kW

(A) 5.32 mA (B) 6.0 mA (C) 6.5 mA (D) 7.0 mA

Q.15 A transistor amplifier circuit is shown in figure. The quiescent collector current, rounded off to first
decimal, is [GATE IN 2003, IIT-Madras]
VCC = 24 V

4.7 kW

560 kW C
V0

C
Vi b = 100, VBE = 0.7 V
C = 0.1mF

(A) 2.6 mA (B) 2.3 mA (C) 2.1 mA (D) 2.0 mA

Q.16 The common emitter amplifier shown in the figure is biased using a 1 mA ideal current source. The
approximate base current value is [GATE EE 2005, IIT-Bombay]
VCC = 5 V

RC = 1 kW

b = 100

Vin 1 mA

(A) 0 A (B) 10 A (C) 100 A (D) 1000 A

Q.17 In the circuit shown, the BJT has a current gain (β) of 50. For an emitter base voltage VEB  600 mV, the
emitter collector voltage VEC (in volts) is_________. [GATE EC 2015 (Set - 02), IIT-Kanpur]

60 kW
500 W

Q.18 In the transistor circuit as shown below, the value of resistance RE in k is approximately,

[GATE EC 2013, IIT-Bombay]

+10 V

I C = 2.0 mA
1.5 kW
15 kW
0.1μF
Vi VCE = 5.0 V
0.1μF V0

6 kW RE

(A) 1.0
(B) 1.5
(C) 2.0
(D) 2.5
Q.19 In the circuit shown, the PNP transistor has VBE  0.7 V and   50 . Assume that RB  100kΩ . For V0
to be 5 V, the value of RC (in kΩ ) is ____________. [GATE EC 2014, IIT-Kharagpur]

RB
VEE = 10 V

Q.20 Consider the circuit shown in the figure. Assuming VBE1  VEB2  0.7 V, the value of the dc voltage VC2
(in volt) is __________. [GATE EC 2016 (Set - 03), IISc Bangalore]

b1 = 100

Q1 Q2

b2 = 50
10 kW
VC 2
1V
1 kW

Q.21 Consider the circuit shown in the figure. Assume base-to-emitter voltage VBE  0.8V and common base
current gain ( ) of the transistor is unity. [GATE EC 2017 (Set - 02), IIT Roorkee]
+18V

44 kW 4 kW

2 kW
16 kW

The value of the collector-to-emitter voltage VCE (in volts) is ________.

Q.22 For the transistor in given figure, β  50 . The value of voltage VEC is
+9 V

1 mA

50 kW
4.7 kW

-9 V

(A) 3.13 V
(B) 4.24 V
(C) 5.18 V
(D) 6.07 V
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 8 GATE ACADEMY®
Q.23 In the circuit shown in below figure. If   50 , the power dissipated in the transistor is _______mV.
+9 V

0.5 mA

50 kW
4.7 kW

-9 V
Q.24 For the circuit shown in figure the transistor   0.992 . The value of voltage VBC is ________Volt.
+ 9V

4 kW

2.2 kW

- 9V
Q.25 The circuit shown in below figure is biased with a constant-current source I Q . For the transistor,
  120 , and the E–B turn-on voltage is VEB (on) = 0.7 V. Determine I Q such that VECQ  3 V .
V + = 5V

VB VECQ
Q1
RB = 20 kW
I CQ RC = 4 kW

V - = -5V
(A) 0.31 mA (B) 0.51 mA (C) 0.71 mA (D) 0.91 mA
Q.26 The base of the transistor in the circuit shown in below figure driven by a constant-current source.
Assume   100 . The value of V 0 for I  100 μA .
+5 V

RC = 1kW

V0
I

(A) 1.505 V (B) 2.505 V (C) 3.505 V (D) 4.505 V

Q.27 The common-emitter current gain of the transistor is   75. The voltage VBE in ON state 0.7V. The
value of IC and RC
+5V

RC
VC = 2V
50kW

I Q = 1mA

-5V

(A) 0.987 mA, 3.04 k (B) 1.013mA, 2.96 k

(C) 0.946 mA, 4.18k (D) 1.057 mA, 3.96 k
Q.28 The common-emitter current gain of the transistor is   75. The voltage VEC in ON state is 0.7V. The
value of VEC is ______________Volt.
+8V

10 kW

10 kW
-2V

3kW

-8V

Q.29 In the circuit shown below, the voltage VC  4 V . The value of  and  are respectively
+5 V

100 kW 2 kW
VC

8 kW
_5 V

(A) 0.943, 17.54 (B) 0.914, 17.54 (C) 0.914, 11.63 (D) 0.914, 10.63
Q.30 In the circuit shown below, Zener voltage V z = 5 V,   100. The value of I CQ and VCEQ are
12 V
500 W

10 kW
15 V 1 kW RTH

10.7 V

Q.32 In the below circuit as shown   99 , VBE  0.6 V , then what are the values of VC and I C corresponding
to the operating point ? [IES EE 2009]
VCC = +10 V

2.7 kW
200 kW

(A) 4.6 V and 1.98 mA (B) 4.7 V and 2.00 mA

(C) 5.4 V and 1.56 mA (D) 4.2 V and 2.1 mA
Q.33 The Si transistor as shown in the circuit below has   50 and negligible leakage current. If
VCC  18 V, VEE  4 V, RE  200  , RC  4 k, RB  72 k , what is the value of the quiescent collector
current I CQ ? [IES EE 2009]

VCC

RB
RE
-VEE

(A) 1.1 mA (B) 2 mA (C) 5 mA (D) 3.6 mA

Q.34 A transistor having α = 0.99 and VBE  0.7 volts, in the circuit shown, then the value of the collector
current will be_____________. [GATE EC 1995, 5 Marks]

1 kW
10 kW

1 kW

Q.35
+ 10 V
5 kW
VE = 1.7 V

VB = 1V

100 kW
5 kW
-10 V

A circuit using the BJT is shown in the above figure, the value of  is [IES EE 2001]
(A) 120 (B) 150 (C) 165 (D) 166
Q.36 In the circuit shown, [IES EC 2002]
+10 V
RC 2.5 kW

40 kW Si Transistor
b = 100
VBE = 0.7 volts
2.7 V

The transistor is biased at

(A) 0 mA (B) 5 mA (C) 3.9 mA (D) 
. Common Data Questions 37 & 38 .
A silicon transistor with VBE  0.7 V and an extremely large β is used in the circuit shown in figure.
+5V

2.2 kW
4 kW

VCE

1 kW
300 W

5 kW RC

-15 V

Q.40 In the circuit shown below, VBE  0.7 V . [GATE IN 2007, IIT-Kanpur]

The  of the transistor and VCE are, respectively

(A) 19 and 2.8 V (B) 19 and 4.7 V (C) 38 and 2.8 V (D) 38 and 4.7 V
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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GATE ACADEMY® 13 BJT Biasing

Q.41 The transistor circuit shown uses a silicon transistor with VBE  0.7 V, IC  I E and a dc current gain of
100. The value of V0 is [GATE EE 2010, IIT-Guwahati]
+10V

10 kW 50 kW

V0
100 W

(A) 4.65 V (B) 5 V (C) 6.3 V (D) 7.23 V



Objective & Numerical Ans Type Questions :

Q.1 A BJT is said to be operating in the saturation region if [GATE EC 1995, IIT-Kanpur]
(A) Both the junctions are reverse biased.
(B) Base-emitter junction is reverse biased and base-collector junction is forward biased.
(C) Base-emitter junction is forward biased and base-collector junction reverse-biased.
(D) Both the junctions are forward biased.
Q.2 If the transistor in the figure is in saturation, then [GATE EC 2002, IISc-Bangalore]
C
IC
IB
β dc denotes the
B dc current gain

E
(A) I C is always equal to  dc I B (B) I C is always equal to dc I B
(C) I C is greater than or equal to  dc I B (D) I C is less than or equal to  dc I B
Q.3 Assuming VCEsat  0.2 V and   50, the minimum base current ( I B ) required to drive the transistor in
figure to saturation is. [GATE EC 2004, IIT-Delhi]
3V
IC
1kW
IB

(A) 56 A (B) 140 mA (C) 60 A (D) 3 mA

Q.4 If for a silicon n-p-n transistor, the base-to-emitter voltage (VBE ) is 0.7 V and the collector-to-base
voltage (VCE ) is 0.2V, then the transistor is operating in the [GATE EC 2004, IIT-Delhi]
(A) normal active (B) saturation mode (C) inverse active mode (D) cut-off mode
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 2 GATE ACADEMY®
Q.5 A bipolar junction transistor (BJT) is used as a power control switch by biasing it in the cut-off region
(OFF state) or in the saturation region (ON state). In the ON state, for the BJT
[GATE EE 2004, IIT-Delhi]
(A) both the base-emitter and base-collector junctions are reverse biased.
(B) the base-emitter junction is reverse biased and the base-collector junction is forward biased.
(C) the base-emitter junction is forward biased, and the base-collector junction is reverse biased.
(D) both the base-emitter and base-collector junctions are forward biased.
Q.6 For the BJT circuit shown, assume that the  of the transistor is very large and VBE  0.7 V . The mode
of operation of the BJT is [GATE EC 2007, IIT-Kanpur]

(A) Cut-off (B) Saturation (C) Normal active (D) Reverse Active
Q.7 The transistor in the given circuit should always be in active region. Take VCE ( sat )  0.2 V ,
VBE  0.7 V . The maximum value of RC in  which can be used, is __________.
[GATE EE 2014 (Set - 02), IIT-kharagpur]

RS = 2 kW 5V
b = 100

Q.8 The common emitter forward current gain of the transistor shown is F  100
[GATE EE 2007, IIT-Kanpur]

The transistor is operating in

(A) Saturation region (B) Cut-off region
(C) Reverse active region (D) Forward active region
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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GATE ACADEMY® 3 Region of BJT
Q.9 The transistor used in the circuit shown below has a  of 30 and I CBO is negligible
[GATE EE 2011, IIT-Madras]

2.2 kW
15 kW
1 kW D VBE = 0.7 V
VCE (sat) = 0.2 V
Vz = 5V

–12 V
If the forward voltage drop of diode is 0.7 V, then the current through collector will be
(A) 168 mA (B) 108 mA (C) 20.54 mA (D) 5.36 mA
Q.10 In the circuit shown, the silicon BJT has   50. Assume VBE  0.7 V and VCE ( sat )  0.2 V . Which one of
the following statements is correct? [GATE EC 2014 (Set - 03), IIT-Kharagpur]
10 V

50 kW
5V
RB

(A) For RC  1kΩ, the BJT operates in the saturation region.

(B) For RC  3kΩ, the BJT operates in the saturation region.
(C) For RC  20 kΩ, the BJT operates in the cut-off region.
(D) For RC  20 kΩ, the BJT operates in the linear region.
Q.11 When a bipolar junction transistor is operating in the saturation mode, which one of the following
statements is TRUE about the state of its collector-base (CB) and the base-emitter (BE) junctions?
[GATE EE 2015 (Set - 02), IIT-Kharagpur]
(A) The CB junctions is forward biased and the BE junction is reverse biased.
(B) The CB junctions is reverse biased and the BE junction is forward biased.
(C) Both the CB and BE junctions are forward biased.
(D) Both the CB and BE junctions are reverse biased.
Q.12 For the BJT Q1 in the circuit shown below, β   , VBE ( on )  0.7 V , VCE ( sat )  0.7 V . The switch is initially
closed. At time t  0 , the switch is opened . The time t at which Q1 leaves the active region is
[GATE EC 2011, IIT-Madras]

(A) 10 ms (B) 25 ms (C) 50 ms (D) 100 ms

4.8 kW
Vin (t )
12 kW
2V
Vin (t )
T
t (in sec)
0V

For the input Vin (t ) as shown in the figure, the transistor switches between the cutoff and saturation
regions of operation, when T is large. Assume collector-to-emitter voltage at saturation VCE ( sat )  0.2 V
and base-to-emitter voltage VBE  0.7 V . The minimum value of the common-base current gain () of
the transistor for the switching should be __________. [GATE EC 2017 (Set - 01), IIT-Roorkee]
Q.14 Consider the circuit shown in figure. If the  of the transistor is 30 and ICBO is 20 nA and the input
voltage is + 5 V, then transistor would be operating in [GATE EE 2006, IIT-Kharagpur]
+12 V

2.2 kW

15kW
Vi Q
100 kW

-12 V

(A) Saturation region (B) Active region (C) Breakdown region (D) Cut-off region
Q.15 The transistor as shown in the circuit is operating in: [IES EC 2013]
+5V

5 kW
C
100 kW
B
E
5V

(A) Cut-off region (B) Saturation region

RB
VCE VCC
IB
VBB VBE

(A) 7.9 (B) 0.79  (C) 79  (D) 790 

Q.18 A silicon transistor with VBE  0.8 V,  dc  100 and VCE  0.2 V is used in the circuit shown below
[IES EE 2004]
+10 V

200 kW

What is the minimum value of RC for which transistor is in saturation?

(A) 4286  (B) 4667  (C) 5000  (D) 1000 
Q.19 For the circuit shown in the below figure, assuming  = 100 for the transistor, the transistor will be in
[IES EE 2001]
+10 V
8 kW
20 kW
Output
Input

10 kW
2 kW

(A) Cut-off region (B) Inverse active region

(C) Active region (D) Saturation region
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 6 GATE ACADEMY®

Q.20 Assuming VCE (sat)  0.3 V for a Silicon transistor at ambient temperature of 25 0 C and hFE  50 , the
minimum base current I B required to drive the transistor into saturation for the circuit shown is
[IES EC 2016]
+ 5V

1 kW
IB
Q

(A) 64 A (B) 78 A (C) 94 A (D) 140 A



Objective & Numerical Ans Type Questions :

Q.1 Two perfectly matched silicon transistors are connected as shown in the figure. Assuming the  of the
transistors to be very high and the forward voltage drop in diodes to be 0.7 V, the value of current I is
[GATE EE 2008, IISc-Bangalore]

(A) 0 mA (B) 3.6 mA

(C) 4.3 mA (D) 5.7 mA
Q.2 Two perfectly matched silicon transistors are connected as shown in figure. The value of the current I is
[GATE EE 2004, IIT-Delhi]
+ 3V
I
1kW

b = 1000 b = 1000
0.7 V

-5V

(A) 0 mA (B) 2.3 mA

(C) 4.3 mA (D) 7.3 mA
Q.3 In the silicon BJT circuit shown below, assume that the emitter area of transistor Q1 is half that of
transistor Q2 . [GATE EC 2010, IIT-Guwahati]

R = 9.3kW I0

Q1 Q2
(b1 = 700) 0.7 V (b2 = 715)

-10 V

The value of current I 0 is approximately

(A) 0.5 mA (B) 2 mA (C) 9.3 mA (D) 15 mA
Q.4 The matched transistors Q1 and Q2 shown in the adjoining figure have β =100. Assuming the base-
emitter voltages to be 0.7 V, the collector-emitter voltage V2 of the transistor Q2 is
[GATE IN 2010, IIT-Guwahati]
12 V 50 V

10 kW 20 kW

Q1 Q2
V2

–
(A) 33.9 V (B) 27.8 V (C) 16.2 V (D) 0.7 V
Q.5 Resistor R1 in the circuit below, has been adjusted so that I1  1 mA . The bipolar transistors Q1 and Q2
are perfectly matched and have very high current gain, so their base currents are negligible. The supply
kT
voltage VCC is 6 V. The thermal voltage is 26 mV.
q
[GATE EC 2016 (Set - 02), IISc-Bangalore]
VCC

R1
I2

Q1 Q2

I1 R2

The value of R2 (in  ) for which I 2  100 A is _______.

Q.6 In figure all transistors are identical and a high value of beta. The voltage VDC is equal to
[GATE EC 1991, IIT-Madras]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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GATE ACADEMY® 3 BJT Current Mirror Circuit
10 volts

5 mA 1 kW

VDC = ?

Q.7 The three transistors in the circuit shown below are identical with VBE  0.7 V and   100 . The voltage
V0 is [GATE IN 2007, IIT Kanpur]
2V 10 V

1kW
1kW
V0

(A) 0.2 V (B) 2 V (C) 7.4 V (D) 10 V

Q.8 The two transistor in below figure are identical. If   25, the current I C 2 is

(A) 28 A (B) 23.2 A (C) 26 A (D) 24 A

Q.9 Consider the current mirror below, and neglect base currents. What is I copy ?
VCC

I REF 0.25 mA
I copy

QREF 1 QREF 2 QREF 3

(A) 0.25 mA (B) 0.25 A (C) 83 mA (D) 83 A

Q.10 In the current mirrors below, neglect base currents and I REF  10 A, what is I copy 3 ?
VCC

I REF I copy1 I copy 2 I copy 3

QREF Q1 Q2 Q3

10
(A) A (B) 30 A (C) 10 A (D) 20 A
3
. Common Data Questions 11 & 12 .
The matched transistor Q1 and Q2 in the circuit below have I REF  50 A .
V+

I REF IC 2 = I0
I C1
I B1 IB2 +
Q1 Q2 VCE 2
+ + –
VBE1 VBE 2

V-

Q.11 If   , then I 0 is
(A) 100 A (B) 50 A (C) 25 A (D) 75 A
Q.12 If   50 then I 0 is
(A) 98.08 A (B) 74.04 A (C) 48.08 A (D) 24.04 A



Objective & Numerical Ans Type Questions :

Q.1 The three-terminal linear voltage regulator is connected to a 10  load resistor as shown in the figure If
Vin is 10 V, what is the power dissipated in the transistor ? [GATE EE 2007, IIT-Kanpur]
+10 V

Vin 1 kW RL = 10 W
6.6 V
Zener diode

(A) 0.6 W (B) 2.4 W (C) 4.2 W (D) 5.4 W

Q.2 For the circuit shown in the figure, the transistor has   40,VBE  0.7 V and the voltage across the zener
diode is 15 V . The current (in mA) through the Zener diode is ________.
[GATE IN 2014, IIT-Kharagpur]
+ 30 V

330 W
100 W

Q.3 In the series regulator circuit given VBE  0.7 V,   100, Vz  6.5 V . The output voltage V0 is ____V.
+ 25 V V0
220 W
20 kW 50 kW

50 kW 30 kW

Q.5 In the regulator circuit of given figure Vz  12 V, = 50, VBE  0.7 V . The Zener current is ______mA

. Common Data Questions 6 & 7 .

The transistor shunt regulator shown in below figure has a regulated output voltage of 10 V, when the
input varies from 20 V to 30 V. The relevant parameter for the Zener diode and the transistor are:
Vz  9.5 V, VBE  0.3V,   99 neglect the current through RB .
20 W

IZ IC
VZ
Vin (20 - 30) V V0 = 10 V
VBE
RB

Q.6 The maximum power dissipated in the Zener diode ( Pz ) is

(A) Pz  75 mW (B) Pz  85 mW (C) Pz  95 mW (D) Pz  115 mW
Q.7 The maximum power dissipated in the transistor ( PT ) is
(A) PT  7.9 W (B) PT  8.9 W (C) PT  9.9 W (D) PT  11.9 W
. Common Data Questions 8 & 9 .
Consider the voltage regulator circuit shown in below figure.
Vi b = 100
15 V V0
(Unregulated) R1 = (Regulated)
1.8 kW
RL = 2 kW

Vz = 8.3V

Q.9 The zener diode current is ____________mA.



Objective & Numerical Ans Type Questions :

Q.1 The input impedance of the emitter follower of figure shown is ______  .
[GATE IN 1993, IIT-Bombay]
VCC
hie = 600 W
h fe = 89
Vi
V0
1kW

Q.2 The circuit shown in figure is said to be in common______ configuration

[GATE IN 1995, IIT-Kanpur]
VCC

Vi
V0
Re

Q.3 A Common Emitter transistor Amplifier has a collector current of 1.0 mA when its base current is
25 A at the room temperature. It’s input resistance is approximately equal to _______ k .
[GATE EC 1994, IIT-Kharagpur]
Q.4 The Common Collector transistor configuration has the following property
[GATE IN 1994, IIT-Kharagpur]
(A) High input and low output - resistances (B) High input and high output - resistances
(C) Low input and low output - resistances (D) Low input and high output - resistances
Q.5 Which of the following statements are correct for basic transistor Amplifier configurations?
[GATE EC 1990, IISc-Bangalore]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 2 GATE ACADEMY®
(A) CB Amplifiers has low output impedance and low current gain.
(B) CC Amplifiers has low output impedance and a high current gain.
(C) CE Amplifiers has low output impedance and a high current gain.
(D) The current gain of CB Amplifier is higher than the current gain of CC Amplifiers.
V0
Q.6 For the Amplifier circuit of fig. the transistor has a  of 800. The mid band voltage gain of the
Vi
circuit will be [GATE EC 1993, IIT-Bombay]
+15 V

200 kW 470 W
6.4 mF
4.7 mF +
+

Vin Vout
100 kW

(A) 0 (B) 1 (C) 1 (D) 800

Q.7 In the transistor amplifier shown in figure, the ratio of small signal voltage gain when the emitter resistor
is bypassed by the capacitor ‘ Ce ’ to when it is not bypassed. (Assuming of simplified approximate h -
parameter model for transistor) is [GATE EE 1996, IISc-Bangalore]
Vcc

RC
R1
Vout
C1
Cc
Vin

R2
Re Ce

(1  h fe ) Re (1  h fe ) Re
(A) 1 (B) h fe (C) (D) 1 
hie hie
Q.8 In the BJT amplifier shown in the figure the transistor is biased in the forward active region putting a
capacitor across RE will [GATE EE 1997, IIT-Madras]
VCC

Rbias RL

+
+

Vin Vout
RE

R1 RC
V0
C2
C1
Vi R2
RE CE

(A) Increases (B) Decreases (C) Is unaffected (D) Drops to zero

Q.12 Choose the correct match for input resistance of various Amplifier Configuration shown in below.
Configuration
CB : Common Base
CC : Common Collector
CE : Common Emitter
Input Resistance
LO : Low
MO : Moderate
HI : High [GATE EE 2003, IIT-Madras]
(A) CB–LO, CC–MO, CE–HI (B) CB–HI, CC–LO, CE–MO
(C) CB–LO, CC–HI, CE–MO (D) CB–MO, CC–HI, CE–LO
Q.13 A bipolar transistor is operating in the active region with a collector current of 1 mA . Assuming that the
'  ' of the transistor is 100 and the transconductance ( g m ) and the input resistance (r ) of the transistor
in the common emitter configuration, are [GATE EC 2004, IIT-Delhi]
(A) g m  25 mA / V and r  15.6 K (B) g m  40 mA / V and r  4.0 K
(C) g m  25 mA / V and r  2.5 K (D) g m  40 mA / V and r  2.5 K
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 4 GATE ACADEMY®

Q.14 The transconductance g m of the transistor shown in figure is 10 mS. The value of input resistance Rin
is [GATE EC 2004, IIT-Delhi]
Vcc

RC
10 W
V0
C=¥ C=¥
VS
β = 50
10 kW
1 kW C=¥

(A) 10 k (B) 8.3 k (C) 5 k (D) 2.5 k

. Statement for Linked Question 15 and 16 .
In the following transistor circuit, VBE  0.7 V , re  25 m V / I E ,  and all the capacitance are very
large. [GATE EC 2008, IISc-Bangalore]
VCC = 9 V

3 kW
20 kW

CC1 CC 2

IE 3 kW
10 kW
2.3 kW CE

Q.15 The Value of DC current I E is

(A) 1 mA (B) 2 mA (C) 5 mA (D) 10 mA
Q.16 The mid-band voltage gain of the amplifier is approximately
(A) –180 (B) –120 (C) –90 (D) –60
Q.17 An amplifier circuit is shown is below. Assume that the transistor works in active region. The low
frequency small-signal parameters for the transistor are g m  20 mS , 0  50 , r0   , rb  0
VCC
1kW

+
~V i V0

2 kW

V 
What is the voltage gain AV   0  of the amplifier? [GATE IN 2006, IIT-Kharagpur]
 Vi 
(A) 0.967 (B) 0.976 (C) 0.983 (D) 0.998
Q.18 In a transconductance amplifier, it is desirable to have [GATE EC 2007, IIT-Kanpur]
(A) A large input resistance and large output resistance.
(B) A large input resistance and a small output resistance.
(C) A small input resistance and a large output resistance.
(D) A small input resistance and a small output resistance.
Q.19 The input impedance ( Zi ) and the output impedance ( Z 0 ) of an ideal transconductance (voltage
controlled current source) amplifier are [GATE EC 2006, IIT-Kharagpur]
(A) Zi  0, Z 0  0 (B) Z i  0, Z 0  
(C) Z i  , Z 0  0 (D) Z i  , Z 0  
Q.20 A small signal source Vi (t )  A cos 20t  B sin 10 t is applied to a transistor Amplifier as shown in fig
6

the transistor has   150 and hie  3 K which expression best approximates V0 (t ) ?
[GATE EC 2009, IIT-Roorkee]
12 V

100 kW 3 kW

100 nF

100 nF
V0 (t )
Vi (t )
20 kW
900 kW
100 mF

(A) V0 (t )  1500 ( A cos 20t  B sin 106 t ) (B) V0 (t )  150 ( A cos 20t  B sin 106 t )
(C) V0 (t )  1500 B sin 106 t (D) V0 (t )  150 B sin 106 t
Q.21 The amplifier circuit shown below uses a silicon transistor. The capacitance CC and C E can be assumed
to be short at signal frequency and the effect of output resistance r0 can be ignored. If C E is
disconnected from the circuit, which one of the following statements is TRUE ?
[GATE EC 2010, IIT-Guwahati]
VCC = 9 V

RB = 800 kW RC = 2.7 kΩ
CC V0
b = 100 CC

VS ~ RE = 0.3kW
CE
R1 R0

(A) The input resistance R1 increases and the magnitude of voltage gain AV decreases
(B) The input resistance R1 decreases and the magnitude of voltage gain AV increases
(C) Both input resistance R1 and the magnitude of voltage gain AV decrease
(D) Both input resistance R1 and the magnitude of voltage gain AV increase
Q.22 The current ib through the base of a silicon npn transistor is 1  0.1 cos (10000  t ) mA . At 300 K, the
r in the small signal model of the transistor is [GATE EC 2012, IIT-Delhi]
ib B C

rp r0

(A) 250  (B) 27.5  (C) 25  (D) 22.5 

Q.23 For the amplifier shown in the figure, the BJT parameters are VBE  0.7 V,   200 and thermal voltage
VT  25mV . The voltage gain (v0 / vi ) of the amplifier is _______.
[GATE EC 2014 (Set-01), IIT-Kharagpur]
VCC = +12 V

RC 5 kΩ
R1 33kΩ
1μF v0
vi 1μF

R2 11kΩ
RS 10 W

RE 1kΩ CE 1mF

Q.24 The circuit shown in figure represents a [GATE EC 2014 (Set-02), IIT-Kharagpur]

Ii Ai I i R

(A)Voltage controlled voltage source (B) Voltage controlled current source

Vin
Vout
RE

(A) g m RE 1 (B) I C RE VT (C) g m r0 1 (D) VBE  VT

Q.26 A BJT in a common-base configuration is used to amplify a signal received by a 50 antenna. Assume
kT / q  25mV . The value of the collector bias current (in mA) required to match the input impedance
of the amplifier to the impedance of the antenna is________.
[GATE EC 2014 (Set-04), IIT-Kharagpur]
Q.27 The magnitude of the mid-band voltage gain of the circuit shown in figure is (assuming h fe of the
transistor to be 100) [GATE EE 2014 (Set-01), IIT-Kharagpur]
+ VCC

10 kW
C
V0
C 10 kW
h fe = 100

Vi
1kW C

(A) 1 (B) 10 (C) 20 (D) 100

Q.28 The desirable characteristics of a transconductance amplifier are
[GATE EC 2014 (Set-03), IIT-Kharagpur]
(A) high input resistance and high output resistance
(B) high input resistance and low output resistance
(C) low input resistance and high output resistance
(D) low input resistance and low output resistance
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 8 GATE ACADEMY®
Q.29 For the DC analysis of the Common-Emitter amplifier shown, neglect the base current and assume that
the emitter and collector currents are equal. Given that VT  25 mV, VBE = 0.7 V, and the BJT output
resistance r0 is practically infinite. Under these conditions, the midband voltage gain magnitude
V0 V
Av  , is _________. [GATE EC 2017 (Set - 01), IIT-Roorkee]
Vi V
VCC = 12 V

RC 2 kW
73 kW R1 10 mF

10 mF C2

C1
RL = 8 kW V0
Vi 47 kW R2
RE 2 kW CE = 100 mF

Q.30 If the emitter resistance in a common-emitter voltage amplifier is not bypassed, it will
[GATE EC 2014 (Set-04), IIT-Kharagpur]
(A) Reduce both the voltage gain and the input impedance.
(B) Reduce the voltage gain and increase the input impedance.
(C) Increase the voltage gain and reduce the input impedance.
(D) Increase both the voltage gain and the input impedance.
Q.31 A good current buffer has [GATE EC 2014 (Set-01), IIT-Kharagpur]
(A) low input impedance and low output impedance.
(B) low input impedance and high output impedance.
(C) high input impedance and low output impedance.
(D) high input impedance and high output impedance.
. Common data for 32, 33 and 34 .
In the transistor amplifier circuit shown in the figure below, the transistor has the following parameters
 DC  60, VBE  0.7 V, hie  , h fe   . The capacitance CC can be assumed to be infinite.
[GATE EC 2006, IIT-Kharagpur]
12 V

1 kW

53kW

5.3 kW
VC
CC
VS

12 kW

C
100 kW V0
C

10 kW b = 100

(A) AV  200 (B) AV  100 (C) AV  20 (D) AV  10

Q.36 If Rs is the source resistance, the output resistance of an emitter- follower using the simplified hybrid
model would be [IES EC 1998]
hie  Rs hie  Rs 1 1
(A) (B) (C) Rs  (D)
1  h fe h fe h fe hoe
Q.37 In the circuit shown in the given figure, assume that the capacitor C is almost shorted for the frequency
range of interest of the input signal. Under this condition, the voltage gain of the amplifier will be
approximately. h fe  100, hie  1 k [IES EC 1999]
Supply

66 kW
C 33kW

Input 66 kW
0.66 kW Output

(A) 0.33 (B) 0.5 (C) 0.66 (D) 1

Q.38 A CE - Amplifier has RC  10 k , given hie  1k, h fe  50, hre  0 and hoe  40 k . What is the
voltage gain ? [IES EC 2006]
(A) – 500 (B) – 400 (C) – 50 (D) – 40
Q.39 The h-parameters of a CE amplifier feeding a load of 10k are hie  1k , h fe  50, hre  0 and
1
 40 k . The voltage gain would be [IES EC 2015]
hoe
(A)  40 (B) 100 (C)  400 (D)  500
Q.40 The transistor in BJT amplifier circuit shown below has   60 , ro  20 k , Vthermal  26 mV .
12 V

2.2 kW
220 kW
V0

Vi Q

The value of output impedance and voltage gain are

(A) 1.98k,  238.27 (B) 20 k,  238.27
(C) 22.2 k,  23.82 (D) 2.2 k,  23.82
Q.41 In the circuit shown below the Q-point is in the center of the load line. The transistor parameters are
  150 and VA   .
+5 V

R1 1.2 kW

Vs
R2 0.2 kW

-5 V

V0
The small-signal voltage gain Av  is __________.
Vs
Q.42 Consider an amplifier circuit shown below. Transistor parameter are given as   100 and
Vthermal  25 mV ,

4 kW

Vin Q2

372 kW

+10 V
The input impedance and voltage gain respectively are,
(A) 0.99 k, 200 (B) 390k, 200 (C) 0.99 k,  400 (D) 390k, 400
. Common data Questions for 43 & 44 .
Consider the circuit shown below. The transistor parameters are   120 and VA   .
+5 V

4 kW

V0
250 kW

Q.43 The hybrid-  parameter values of g m , r and ro are,

(A) 24 mA/V, , 5k (B) 24mA/V, 5k, 
(C) 48mA/V, 10k, 18.4 k (D) 48mA/V, 18.4 k, 10 k
V0
Q.44 The small signal voltage gain Av  is ____________.
Vs
. Common Data Question 45 to 51 .
Consider the network shown in below figure

Q.45 The value of re is ____________ 

Q.46 The value of input impedance Z i (with r0   ) is

(A) 1.07 k (B) 2.07 k (C) 3.07 k (D) 4.07 k
Q.47 The value of output impedance Z 0 (with r0   ) is ____________ k .

Q.48 The value of voltage gain Av (with r0   ) is

(A)  70.11 (B) 140.11 (C)  280.11 (D)  460.11
Q.49 The value of input impedance Zi (with r0  50 k) is ____________ k .

Q.50 The value of output impedance Z 0 (with r0  50 k) is

(A) 1.83 k (B) 2.83 k (C) 3.83 k (D) 4.83 k
Q.51 The value of voltage gain Av (with r0  50 k) ______________.
Q.52 In the circuit shown below   80 and VA  
+9 V

11kW

CE
2 kW

V0
Vs
3.71kW 10 kW

- 9V

V0
The small signal voltage gain Av  is ______________.
Vs



Objective & Numerical Ans Type Questions :

Q.1 The feedback amplifier shown in figure has [GATE EC 1989, IIT-Kanpur]
VCC

(A) current - series feedback with large input impedance and large output impedance.
(B) voltage - series feedback with large input impedance and low output impedance.
(C) voltage - shunt feedback with low input impedance and low output impedance.
(D) current - shunt feedback with low input impedance and output impedance.
Q.2 In a common Emitter amplifier, the un bypassed emitter resistance provides
[GATE EE 1992, IIT-Delhi]
(A) Voltage-shunt feedback (B) Current - Series feedback
(C) Negative - Voltage feedback (D) Positive - current feedback
Q.3 To obtain very high input and out put impedances in a feedback Amplifier, the mostly used is
[GATE EC 1995, IIT-Kanpur]
(A) Voltage - series (B) Current - series (C) Voltage - shunt (D) Current - shunt
Q.4 In the circuit shown in figure is a finite gain amplifier with a gain of K, a very large input impedance and
a very low output impedance. The input impedance of the feedback amplifier with the feedback impedance
Z connected as shown will be [GATE EC 1996, IISc-Bangalore]

+ +
Vi N V0
_ _

 1  Z   Z 
(A) Z 1   (B) Z 1  K  (C)  (D) 
 K  K  1  1  K 
Q.5 Negative feed back in
1. Voltage series configuration
2. current shunt configuration [GATE EC 1997, IIT-Madras]
(A) increases input impedance (B) decreases input impedance
(C) increases closed loop gain (D) leads to oscillation
Q.6 In a shunt-shunt negative feedback Amplifier, as compared to the basic Amplifier.
[GATE EC 1998, IIT-Delhi]
(A) both input and output impedance decreases.
(B) input impedance decreases but output impedance increases.
(C) input impedance increases but output impedance decreases.
(D) both input and output impedance increases.
Q.7 The circuit of the figure is an example of feedback of the following type [GATE EC1998, IIT-Delhi]
+Vcc
R R

V0
C

(A) Current series (B) Current shunt (C) Voltage series (D) Voltage shunt
Q.8 Negative feedback in an amplifier [GATE EC 1999, IIT-Bombay]
(A) Reduces gain (B) Increase frequency and phase distortions
(C) Reduces bandwidth (D) Increase Noise
Q.9 An amplifier has an open-loop gain of 100, an input impedance of 1 k and an output impedance of
100  . A feedback network with a feedback factor of 0.99 is connected to the amplifier in a voltage
series feedback mode. The new input and output impedance respectively are
[GATE EC 1999, IIT-Bombay]
(A) 10  and 1  (B) 10  and 10 
(C) 100 k and 1  (D) 100 k and 1 k
Q.10 In a negative feedback amplifier using Voltage - Series (i.e., voltage- sampling, series mixing) feedback.
[GATE EC 2000, IIT-Kharagpur]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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GATE ACADEMY® 3 Low Frequency BJT Amplifier
(A) Ri decreases and R0 decreases (B) Ri decreases and R0 increases
(C) Ri increases and R0 decreases (D) Ri increases and R0 increases
( Ri and R0 denote the input and output resistances respectively)
Q.11 Voltage series feedback (also called series-shunt feedback) results in [GATE EC 2004, IIT-Delhi]
(A) increase in both input and output impedances.
(B) decrease in both input and output impedances.
(C) increase in input impedance and decrease in output impedance.
(D) decrease in input impedance and increase in output impedance.
Q.12 The feedback used in the circuit shown figure can be described as [GATE EE 2004, IIT-Delhi]
VCC

RC
RF C=a
V0

C
RL

RS RB
CE

(A) Shunt - Series feedback

(B) Shunt - Shunt feedback
(C) Series - Shunt feedback
(D) Series - Series feedback
Q.13 The effect of current shunt feedback in an amplifier is to [GATE EC 2005, IIT-Bombay]
(A) increase the input resistance and decrease the output resistance.
(B) increase both input and output resistances.
(C) decrease both input and output resistances.
(D) decrease the input resistance and increase the output resistance.
Q.14 A FET source follower is shown in the figure below. [GATE EE 2005, IIT-Bombay]
15 V

1μF
Vi
V0
1 MW
1.5 kW

The nature of feedback in this circuit is

(A) positive current (B) negative current
(C) positive voltage (D) negative voltage
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131‐13156 Online Test Series
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Analog Electronics [Workbook] 4 GATE ACADEMY®
Q.15 As shown in the figure, a negative feedback system has an amplifier of gain 100 with ±10% tolerance in
the forward path and an attenuator of value 9/100 in the feedback path. The overall system gain is
approximately. [GATE EE 2010, IIT-Guwahati]
Vi 100 ± 10% V0

9
100

(A) 10 ± 1% (B) 10 ± 2% (C) 10 ± 5% (D) 10 ± 10%

Q.16 In a voltage-voltage feedback as shown below which one of the following statements is TRUE if the gain
k is increased? [GATE EC/EE/IN 2013, IIT-Bombay]

vin v1 A0 vout

v f = kvout k

(A) The input impedance increases and output impedance decreases.

(B) The input impedance increases and output impedance also increases.
(C) The input impedance decreases and output impedance also decreases.
(D) The input impedance decreases and output impedance increases.
Q.17 In the ac equivalent circuit shown in the figure, iin is the input current and RF is very large, the type of
feedback is [GATE EC 2014, IIT-Kharagpur]

RD
RD vout
M2
M1

iin RF
small signal
input

(A) voltage-voltage feedback.

(B) voltage-current feedback.
(C) current-voltage feedback.
(D) current-current feedback.
Q.18 The feedback topology in the amplifier circuit (the base bias circuit is not shown for simplicity) in the
figure is [GATE EC 2014, IIT-Kharagpur]

RC Io
vo

RS
RE
va

(A) Voltage shunt feedback (B) Current series feedback

(C) Current shunt feedback (D) Voltage series feedback
Q.19 A good transconductance amplifier should have [GATE EC 2017 (Set - 01), IIT-Roorkee]
(A) high input resistance and low output resistance.
(B) low input resistance and high output resistance.
(C) high input and output resistances.
(D) low input and output resistances.
Q.20 Circuit of a feedback amplifier having series type of feedback is shown in the given figure.
VCC

V1
V0
Re

The  of feedback network is determined by [IES EE 1994]

2
R R R 
(A)  e (B) Re (C)  L (D)   e 
RL Re  RL 
Q.21 The given circuit has a feedback factor of [IES EC 1999]
+ VCC

RC
V0
RS

VS
RE

 RC  RE  RE  RC
(A) (B) (C) (D)
RS RC RS RE

Ri
Vi
Op-amp V0

(A) Voltage series feedback (B) Voltage shunt feedback

(C) Current shunt feedback (D) Current series feedback
Q.23 The open-loop voltage gain of an amplifier is 240. The noise level in the output without feedback is 100
1
mV. If a negative feedback with   is used, the noise level in the output will be [IES EE 2003]
60
(A) 1.66 mV (B) 2.4 mV (C) 4.0 mV (D) 20 mV
Q.24 An Amplifier has an open loop gain of 1000  10 . Negative feedback is provided such that the gain
variation remains within 0.1%. What is the amount of feedback  F ? [IES EC 2006]
(A) 1/10 (B) 1/9 (C) 9/100 (D) 9/1000
Q.25 An amplifier without feedback has a gain of 1000. What is the gain with a negative feedback of 0.009?
[IES EE 2007]
(A) 900 (B) 125 (C) 100 (D) 10
Q.26 A feedback amplifier has an open loop gain of –100. If 4% of the output is feedback loop gain of the
amplifier? [IES EC 2008]
(A) –33.3 (B) –25 (C) –20 (D) +25
Q.27 Match list-I (Type of Feedback) with list-II (Effect on Rin and Rout ) and select the correct answer using
the code given below the lists. [IES EC 2008]
List – I List – II
A. Voltage series 1. Rin increases and Rout decreases.
B. Voltage shunt 2. Rin and Rout decreases
C. Current series 3. Rin and Rout increases
D. Current shunt 4. Rin decreases and Rout increases
Codes:
A B C D
(A) 3 4 2 1
(B) 1 2 3 4
(C) 2 3 1 4
(D) 4 1 2 3
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GATE ACADEMY® 7 Low Frequency BJT Amplifier
 A0
Q.28 A negative feedback amplifier with open-loop gain A  0 and feed back factor  ( 0) will have
 0
1 j
0
a 3 dB cut off at what frequency? [IES EE 2008]
0
(A) 0 A0  (B) 0 (1  A0 ) (C) (D) 0 (1  A0 )
(1  A0 )
Q.29 The Amplifier circuit shown in the figure is an example of [IES EC 2011]
+VCC

RC
RF
Vout
Vin

RE CE

(A) Voltage series feedback (B) Voltage shunt feedback

(C) Current series feedback (D) Current shunt feedback
Q.30 A feedback amplifier is designed with an amplifier gain of –1000 and feedback of   0.1 . If the
amplifier had a gain change of 20% due to temperature, the change in gain of the feedback amplifier is
[IES EE 2013]
(A) 10% (B) 5% (C) 0.2% (D) 0.01%
1
Q.31 An amplifier with mid band gain A  500 has negative feedback   . If upper cut-off without
100
feedback were at 60 kHz, then with feedback it would become [IES EC 2014]
(A) 10 kHz (B) 360 kHz (C) 12 kHz (D) 300 kHz
Q.32 In a voltage-series-feedback amplifier with open loop gain Av and the feedback factor , the input
resistance becomes [IES EE 2015]
Ri Ri
(A) (B) Ri (1   Av ) (C) Ri (1  Av ) (D)
(1  Av ) (1  Av )

Q.33 A negative feedback of   2.5  103 is applied to an amplifier of open-loop gain 1000. What is the change
in overall gain of the feedback amplifier, if the gain of the internal amplifier is reduced by 20%?
[IES EC 2016]
(A) 2957 (B) 2867 (C) 2757 (D) 2667



Objective & Numerical Ans Type Questions :

Q.1 In a multi-stage RC-Coupled Amplifier the coupling capacitor [GATE EC 1993, IIT-Bombay]
(A) Limits the low frequency response.
(B) Limits the high frequency response.
(C) Does not effect the frequency response.
(D) Blocks the d.c components without effecting the frequency response.
Q.2 The Bandwidth of an n-stage tuned Amplifier, with each stage having a bandwidth of B, is given by
[GATE EC 1993, IIT-Bombay]
1 1
B B
(A) (B) (C) B 2 − 1 n
(D) B / 2 − 1 n
n n
Q.3 An RC-Coupled Amplifier is assumed to have a single-pole low frequency transfer function. The
maximum lower-cut-off frequency allowed for the Amplifier to pass 50 Hz . Square wave with no more
than 10% tilt is ______Hz. [GATE EC 1995, IIT-Kanpur]
Q.4 An Amplifier has an open-loop gain of 100 and its lower and upper-cut-off frequency of 100 Hz and
100 KHz respectively, a feedback network with a feedback factor of 0.99 is connected factor of amplifier.
The new lower and upper-cut-off frequency’s are at _________ and __________.
[GATE EE 1995, IIT-Kanpur]
Q.5 An npn transistor has a beta cut-off frequency fβ of 1 M Hz and Common Emitter short circuit low
frequency current gain β0 of 200 at unity gain frequency fT and the alpha cut-off frequency f α
respectively are [GATE EC 1996, IISc-Bangalore]
(A) 200 MHz, 201 MHz (B) 200 MHz, 199 MHz
(C) 199 MHz, 200 MHz (D) 201 MHz, 200 MHz
Q.6 From measurement of the rise time of the output pulse of an Amplifier whose input is a small Amplitude
square wave, one can estimate the following parameter of the Amplifier
[GATE EC 1998, IIT-Delhi]
(A) Gain-bandwidth product (B) Slew Rate
(C) Upper 3-dB frequency (D) Lower 3-dB frequency
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 2 GATE ACADEMY®

Q.7 A multistage Amplifier has a low-pass Response with three Real poles at s = −ω1 , − ω2 and ω3 . The
approximate overall bandwidth B of the Amplifier will be given by [GATE EC 1998, IIT-Delhi]
1 1 1 1
(A) B = ω1 + ω2 + ω3 (B) = + +
B ω1 ω2 ω3
1
(C) B = (ω1 + ω2 + ω3 ) 3 (D) B = ω12 + ω22 + ω33
Q.8 The fT of a BJT is related to its g m , Cπ and Cμ as follows [GATE EC 1998, IIT-Delhi]
Cπ + Cμ 2π (Cπ + Cμ )
(A) fT = (B) fT =
gm gm
gm gm
(C) fT = (D) fT =
Cπ + Cμ 2π (Cπ + Cμ )
Q.9 An NPN transistor (with Cπ = 0.3 pf ) has a unity gain cutoff frequency fT of 400 MHz at a DC-bias
current I C = 1mA . The value of its Cπ (in pf ) is approximately (VT = 26 mV) .
[GATE EC 1999, IIT-Bombay]
(A) 15 (B) 30 (C) 50 (D) 96
Q.10 An amplifier is assumed to have a single-pole high frequency transfer function. The rise time of its output
response to a step function input is 35 nsec. The upper 3 dB frequency (in MHz) for the amplifier to a
sinusoidal input is approximately at [GATE EC 1999, IIT-Bombay]
(A) 4.55 (B) 10 (C) 20 (D) 28.6
Q.11 The current gain of a bipolar transistor drops at high frequencies because of
[GATE EC 2000, IIT-Kharagpur]
(A) Transistor capacitances (B) High current effects in the base
(C) Parasitic inductive elements (D) The Early effect
Q.12 An npn BJT has g m = 38 mA / V, Cμ = 10−14 F, Cπ = 4 × 10−13 F and DC current gain β = 90 . For this
transistor fT and fβ are [GATE EC 2001, IIT-Kanpur]
(A) fT = 1.64 × 108 Hz and fβ = 1.47 × 1010 Hz (B) fT = 1.47 × 1010 Hz and fβ = 1.64 ×108 Hz
(C) fT = 1.33 × 1012 Hz and fβ = 1.47 × 1010 Hz (D) fT = 1.47 × 1010 Hz and fβ = 1.33 ×1012 Hz
Q.13 Three identical RC-Coupled transistor amplifiers are cascaded. If each of the amplifiers has a frequency
response as shown in the figure, the overall frequency response is as given as
[GATE EC 2002, IISc-Bangalore]
AV
dB

0
-3

f
40 Hz 2 kHz

0 0

-3 -3

f f
40 Hz 0.5 kHz 40 Hz 1 kHz

0 0

-3 -3

f f
10 Hz 0.5 kHz 40 Hz 2 kHz

Q.14 A unity gain buffer amplifier has a bandwidth of 1 MHz. The output voltage of the amplifier for an input
of 2V sinusoid of frequency 1 MHz will be [GATE IN 2002, IISc-Bangalore]
2 4
(A) 2 V (B) 2 2 (C) (D) V
2 2
Q.15 Generally, the gain of a transistor Amplifier falls at high frequency due to the
[GATE EC 2003, IIT-Madras]
(A) Internal Capacitances of the device (B) Coupling Capacitor at the input
(C) Skin Effect (D) Coupling Capacitor at the output
Q.16 The ac schematic of an NMOS common-source stage is shown in the figure below, where part of the
biasing circuits has been omitted for simplicity. For the n-channel MOSFET M, the trans-conductance
g m = 1mA/V and body effect and channel length modulation effect are to be neglected. The lower cutoff
frequency in Hz of the circuit is approximately at [GATE EC/EE/IN 2013, IIT-Bombay]

RD
10 kW
C
V0
1mF
Vi M
RL
10 kW

(A) 8 (B) 32 (C) 50 (D) 200

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Analog Electronics [Workbook] 4 GATE ACADEMY®
Q.17 Which one of the following statement is correct about an ac-coupled common-emitter amplifier operating
in the mid-band region? [GATE EC 2016 (Set - 02), IISc-Bangalore]
(A) The device parasitic capacitances behave like open circuits, whereas coupling and bypass capacitances
behave like short circuits.
(B) The device parasitic capacitances, coupling capacitances and bypass capacitances behave like open
circuits.
(C) The device parasitic capacitances, coupling capacitances and bypass capacitances behave like short
circuits.
(D) The device parasitic capacitances behave like short circuits, whereas coupling and bypass capacitances
behave like open circuits.
Q.18 The Miller effect in the context of a Common Emitter amplifier explains
[GATE EC 2017 (Set - 01), IIT-Roorkee]
(A) an increase in the low-frequency cut-off frequency
(B) an increase in the high-frequency cut-off frequency
(C) a decrease in the low-frequency cut-off frequency
(D) a decrease in the high-frequency cut-off frequency
Q.19 A two-stage amplifier is required to have an upper cut-off frequency of 2MHz and a lower cut-off
frequency of 30Hz. The upper and lower cut-off frequencies of individual stages are respectively
approximately [IES EC 1993]
(A) 4 MHz, 60 Hz (B) 3 MHz, 20 Hz (C) 3 MHz, 60 Hz (D) 4 MHz, 20 Hz
Q.20 The upper 3 dB frequency in a Common Emitter amplifier is given in terms of the hybrid parameters as
[IES EC 1995]
g g h fe g
(A) b ' e (B) b ' e (C) (D) m
2πC C gb ' e h fe
Q.21 Consider the following statements [IES EC 2000]
The lower cut - off frequencies for an RC coupled CE amplifier depend on
1. Input and output coupling capacitors
2. Emitter bypass capacitor
3. Junction capacitors
Which of these statements is/are correct?
(A) 1 alone (B) 2 alone (C) 1 and 2 (D) 2 and 3
Q.22 The upper cut-off frequencies f 21 and f 22 of the two stages of a cascaded amplifier are respectively 5 MHz
and 3.3 MHz. The equivalent upper cut-off frequency of the cascaded amplifier would be
[IES EE 2000]
(A) 4.16 MHz (B) 3.33 MHz (C) 2 MHz (D) 5 MHz
Q.23 In a single-stage RC coupled common emitter amplifier, the phase shift at the lower 3 dB frequency is
[IES EC 2001]
(A) Zero (B) 135° (C) 180 (D) 225°
Q.24 In an RC coupled amplifier, the gain decreases in the frequency response due to the [IES EE 2001]
(A) Coupling capacitor at low frequency and by pass capacitor at high frequency
(B) Coupling capacitor at high frequency and bypass capacitor at low frequency
(C) Coupling junction capacitance at low frequency and coupling capacitor at high frequency
(D) Device junction capacitor at high frequency and coupling capacitor at low frequency.
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GATE ACADEMY® 5 Low Frequency BJT Amplifier
Q.25 An RC amplifier stage has a bandwidth of 500 kHz. What will be the rise time of this amplifier stage?
[IES EC 2002]
(A) 0.35 μs (B) 0.7 μs (C) 1.0 μs (D) 2.0 μs
Q.26 A BJT is to be used in a high frequency circuit in common emitter amplifier. For a higher upper cut - off
frequency ( Cμ , Cπ and r0 have their usual meanings) [IES EC 2002]
(A) Cμ should be as small as possible
(B) π0 and Cμ should be as large as possible
(C) Cμ and Cπ should be as large as possible
(D) r0 , Cμ and Cπ should be as large as possible
Q.27 The Common Emitter current gain -bandwidth product of a transistor ( fT ) is defined as the frequency at
which [IES EC 2003]
(A) Alpha of the transistor falls by 3 dB (B) Beta of the transistor falls by 3 dB
(C) Beta of the transistor falls by unity (D) Power gain of the transistor falls by unity
Q.28 Which of the following components control the low frequency of the RC coupled amplifier?
1. Wiring capacitor
2. Parasitic capacitances of transistor
3. Coupling capacitances
4. Emitter bypass capacitance
Of these statements which are correct [IES EC 2003]
(A) 1 and 2 (B) 2 and 3 (C) 3 and 4 (D) 1, 2 and 4
Q.29 An amplifier has two identical cascaded stages. Each stage has a band width of 20 KHz. The overall band
width shall approximately be equal to [IES EC 2003]
(A) 10 KHz (B) 12.9 KHz (C) 20 KHz (D) 28.3 KHz
Q.30 In an RC coupled common emitter amplifier [IES EE 2003]
(A) Coupling capacitance affects the h.f. response and by pass capacitance affects the l.f. Response.
(B) Both coupling and bypass capacitances affect the h.f. response only.
(C) Both coupling and bypass capacitances affect the l.f. response only.
(D) Coupling capacitance affects the l.f. response and the bypass capacitance affects h.f.
Q.31 The transfer function of a transistor amplifier is given by [IES EC 2004]
V 4240
Av = 0 =
Vs  f  f 
1 + j 5 
1+ j 
 4 × 10   4 ×105 
Which one of the following gives the approximate upper 3-dB frequency f H* of the amplifier
(A) 4 ×105 Hz (B) 2.2 ×106 Hz (C) 4 ×106 Hz (D) 4.4 ×106 Hz
Q.32 Two identical RC coupled amplifier, each having an upper cut-off frequency fu , are cascaded with
negligible loading. What is the upper cur-off frequency of the overall amplifier? [IES EE 2004]
fu f
(A) (B) f u 2 −1 (C) u (D) 2 fu
2 −1 2
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Analog Electronics [Workbook] 6 GATE ACADEMY®

Q.33 Two identical RC coupled amplifiers, each having an lower cut-off frequency f1 , are cascaded with
negligible loading. What is the lower cut-off frequency of the overall amplifier? [IES EE 2004]
f1 f
(A) (B) f1 2 − 1 (C) 1 (D) 2 f1
2 −1 2
Q.34 If the coupling capacitor of a CE transistor amplifier is shorted, which one of the following graphs will
represent the frequency response curve of the amplifier?
( Av = voltage gain, f = frequency in Hertz, Amax = maximum value of Av ) [IES EE 2004]
(A) (B)
Amax Amax
AV AV

f f

Q.35 fT is the frequency at which the short circuit [IES EC 2005]

(A) Common collector current gain has a magnitude of unity
(B) Common base current gain has a magnitude of unity
(C) Common emitter current gain has a magnitude of unity
1
(D) Common emitter current gain has a magnitude of .
2
Q.36 A cascaded Amplifier comprises N identical non-interacting stages, each having a lower 3 dB frequency
of f L . If f L* is the lower 3 dB frequency of the cascaded Amplifier, then which one of the following is
correct? [IES EC 2005]
(A) f L* = f L (B) f L* = f L 21/ n − 1

(C) f L* = f L / 21/ n − 1 (D) f L* = f L / N

Q.37 In a FET common-source high frequency amplifier, which one of the following is the correct. Expression
for input capacitance? [IES EC 2006]
(A) Ci = C gs + (1 − AV ) C gd (B) Ci = C gs + (1 − 1/AV ) C gd
(C) Ci = C gd + (1 − AV ) C gs (D) Ci = C gd + (1 − 1/AV ) C gs
Q.38 The two stages of a cascade amplifier have individual upper cut-off frequencies f1 = 5 MHz and f 2 =
3.33 MHz. What is the best approximation for the upper cut-off frequency of the cascade combination?
[IES EC 2006]
(A) 4.16 MHz (B) 3.33 MHz (C) 2.5 MHz (D) 5.00 MHz
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GATE ACADEMY® 7 Low Frequency BJT Amplifier

Q.39 When two amplifiers each of bandwidth f H = 10 kHz are cascade, the overall bandwidth becomes
[IES EE 2006]
(A) 10 kHz (B) 6.4 kHz (C) 5 kHz (D) 20 kHz
Q.40 Which of the following statement is correct? [IES EC 2007]
The rise time of an amplifier is
(A) Directly proportional to the upper 3-dB frequency
(B) Inversely proportional to the upper 3-dB frequency
(C) Directly proportional to the lower 3-dB frequency
(D) Inversely proportional to the lower 3-dB frequency.
Q.41 Cascode amplifiers when compared with a simple Common Emitter amplifier provide which of the
following? [IES EC 2007]
(A) Higher voltage gain and same bandwidth
(B) Same voltage gain but higher bandwidth
(C) No change in either voltage gain (or) Bandwidth
(D) Voltage gain less than one but bandwidth equal to fT
Q.42 An Amplifier has gain A = 100∠1800 , Upper cutoff frequency of 100 kHz and lower cutoff frequency of
1 kHz. A negative feedback of β = 0.1 is added. Which one of the following is not correct?
[IES EC 2008]
(A) Gain becomes 100/11
(B) Lower cutoff frequency becomes (1000/11)Hz
(C) Upper cutoff frequency becomes 1.1 MHz
(D) dB of feedback is 20 log10 11
Q.43 Which of the following components control the high frequency response of the R-C coupled Amplifier?
1. Parasitic capacitances of the transistor
2. Coupling capacitance
3. Stray capacitance
4. Wiring capacitance
Select the correct answer using the code given below [IES EC 2008]
(A) 1 and 2 only (B) 2 and 3 only (C) 3 and 4 only (D) 1, 3 and 4
Q.44 What is the effect of cascading the amplifier stages? [IES EE 2008]
(A) To increase the voltage gain and increase the bandwidth.
(B) To increase the voltage gain and reduce the bandwidth.
(C) To decrease the voltage gain and increase the bandwidth.
(D) To decrease the voltage gain and reduced the bandwidth.
Q.45 The lower 3dB frequency of an n-stage amplifier with non-interacting stages is given by

fL  1  fL  1 
(A) (B) f L  2 n − 1 (C) (D) f L  2 n − n 
1
  1
 
2n −1 2n − n
Where f L is the 3dB frequency of a single stage. [IES EC 2012]



Answer Keys :

1. A 2. C 3. 159 4. * 5. A
6. C 7. A 8. D 9. A 10. B
11. A 12. B 13. A 14. A 15. A
16. A 17. A 18. D 19. B 20. A
21. C 22. A 23. D 24. D 25. B
26. A 27. C 28. C 29. B 30. C
31. A 32. B 33. A 34. B 35. C
36. C 37. A 38. C 39. B 40. B
41. B 42. D 43. D 44. B 45. A
46. A 47. D 48. C 49. B 50. C

Objective & Numerical Ans Type Questions : I DS (mA)

Q.1 The small-signal resistance (i.e., dVB /dI D ) in VGS = 4 V

4
kΩ offered by the n-channel MOSFET M 3V
shown in the figure below, at a bias point of 3
2V
VB = 2 V is (device date for M: device trans- 2
1V
conductance parameter k N = μ nC 'ox (W /L) 1

= 40 μA/V 2 , threshold voltage VTN = 1V, and 0 VDS (V)

neglect body effect and channel length Q.2 The transconductance of the MOSFET is
modulation effects) [GATE EE 2005, IIT Bombay]
[GATE EC 2013, IIT Bombay] (A) 0.75 mS (B) 1 mS
VB (C) 2 mS (D) 10 mS
Q.3 The voltage gain of the amplifier is
ID
[GATE EE 2005, IIT Bombay]
(A) + 5 (B) – 7.5
(C) + 10 (D) – 10
M Q.4 In the circuit shown in the figure, the
channel length modulation of all transistors
is non-zero (λ ≠ 0). Also, all transistors
operate in saturation and have negligible
(A) 12.5 (B) 25
body effect. The ac small signal voltage gain
(C) 50 (D) 100
(V0 /Vin ) of the circuit is
. Statement for Linked Answer Qu 2 & 3 .
Assume that the threshold voltage of the n- channel [GATE EC 2016, IISc Bangalore]
VDD
MOSFET shown in figure is + 0.75 V. The output
characteristics of the MOSFET are shown below.
VDD = 25 V
M3 M2
R = 10 kΩ
Vout VG

+ V0
Vin = 2 mV
-
Vin M1
2V

(A) − g m1 (r01 r02 r03 ) Q.6 Two identical NMOS transistor M 1 and M 2

  are connected as shown below. Vbias is

 1 
(B) − g m1  r01   r03  chosen so that both transistor are in
  gm3  
saturation. The equivalent g m of the pair is
  1  
(C) − g m1  r01   r02 r03  defined to be ∂ I out at constant Vout .
∂Vi
  g m 2  
[GATE EC 2008, IISc Bangalore]
  1  
(D) − g m1  r01   r03 r02  I out
Vout
  g m3  
Vbias M2
Q.5 Two identical NMOS transistors M 1 and
M 2 are connected as shown below. The
circuit is used as an amplifier with the input Vi M1
connected between G and S terminals and
the output taken between D and S terminals.
Vbias and VD are so adjusted that both The equivalent g m of the pair is
transistors are in saturation. The (A) The sum of individual g m 's of the
transconductance of this combination is transistors
∂i
defined as g m = D while the output (B) The product of individual g m 's of the
∂vGS
transistors
∂v
resistance is r0 = DS , where iD is the (C) Nearly equal to the g m of M 1
∂iD
current flowing into the drain of M 2 . Let (D) Nearly equal to g m / g0 of M 2
g m1 , g m2 be the transconductances and Q.7 In the circuit shown, the threshold voltages of
r01 , r02 be the output resistances of the pMOS (V ) tp and nMOS (Vtn )
transistors M 1 and M 2 respectively. transistors are both equal to 1 V. All the
VD transistors have the same output resistance rds
D
of 6 M Ω . The other parameters are listed
Vbias M2
below :
G M1 W 
μ n Cox = 60 μA/V 2 ;   =5
S  L  nMOS
Which of the following statements about W 
μ pCox = 30 μA/V 2 ;   = 10
estimates for g m and r0 is correct?  L pMOS
[GATE EC 2018, IIT Guwahati] μ n and μ p are the carrier mobilities, and
(A) g m ≈ g m1 g m2 r02 and r0 ≈ r01 + r02 Cox is the oxide capacitance per unit area.
(B) g m ≈ g m1 + g m2 and r0 ≈ r01 + r02 Ignoring the effect of channel length
modulation and body bias, the gain of the
(C) g m ≈ g m1 and r0 ≈ r01 g m2 r02
circuit is ______ (rounded off to 1 decimal
(D) g m ≈ g m1 and r0 ≈ r02 place). [GATE EC 2019, IIT Madras]

V dd = 4 V Q.10 An n-channel depletion MOSFET has

following two points on its I D − VGS curve :
(i) VGS = 0 at I D = 12 mA and
(ii) VGS = – 6 Volts at Z0 = ∞
Vo ut
Which of the following Q-points will give
Vin the highest transconductance gain for small
signals? [GATE EC 2006, IIT Kharagpur]
(A) VGS = – 6 Volts
(B) VGS = – 3 Volts
Q.8 In the circuit shown, V1 = 0 and V2 = Vdd .
(C) VGS = 0 Volts
The other relevant parameters are mentioned
in the figure. Ignoring the effect of channel (D) VGS = 3 Volts
length modulation and the body effect, the
Q.11 In the circuit shown in the figure, transistor
value of I out is ______ mA (rounded off to
M1 is in saturation and has
1 decimal place).
transconductance gm = 0.01 Siemens.
[GATE EC 2019, IIT Madras]
Vdd Ignoring internal parasitic capacitances and
assuming the channel length modulation λ to
W W be zero, the small signal input pole
=1 0 =1 0 W /L = 40
L L
frequency (in kHz) is _________.
Vdd W W
I out [GATE EC 2016, IISc Bangalore]
V1 =5 =5 V2
L L
VDD
1 mA

1 kW
W /L = 2 W /L = 3

V0
50 pF
Q.9 In the MOSFET amplifier of the figure, the
Vin M1
signal output V1 and V2 obey which of the 5 kW
following relationship.
[GATE EC 1998, IIT Delhi]
VDD . Common Data Questions 12 & 13 .

RD The circuit shown in below figure with

VGSQ = 6 V, I DQ = 2.5 mA
12 V
V1
2.2 kW
Vi ~ RD V2 V0
2 I D (ON ) = 6 mA
100 MW
Vi VGS (ON ) = 8 V
V V VT = 3V
(A) V1 = 2 (B) V1 = − 2 z0
2 2 zi YOS = 20 mS
(C) V1 = 2V2 (D) V1 = −2V2
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Analog Electronics [Workbook] 4 GATE ACADEMY®

Q.12 The value of g m is VDD

(A) 1.44 mS (B) 2.44 mS

(C) 3.44 mS (D) 4.44 mS 60 kW 10 kW
Q.13 The value of Av is ________. 2 kW V0
. Common Data Questions 14 & 15 . +
Consider the source-follower circuit in given Vs 300 kW
–
figure. The values of parameter are
g m = 2 mS and r0 = 100 kΩ .
(A) – 8.01 (B) 8.01
+5 V
(C) 14.16 (D) – 14.16
Q.19 Consider the common source circuit in given
figure. The transistor parameters are
V0 VTN = 0.8 V, K n = 1mA / V 2 and λ = 0 . The
+
Vs 500 kΩ small-signal voltage gain is
− 4 kΩ
+5V
−5 V

Q.14 The voltage gain Av is 165 kW 7 kW

(A) 0.89 (B) – 0.89 V0
(C) 2.79 (D) – 2.79
Q.15 The output resistance R0 is _________ kΩ . Vs 35kW 0.5 kW

Q.16 Which of the following gain equations is

correct for a MOSFET common-source -5V
amplifier?
(A) – 10.83 (B) – 8.96
( g m is mutual conductance, and RD is load
(C) – 5.76 (D) – 3.28
resistance at the drain)
Q.20 For the circuit shown in below figure, the
(A) AV = g m /RD (B) AV = g m RD
transistor parameters are VTN = 2V ,
(C) AV = g m /(1 + RD ) (D) AV = RD /g m Kn = 0.20 mA/V2 and λ = 0 . Determine the
Q.17 A MOSFET has a drain circuit resistance Rd voltage gain AV = (V0 / Vs ) .
of 100 kΩ and operates at 20 kHz. The VDD = 10 V
MOSFET parameters are : g m = 1.6 mA/V ,
RD = 8 kW
rd = 44 kΩ , C gs = 3.0 pF , Cds = 1.0 pF and RF
V0
C gd = 2.8 pF . The voltage gain of this Rs C®¥ 100 kW

device as a single stage amplifier is ______. +

+ 10 kW
Q.18 In the circuit of given figure, the parameters Vs Vi
are g m = 1mA / V, r0 = 50 kΩ . The gain – –

V0
Av = is (A) – 3.44 (B) – 7.56
Vs
(C) – 9.5 (D) – 11.6
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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GATE ACADEMY® 5 MOSFET Amplifier

. Common Data Questions 21 to 23 . (A) 3.84 (B) – 3.84

Consider the common source amplifier (C) 8.52 (D) – 8.52
shown in given figure. The transistor . Common Data Questions 25 & 26 .
parameter are VTN = 1.5 V , K n = 0.5 mA / V 2 For the circuit shown in figure the
−1
and λ = 0.01V . The resistance of source is parameters are : VDD = 11V, R1 = 80 kΩ,
Rs = 4 kΩ . R2 = 30 kΩ and RD = 5kΩ . The transistor
+10 V
parameters are : VTN = 1.5 V, k = 0.5 mA/V 2
and λ = 0.01V−1 . Assume RG = 4 kΩ .
70.9 kW R1 RD 5 kW
VDD
4 kW V0

+ Rs
RD
Vs R2 29.1kW R1
– V0
R0
RG CC1
Ri

Q.21 The small-signal voltage gain Av is _____.

Q.22 The amplifier output resistance is Vi R2
R0
(A) 4.76 kΩ (B) 100 kΩ
(C) 5 kΩ (D) ∞
Q.23 The amplifier input resistance is ________
kΩ .
V0
Q.24 For the circuit shown in figure assume Q.25 The small signal voltage gain Av = is
Vi
parameters are : VGSQ = 2 V . Assume
________.
transistor parameters are: VTN = 1V,
Q.26 The output resistance R0 is
k = 0.80 mA/V 2 and λ = 0.02 V −1 . Assume
(A) 2.73kΩ (B) 4.73kΩ
the transistor is biased in the saturation
region. The small signal voltage gain (C) 6.73kΩ (D) 8.73kΩ
V
Av = 0 is
Vi
VDD = 5 V

iDS RD = 2.5 kW

VDS
VGS
Vi

VGSQ

Answer Keys

Objective & Numerical Answer Type Questions

1. B 2. B 3. D 4. C 5. C
6. C 7. – 900 8. 6 9. D 10. D
11. 57.87 12. A 13. –3 14. A 15. 0.5
16. B 17. – 48.8 18. A 19. C 20. A
21. – 5.6 22. A 23. 20.6 24. B 25. –6
26. B



Objective & Numerical Ans Type Questions : 1

(A) and R1  R2
CR
Q.1 The value of C required for sinusoidal
1
oscillations of frequency 1 kHz in the circuit (B) and R1  4 R2
of below figure is CR
1
[GATE EC 2004, IIT-Delhi] (C) and R1  R2
2CR
1kW 2.1kW
1
(D) and R1  4 R2
– 2CR
+ C Q.3 The circuit in the figure employs positive
1kW feedback and is intended to generate
sinusoidal oscillation. If at a frequency f 0 ,
1kW C
Vf ( f ) 1
B( f )   00 then to sustain
V0 ( f ) 6
1
(A) μF (B) 2π μF oscillation at the frequency, which condition
2
is satisfied?
1
(C) μF (D) 2 π 6 μF [GATE EC 2002, IISc-Bangalore]
2 6
Q.2 The circuit shown in the figure has an ideal R2
Op-Amp. The oscillation frequency and the
R1 _
condition to sustain the oscillations,
respectively, are + +
[GATE EC 2015 (Set-01), IIT-Kanpur]
V0 (t )
R1 + Network
Vf ( f ) B(f )
_ –
R2
- V0
+
(A) R2  5R1 (B) R2  6R1
2R
R C
2C R1 R1
(C) R2  (D) R2 
6 5

Cc R1 L = 10 mH
0.01 mF 10 mH 1 kW
V0

C1 = 2 pF C2 = 2 pF

R2
(A) 105 rad/sec, 2  104  Re Ce
(B) 2 10 rad/sec, 2 10 
4 4

(C) 2  104 rad/sec, 105  (A) Hartley oscillator with

(D) 105 rad/sec, 105  f oscillation  79.6 MHz
(B) Colpitts oscillator with
 Vy 
Q.5 Determine the transfer function   for f oscillation  50.3 MHz
 Vx  (C) Hartley oscillator with
the RC network shown in figure 1. f oscillation  159.2 MHz
(D) Colpitts oscillator with
f oscillation  159.2 MHz

Practice (objective & Num Ans) Questions :

Q.1 In the Wien bridge oscillator circuit shown
in figure, the bridge is balanced when
C1

R1 + VCC
+
–
R3
- VCC

C2 R2 R4

R3 R1 1 Q.4 The frequency of oscillation of the circuit

(A)  ,  shown in below figure is ______ Hz.
R4 R2 R1C1 R2C2
(Assume the Op-Amp to be ideal)
R2 C2 1
(B)  ,  R2 = 1kW R1 = 2 kW
R1 C1 R1C1R2C2
R3 R1 C2 1
(C)   , 
R4 R2 C1 R1C1 R2C2
R3 R1 C2 1 R = 1 kW
(D)   , 
R4 R2 C1 R1C1 R2C2
C = 4.7 mF
Q.2 The configuration of given figure is a
R1 R2 R = 1 kW C = 4.7 mF

R Assignment (objective & Num Ans) Questions :

C Q.1 The phase shift oscillator shown below

operate at f  80kHz . The value of
R C
resistance RF is _________ k .
RF
(A) Precision integrator
100 pF 100 pF 100 pF
(B) Hartley oscillator +
v0
(C) Butterworth high pass filter R -
(D) Wien-bridge oscillator R R
Q.3 The oscillator circuit shown in the figure is
has an ideal inverting amplifier, its
frequency of oscillation (in Hz) is Q.2 The value of C required for sinusoidal
oscillation of frequency 1 kHz in the
following circuit is ________ F .
1kW 2.1kW
C C C

R R R
+
-
C
1
(A)
(2π 6 RC ) 1kW

1
(B) 1kW
(2πRC ) C
1
(C)
( 6 RC ) . Common Data Questions 3 & 4 .
6 The Wein bridge oscillator circuit is shown
(D)
(2πRC ) in figure.

R3 Ideal
opamp

R1 = 2 kW
C1 = 0.5 mF

R2 = 100 kW C2 = 2 nF

Q.3 The frequency of oscillation of oscillator is

(A) 156 Hz (B) 256 Hz
(C) 356 Hz (D) 456 Hz
Q.4 At frequency of oscillation the feedback
factor  is____________.

Answer Keys

Objective & Numerical Answer Type Questions

1. A 2. D 3. A 4. A 5. *
6. B
Practice (Objective & Numerical Answer) Questions
1. C 2. D 3. A 4. 33.8627
Assignment (Objective & Numerical Answer) Questions
1. 236 2. 0.159 3. C 4. 0.976

Objective & Numerical Answer Type Questions

 Vy  1
5. R f  2 k, f  159 kHz,   
 Vx   SCR  3  1 
 SCR 

5V
Objective & Numerical Ans Type Questions :
RA VCC reset
Q.1 The circuit of below figure shows a 555
10 kW
Timer IC connected as an astable discharge
multivibrator. The value of the capacitor C RB out
is 10 nF. The values of the resistors RA and 10 kW trigger
VC thershold
RB for a frequency of 10 kHz and a duty
cycle of 0.75 for the output voltage C
1μF ground
waveform are
[GATE EE 2003, IIT-Madras]
VCC
If RB is shorted, the waveform at VC is

RA
(A)
Th
RB
555
Tr Timer Vout
R1 IC
C

(B)

(A) RA  3.62 k, RB  3.62 k

(B) RA  3.62 k, RB  7.25 k

(C) RA  7.25 kΩ, RB  3.62 k

(C)
(D) RA  7.25 k, RB  7.25 k
Q.2 A 555 astable multi-vibrator circuit is shown
in the figure below :
[GATE IN 2007, IIT-Kanpur]

(D) Practice (objective & Num Ans) Questions :

Q.1 IC 555 in the adjacent fig is configured as an

astable multivibrator. It is enabled to
oscillate at t  0 by applying a high input to
pin 4. The pin description is : 1 and 8 –
Q.3 An astable multi-vibrator circuit using a 555 supply; 2 – trigger; 4 – reset; 6 – threshold;
IC is given in the following figure. The 7 – discharge. The waveform appearing
frequency of oscillation is across the capacitor starting from t  0 , as
observed on a storage CRO is
[GATE IN 2006, IIT-Kharagpur]
+
VCC = 5 V

10 kW 8
8 4
7
I = 5 mA 3
6 output IC 555 3
Vth 10 kW

2 555 2, 6
4 1
Vtrig 7 C
discharge
C = 0.1μF

1 (A)

(A) 20 kHz (B) 30 k Hz

(C) 40 kHz (D) 45 kHz
Q.4 A monostable multivibrator circuit is shown
in the given figure. The value of C would be
(B)
nearly

9.1kW
4 8
6
Trigger
2 555 7
C (C)
1 5 3
V0

0.01 mF V0

t
N
thigh = 1 ms
(D)
(A) 0.001 F (B) 0.01 F
(C) 0.1 F (D) 1.0 F

(Discharge) 2
(Gnd) C 1 5
7 1
12 kW

0.01μF
(A) R1C and R2C

(B) R1C and ( R1  R2 )C

The voltage VC across the capacitor varies
(C) ( R1  R2 )C and R1C
between
(A) 3 V to 5 V (B) 3 V to 6 V (D) R2C and R1C
(C) 3.6 V to 6 V (D) 3.6 V to 5 V Assignment (objective & Num Ans) Questions :
Q.3 An IC 555 ship has been used to construct a
Q.1 The function of the diode D in the timer
pulse generator. Typical pin connections
circuit shown above is to
with components is shown below in figure
+5 V
for such an application. However it is
desired to generate a square pulse of 10 kHz. RA
4 8
VCC
7

RB
RA
4 8 D 555 3 V0
Discharge 6
Reset VCC
2
Output Trigger
IC 555 7 RB 5 1
C
CF
6
Threshold
GND 5 0.01 mF
Control (A) Increase the charging time of C
0.01 mF (B) Decreases the charging time of C
(C) Increase the discharging time of C
Evaluate values of RA and RB if the
(D) Decrease the discharging time of C
capacitor has the values of 0.01 F for the
configuration chosen. If necessary you can . Common Data Questions 2 & 3 .
suggest modifications in the external circuit The Timer-555 circuit is shown in the
configuration. figure.

C 1 0.01mF Discharge
Threshold Output V0
+
C = 15nF V
Q.2 The frequency of oscillation when –C

C  0.1F and R1  R2  5k, is Ground

Vin +
(A) 513 Hz (B) 690 Hz –

(C) 221 Hz (D) 962 Hz

Q.3 When R1  R2  5 k and f0  1.6kHz, the
value of C is __________nF.

Answer Keys

Objective & Numerical Answer Type Questions

1. C 2. A 3. B 4. C
Practice (Objective & Numerical Answer) Questions
1. B 2. B 3. 7.14 k 4. C
Assignment (Objective & Numerical Answer) Questions
1. D 2. D 3. 60.1 4. 6.06



Chapter-6 : Operational Amplifier

Objective & Numerical Answer Type Questions

1. D 2. -4 3. D 4. C 5. C
6. A 7. D 8. D 9. A 10. B
11. D 12. D 13. C,D 14. D 15. D
16. A 17. B 18. D 19. B 20. D
21. A 22. C 23. D 24. B 25. C
26. C 27. B 28. A 29. B 30. A
31. A 32. B 33. B 34. B 35. C
36. B 37. B 38. C 39. B 40. A
41. A 42. B 43. C 44. B 45. C
46. D 47. B 48. 0.6 49. 12 50. 250
51. 1 52. D 53. B 54. C 55. B
56. B 57. C 58. 1 59. D 60. A
61. B 62. B 63. A 64. D 65. C
66. A 67. B 68. B 69. C 70. A
71. B 72. C 73. D 74. C 75. B
76. C 77. C 78. 1.5 79. D 80. 0.5
81. D 82. D 83. D 84. D 85. B
86. A 87. B 88. D 89. C 90. D
91. D 92. D 93. 0.67 94. B 95. A
96. C 97. 1 98. B 99. A 100. C
101. C 102. A 103. D 104. A 105. C
106. 0.8 107. A 108. C 109. 0.635 110. A
111. D 112. 9 113. 1 114. C 115. A
116. -1 117. 100 118. D 119. A 120. A
121. D 122. D 123. C 124. A 125. A
126. A 127. D 128. A 129. A 130. A
131. A 132. C 133. B 134. C 135. D
136. D 137. A 138. D 139. D 140. D
141. B 142. D 143. B 144. A 145. 3.1 - 3.3
146. A 147. 159.15 148. D 149. A 150. 1.245
151. B 152. C 153. D 154. -1 155. A
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®
Analog Electronics [Workbook] 2 GATE ACADEMY
156. 44.37 157. 2.95 158. 15-16 159. A 160. C
161. D 162. C 163. D 164. A 165. A
166. D 167. C 168. D 169. D 170. D
171. B 172. B 173. A 174. C 175. 1.6
176. B 177. B 178. D 179. B, C 180. B
181. C 182. B 183. C 184. B 185. C
1092-
186. C 187. 188. 2.8 189. D 190. B
1094
191. 3 192. B 193. D 194. D 195. C
196. C 197. D 198. 413.8 199. 20 200. C
201. D 202. D 203. B 204. C 205. A
206. C 207. B 208. D 209. B 210. C
211. 40.4 212. D 213. A 214. C 215. D
216. B 217. A 218. B 219. D 220. B
221. B 222. 17.69 223. C 224. C 225. A
226. A 227. D 228. D 229. D 230. 10.83
231. D 232. A 233. D 234. 1.5

Chapter-7 : BJT Biasing

1. B 2. A 3. 105.14 4. 0.75 5. 93
6. C 7. C 8. B 9. A 10. B
11. 1 12. B 13. D 14. A 15. B
1.04 –
16. B 17. 2 18. A 19. 20. 0.5
1.12
21. 6 22. D 23. 3.87 24. 4.47 25. C
26. D 27. A 28. 4.1 29. D 30. B
31. 90 32. A 33. B 34. 5.33 35. C
36. C 37. A 38. B 39. 7.07 40. A
41. A

Chapter-8 : Region of BJT

1. D 2. D 3. B 4. B 5. D
6. B 7. 22 – 23 8. D 9. D 10. B
11. C 12. C 13. 0.90 14. A 15. B
16. B 17. D 18. B 19. D 20. C

Chapter-9 : Current Mirror Circuit

1. C 2. C 3. B 4. B 5. 598.67
6. 5 7. C 8. B 9. D 10. C
11. B 12. C

Chapter-10 : BJT Regulator Circuit

1. B 2. 40 – 43 3. 12 4. 8.9 5. 36.17
6. C 7. C 8. 7.6 9. 3.66

Chapter-11 : Low Frequency BJT Amplifier

1. 90.6 2. Collector 3. 1 4. A 5. A, B
6. C 7. D 8. B 9. B 10. C
11. B 12. B 13. D 14. D 15. A
16. D 17. D 18. A 19. D 20. D
– 230 to
21. A 22. C 23. 24. C 25. B
– 240
26. 0.5 27. D 28. A 29. 128 30. B
31. B 32. C 33. B 34. A 35. D
36. A 37. D 38. B 39. C 40. B
41. – 5.75 42. C 43. B 44. – 1.88 45. 10.71
46. A 47. 3 48. C 49. 1.07 50. B
51. –264.24 52. – 47.4

Chapter-12 : Feedback Amplifier

1. C 2. B 3. B 4. D 5. 1-A, 2-B
6. A 7. D 8. A 9. C 10. C
11. C 12. B 13. D 14. D 15. A
16. A 17. B 18. B 19. C 20. B
21. B 22. A 23. D 24. D 25. C
26. C 27. B 28. D 29. B 30. C
31. B 32. C 33. D



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