IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO.

10, OCTOBER 2023 3867

A Low-Complexity Sensing Scheme for

Approximate Matching Content-Addressable
Memory
Esteban Garzón , Member, IEEE, Roman Golman , Marco Lanuzza , Senior Member, IEEE,
Adam Teman , Member, IEEE, and Leonid Yavits , Member, IEEE

Abstract—The need for approximate rather than exact in various domains, including images, DNA sequencing,
search arises in numerous compare-intensive applications, from and biomedical data, there is a growing need for CAMs
networking to computational genomics. This brief presents a that can perform approximate search operations [3], [4],
novel sensing approach for approximate matching content- [5], [6]. Conventional CMOS-based or emerging resistive
addressable memory (CAM) designed to handle large Hamming memory-based CAMs typically support only exact search
distances (HDs) between the query pattern and stored data. The
operations [7], [8]. Other memory sensing schemes have been
proposed matchline sensing scheme (MLSS) employs a replica
mechanism and a 12-transistor positive feedback sense ampli- proposed [1], [2], [9], [10].
fier to effectively resolve the approximate match operation. The Several techniques have been proposed in literature to
MLSS was integrated into a 4 kB approximate CAM array and enable approximate matching in CAMs by leveraging cus-
fabricated in a 65 nm CMOS technology. With an overall area tomized sensing schemes and other solutions (i.e., involv-
footprint of 0.0048 mm2 , which includes 512 sense amplifiers and ing redundancy). For instance, error-correction codes have
the replica mechanism, the MLSS allows a flexible and dynamic been suggested for Ternary CAMs (TCAMs) and NAND-
adjustment of the HD tolerance threshold via several design vari- type CAMs, which employ parity bits and a dedicated
ables. Experimental measurements demonstrate the efficiency of matchline scheme [11], [12]. However, these methods can
our sensing scheme in tolerating very large HDs with the highest only handle a small Hamming distance (HD) of 1 to
sensitivity.
4 bits between the input query pattern and stored data,
Index Terms—HD-CAM, hamming distance, content- and their implementations require large area overhead and
addressable memory, approximate CAM, approximate match, increased design complexity. Tunable sampling time tech-
matchline sense amplifier. niques have also been explored [13]; however, their imple-
mentation is challenging due to the strong dependency on
precise device and circuit sizing, susceptibility to jitter,
I. I NTRODUCTION and higher probability of generating false results (matches
ONTENT-ADDRESSABLE memories (CAMs) are instead of mismatches and vice versa). A recent solution,
C widely used in many applications requiring high-speed
parallel search operations between an input query pattern
proposed in [14], presents a large HD-tolerant approximate
CAM (HD-CAM) based on matchline charge redistribution.
and the complete dataset stored within the memory [1], [2]. Unfortunately, the sensing scheme presented in this brief also
Due to the wide demand for similarity search in numer- suffers from a high degree of design complexity and large area
ous emerging applications such as compare-intensive big overhead.
data workloads, machine learning, and pattern recognition This brief proposes a low-complexity, scalable, and area-
efficient sensing scheme for approximate CAMs with a tunable
Manuscript received 4 April 2023; revised 22 May 2023; accepted 12 matchline discharge rate [14], [15]. Our sensing scheme con-
June 2023. Date of publication 14 June 2023; date of current version sists of a 12-transistor positive feedback sense amplifier along
25 September 2023. This work was supported in part by the European
Union’s Horizon Europe Programme for Research and Innovation under Grant with a replica mechanism that provides control of the sampling
101047160; in part by the Israeli Ministry of Science and Technology under time during approximate match operations. Specifically, the
Lise Meitner Grant for Israeli-Swedish Research Collaboration; and in part replica line enables the sensing of the sense amplifier that fur-
by the Italian Ministry of University and Research (MUR) through the Project ther resolves the compare result. Additional design variables
PRIN under Grant 2020LWPKH7. The work of Esteban Garzón was supported
by the Italian MUR under the call “Horizon Europe 2021–2027 Programme
allow adjusting the HD tolerance threshold and the sensitivity
under Grant H25F21001420001.” This brief was recommended by Associate of the proposed sensing scheme. A 4 kB HD-CAM design [14]
Editor Z. Di. (Corresponding author: Esteban Garzón.) integrating the proposed matchline sensing scheme, was fabri-
Esteban Garzón and Marco Lanuzza are with the Department of cated in a commercial 65 nm CMOS technology. The sensing
Computer Engineering, Modeling, Electronics and Systems, University of scheme of the HD-CAM design has a silicon footprint of
Calabria, 87036 Rende, Italy (e-mail: [email protected]; m.lanuzza@
dimes.unical.it). 0.0048 mm2 . The effectiveness of the suggested approximate
Roman Golman, Adam Teman, and Leonid Yavits are with the EnICS match sensing scheme (i.e., its sensitivity as a function of
Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel HD and its susceptibility to variations) is evaluated through
(e-mail: [email protected]; [email protected]; leonid.yavits@ experimental measurements.
biu.ac.il).
Color versions of one or more figures in this article are available at
This brief provides the following main contributions:
https://doi.org/10.1109/TCSII.2023.3286257. • To our knowledge, this is the first sensing scheme
Digital Object Identifier 10.1109/TCSII.2023.3286257 for approximate search CAM, enabling highly sensitive
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
3868 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO. 10, OCTOBER 2023

Fig. 1. Overview of the Hamming Distance (HD) tolerant CAM (HD-CAM) based on tunnable matchline discharge rate. (a) HD-CAM array. (b) n-bit
HD-CAM word. (c) HD-CAM cell highlighting the storage, comparison and approximate match evaluation blocks. For the sake of simplicity, wordline (WL)
is not shown in the HD-CAM cell block of (b) and (c).

approximate match sensing capabilities, that has been associative search operation involves two steps: precharge and
fabricated and evaluated in silicon. evaluation. During the precharge step, the ML is precharged
• Our sensing scheme supports a very wide range of HD to VDD by enabling the MPC transistor (PC = ‘0’). This is
tolerance through user-configurable design variables. followed by the evaluation step, where the MPC transistor is
• The proposed sensing scheme presents low susceptibility cut off (PC = ‘1’), and the query data is loaded onto the SLs.
to sampling time, temperature, and process variations. The comparison between the query pattern and the data word
• Unlike state-of-the-art matchline sensing schemes, the is performed by the M1-M3 transistors. An evaluation transis-
proposed design utilizes the charge redistribution of a tor (M4) is integrated into the HD-CAM cell to regulate the
replica line to control the sense amplifier sampling time. discharge rate of the ML according to the evaluation voltage
level (Veval ). By controlling the voltage level on M4, HD-CAM
II. BACKGROUND : H AMMING D ISTANCE T OLERANT CAM can perform approximate matching when Veval < VDD , while
The HD tolerant CAM (HD-CAM), proposed in [14], is a conventional exact match CAM operation is executed when
capable of both exact and approximate matching; the latter M4 is driven by a full voltage level, Veval = VDD .
tolerating HDs of up to 60% of the length of the query pat-
tern. HD-CAM design is based on the observation that the III. P ROPOSED M ATCHLINE S ENSING S CHEME (MLSS)
matchline voltage drop is proportional to the HD between
the query pattern and a data word. To evaluate the effi- A. Design and Operating Principle
ciency of HD-CAM approximate matching, it was tested The proposed matchline sensing scheme (MLSS) is based
as a real-time DNA classifier programmed to detect Severe on a positive feedback sense amplifier (SA) that is controlled
Acute Respiratory Syndrome Coronavirus-2 (SARS-CoV-2) by a replica line, as illustrated in Fig. 2 (a). The ML replica
DNA in a metagenomic sample (i.e., containing the DNA line (MLRL) is composed of n replica transistors (Mn−1 to
of multiple organisms). Noteworthy attributes of HD-CAM M0 ) that are connected in parallel. The gate terminals of these
include its ability to tolerate large HDs with high sensitiv- devices are grounded, their drain terminals are connected to
ity and precision, its resilience to DNA sequencing errors and VDD , and their source terminals are connected to the MLRL.
sampling time variation, and its reduced area overhead and The MLSS includes three additional transistors (MN1, MN2,
design complexity. and MP), along with an inverter (I1). MN2 and MP are con-
Fig. 1(a) shows the top-level schematic view of an m × n trolled by the PC signal. The gate of MN1 is connected to the
HD-CAM [14]. Each row in the CAM has its own matchline replica voltage (Vrep ), which in the final design is the same as
(ML), which is connected to a ML sense amplifier (MLSA). Veval (or VDD ), i.e., does not require a separate voltage source
A pair of searchlines (SLs) are connected to all the bitcells (or MN1). However, for the sake of evaluating the MLSS sus-
in a column, thereby forming an n-bit HD-CAM word, as ceptibility to sampling time variations, we enable the Vrep to be
shown in Fig. 1(b). The precharge (PC) transistor (MPC) is biased separately to adjust the MLRL discharge, as presented
used to precharge the ML. The MLSA senses the state of the hereafter.
matchline against a reference voltage (Vref ). Fig. 1(c) shows The MLRL emulates the capacitance of a ML. Its output is
the NOR-type HD-CAM bitcell, which is built upon the con- the Sen signal that timely enables the sensing of the positive
ventional NOR-type CAM bitcell [1]. Similar to a standard feedback SA. Fig. 2(b) details the schematic of the positive
six-transistor static random access memory (6T-SRAM) cell, feedback SA. It comprises a pair of cross-coupled inverters
it is based on a pair of cross-coupled inverters for storing with four enable transistors (MEN1 -MEN4 ), whose gates are
data and accessed for write and read by enabling row access driven by Sen. MEN1 (MEN2 ) acts as header (footer) to con-
through the word line (WL) and driving SL and SL to oppo- nect the latch to (down to) VDD (ground). The last two enable
site logic values for write or pre-charging them for read. The transistors, MEN3 and MEN4 , are connected to the output
GARZÓN et al.: LOW-COMPLEXITY SENSING SCHEME FOR APPROXIMATE MATCHING CAM 3869

down the MLRL discharge, which in turn delays the Sen signal
assertion. Therefore, the design variable (Vrep ) may provide an
additional level of flexibility, enabling the fine-tuning of the
sensitivity response of the approximate match.

B. MLSS in Approximate CAM Memory Array

The top-level architecture of the HD-CAM memory array,
including the MLSS and peripherals, is illustrated in Fig. 4(a).
A 32- kbit HD-CAM array, organized as 512 64-bit words,
comprises two 256×64 memory blocks. Two replica circuits
are built in the HD-CAM array: the replica row and the replica
column. The replica row has 64 transistors connected in par-
allel. Note that to balance the IR drop between the MLRL
and the 512 SAs, the MLRL is placed at the middle of the
memory array. The replica row generates the self-timed Sen
signal to control the positive feedback SAs. Every evaluation
of the SA is preceded by a precharge of the MLRL to ini-
tialize the sensing of the 512 HD-CAM words. This ensures
that the evaluation phase will start only after the precharge
to achieve a correct search operation across Process-Voltage-
Temperature (PVT) variations. The replica column serves to
synchronize the delays of the Sen signal and the SL/SL lines.
This replica column is connected to the Sen line, and com-
Fig. 2. Proposed matchline sensing scheme (MLSS) for HD tolerant CAM prises 512 delay cells connected in parallel, as shown in Fig. 4.
based on tunable matchline discharge rate. (a) Schematic of the MLSS. The delay cells represent the capacitance of the SL/SL lines
(b) schematic of the positive feedback sense amplifier. that are connected along the column of the memory cell.
The layout of the HD-CAM memory array is shown in
Fig. 4(b). The height of three rows matches the height of the
SA. Therefore, three SAs are placed next to each other in a
single row, as shown in the sub block view at the top of the
memory array. The inset shows the layout of the positive feed-
back SA, exhibiting an area footprint of 13.4 µm2 . The total
area of the MLSS including all 512 SAs, as well as the replica
row and column, is 0.0048 mm2 .

IV. E XPERIMENTAL R ESULTS

A. Test Chip and Measurement Setup
Fig. 3. Matchline sensing scheme (MLSS) behavior during search operation.
Fig. 5(a) shows the test board with the fabricated test chip,
nicknamed “LEO-II”. The layout of the fabricated chip is pro-
terminals of the cross-coupled inverters. The sources of the
vided on the right side of Fig. 5(a) with the approximate search
MEN3 and MEN4 devices are connected to Vref and ML,
CAM arrays highlighted among the various SoC components
respectively, while the drains are connected to the inverters
and other research projects integrated within the chip. Fig. 5(b)
that output MLSo and MLSo respectively.
provides the main features of the 4 mm2 chip, fabricated in
Overall, the MLSS operation is controlled by the PC signal. 65 nm CMOS technology. The SoC features the operating
When PC = ‘0’, MLRL is charged to VDD , avoiding any sens- frequency of 300 MHz at a supply voltage of 1.2 V. Fig. 5(c)
ing activity by the SA. The comparison starts when PC = ‘1’, shows our experimental setup, with an Intel Cyclone-V FPGA
enabling the MLRL to discharge through transistors MN1 and used for control and testing support during measurements.
MN2. Once the MLRL voltage level drops below the threshold
of the I1 inverter, the Sen triggers the start of the SA sam-
pling. The MEN3 and MEN4 transistors will transfer the Vref B. Methodology and Measurement Results
and ML signals to the terminals of the cross-coupled invert- Offline setup: First, we create a random dataset and store it
ers. The highest voltage level will raise a terminal to VDD , in the HD-CAM array. Second, we build a query data set,
while the other terminal will drop down to ground. The role which is the same dataset as the one stored in HD-CAM,
of the positive feedback SA is to compare the ML and Vref but overlaid with random errors at a certain predefined rate
signals. When the ML voltage level is above Vref , the SA sig- (i.e., a certain number of bit errors in random positions per
nals a match (exact or approximate). On the other hand, if memory row). The error rate defines the Hamming distance
the ML voltage falls below Vref , the SA signals a mismatch, (HD) between queries and the data stored in HD-CAM. Third,
as illustrated in Fig. 3. This figure also shows two particular the MLSS is configured by setting its HD tolerance threshold
cases: when Vrep is close to VDD and when Vrep is less than using the design variables Veval and Vref .
half VDD . These two examples are labeled as sampling time Online test: The query datawords are searched one by one in
at t1 and t2 , and correspond to approximate match and mis- the HD-CAM, and the number of matches is recorded. Since
match responses, respectively. Note that lowering Vrep slows the MLSS HD threshold is configured to tolerate said HD,
3870 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO. 10, OCTOBER 2023

Fig. 4. (a) Top-level architecture of the HD-CAM memory array along with the matchline sensing scheme and peripherals. (b) Layout of the HD-CAM
array highlighting the replica row and sense amplifiers. In the inset: the positive feedback sense amplifier layout.

Fig. 5. (a) LEO-II SoC board along with a top-level view of the SoC
layout highlighting HD-CAM, the approximate search CAM equipped with
the proposed sensing scheme. (b) Main features of the test chip. (c) Photo
of the experimental setup. For the purposes of testing and control, an Intel
Cyclone-V FPGA is connected to the prototyping board.

we expect each query to match in HD-CAM. Therefore, all

matches are true positive (TP) results, while all mismatches are Fig. 6. Measurement results of the MLSS sensitivity for different voltages
false negative (FN) ones. Using these results, we can calculate and temperature variations. Sensitivity as a function of: (a) Vref and Veval ,
the sensitivity of the MLSS as TP/(TP + FN). (b) HD for Veval = 0.6 V and Vref = 0.8 V, (c) Vref for different evaluation
Silicon measurement results of the MLSS sensitivity, for Vrep , (d) temperature. (e) Die-to-die variability box plot of sensitivity.
different Vref , Veval , and Vrep , temperature, and different sili-
con samples are provided in Fig. 6. Sensitivity as a function
of Vref is shown in Fig. 6(a) for a HD of 4 (i.e., 4 bit errors The threshold Vref (i.e., the highest Vref at which the MLSS
in random positions in each HD-CAM row). Vrep = Veval , sensitivity is still 100%) depends on Veval . The lower the Veval ,
and Veval is varied between 0.6 V and 1.0 V. For lower values the higher the threshold Vref .
of Vref , the MLSS sensitivity is 100%, meaning that MLSS Fig. 6(b) shows the MLSS sensitivity as a function of HD
tolerates the HD of 4 and correctly resolves the compare for Vref = 0.8 V and Veval = 0.6. The highest HD for which
results. With increasing Vref , the MLSS sensitivity diminishes, the MLSS sensitivity is still 100% (refer to the highlighted
meaning some matches are falsely registered as mismatches. region), marks the HD tolerance threshold of the MLSS. The
GARZÓN et al.: LOW-COMPLEXITY SENSING SCHEME FOR APPROXIMATE MATCHING CAM 3871

TABLE I
C OMPARISON B ETWEEN THE P ROPOSED D ESIGN AND OTHER P OSSIBLE S ENSING S CHEMES C OMPATIBLE W ITH H AMMING D ISTANCE CAM

higher (lower) the Veval or Vref , the lower (higher) the HD scheme exhibits high sensitivity over a wide range of HDs
tolerance threshold. between the queries and stored data. Testing results show that
We also analyze the MLSS susceptibility to sampling time the proposed design can flexibly adjust the tolerance thresh-
variation, to model which we vary the Vrep . Fig. 6(c) shows old, while exhibiting very limited susceptibility to sampling
the MLSS sensitivity as function of Vref for VDD of 1.2 V time, temperature, and process variations. The proposed design
and different Vrep values. Two sets of measurement results offers an efficient, low-complexity and robust alternative to
are shown: for Veval of 1 V and 0.6 V. For Veval of 1 V, the state-of-the-art approximate search CAM sensing approaches.
sample timing variation shows a very little effect on the MLSS
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