2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai,

INDIA

LOW POWER XOR GATE DESIGN AND ITS

APPLICATIONS
1 RAVALI.K, 4 SAKTHIVEL R
2 NAGAPURKAR RENUKA VIJAY, School of Electronics Engineering
3 SRILAKSHMI JAGGAVARAPU Associate Professor
School of Electronics Engineering VIT University, Vellore, India.
M.Tech, VLSI Design, VIT University, Vellore, India. [email protected]
[email protected]

Abstract— With advent of technology scaling, the prime designers at all levels of design along with delay and area
objective of design i.e. low power consumption can be easily considerations.
acquired. For any digital logic design the power consumption The exclusive-OR(XOR) and exclusive-NOR(XNOR) gates
depends on; Supply voltage, number of transistors incorporated are popular in microprocessors and are the basic building
in circuit and scaling ratios of the same. As CMOS technology block of many arithmetic [6] and encryption circuits especially
supports inversion logic designs; NAND & NOR structures are
circuits used for performing arithmetic operations, like full
useful for converting any logic equation into physical level design
that comprises of PMOS and NMOS transistors. In similar way, adders[5], compressors, comparators, parity checkers ,error
logic can be implemented in other styles as well, with the detectors and correctors, and adders[3] The main concern to
difference in number of transistors required. The conventional design a circuit with XOR/XNOR gates is to obtain low power
CMOS design for XOR logic can be possible with 8 or more than consumption and delay in the critical path and full output
8 transistors, with the methodology discussed in this paper, the swing with less number of transistors[4].
same design for XOR logic can be made possible with 6 With the availability of logic design techniques for designing
transistors. The proposed methodology consists of Pass transistor any logic that comprised of universal gates, leads to use of
logic and Single feedback topology. This design consumes 50% more number of transistors when inversion of inputs is
less power than that of conventional XOR logic design with
applied. The methodology used for designing the logic in this
CMOS technology. Since the design for XOR logic, is useful for
variety of applications such as Data encryption, Arithmetic paper introduces similar functionality to XOR/XNOR gates
circuits, Binary to Gray encoding etc. the XOR logic has been without any inversion of input [1]. The functionality
selected for design. The design explained in this paper is implemented can be made active with minimum of supply
simulated with Cadence 90nm technology. voltage requirements ranging from 0.6V to 3.3V, which is not
capable of switching the logic designed with CMOS
Keywords— Low Power, XOR Design, Pass Transistor Logic, technology [7][8]. The below section II Design of XOR Gate
Single feedback topology, Digital Design Techniques. with feedback technique followed by section III Applications
Introduction of designed XOR Gate, section IV Simulation Results of XOR
Gate and its Applications Design, section V conclusion and
The evolution of CMOS technology has laid down the design section VI references.
of Universal logic gates at physical level of abstraction [4].
With up gradation to CMOS; Pass transistor logic, I. EASE OF USE
Transmission gates [11], Domino logic, Ratioed and Dynamic Design of low power XOR/XNOR logic can be possible with
logic supports any design with comparable Power various logic styles [10][2] as specified with reduced VDD,
consumption, Area that comprises of number of transistors low frequency of operation, and lesser switching activity [12].
and Power supply requirements. With decrease in technology Here we are designing an XOR and XNOR circuit shown in
node, the power supply requirements also reduce to greater Fig.1 with pass transistor logic and a single feedback
extent and thereby logic design with low power availability technique without use of an inverter [1].
becomes need of time. Raising in number of transistors on In this circuit design, two cross coupled circuits are connected
chip power consumption in VLSI(very large scale by a feedback technique with the help of one PMOS transistor
integration)systems are also raised, because of Demand and and NMOS transistor, in which VDD is connected to PMOS
vogue of portable consumer electronics are making the IC transistor M4 and NMOS transistor M3 is grounded as shown
designers to aspire for high speed, high battery durability, low in Fig.1. The VDD of this circuit can be varied from 0.6V to
power chips and more reliability. If low power techniques are 3.3V. The cross coupled NMOS produce logic ‘high’ at its
not there in the circuit means it will suffer from low battery output end when both the inputs ‘a’ and ‘b’ are ‘high’. Hence,
life. Power consumption can be reduced by minimizing the gating signal is used to pass logic ‘low’ to the output of XOR
supply voltage; the designer may able to attain low power signal. Similarly, the cross coupled PMOS produce logic ‘low’
consumption but has to face tradeoff between other at its output when both the inputs ‘a’ and ‘b’ are ‘low’ and
requirements like speed and reliability [9]. Low power with the help of gating signal this can produce logic ‘high’ to
consumption is one of the important design criteria for all IC the XNOR output.

978-1-5090-4740-6/17/$31.00 ©2017 IEEE

 2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

Fig. 1. XOR Design with single feedback using pass transistor logic
TABLE I
Truth table for XOR/XNOR Logic
Inputs XOR XNOR

00 0 1

01 1 0

10 1 0

11 0 1

II. APPLICATIONS OF DESIGNED XOR GATE

A. Binary To Gray Converter:

Fig. 2. Binary to Gray Code Converter Design

The circuit shown in the Fig.1 consists of 6 transistors, in

which transistor M3 and M4 are NMOS and PMOS
transistors forming a regenerative feedback. As technology
utilized to obtain simulation results, is Cadence 90nm, which
incorporates 100nm as transistor’s minimum length and
120nm as minimum width. The NMOS aspect ratio is kept as
120nm/100nm and PMOS aspect ratio is altered 2.5 times that Code conversion is important in applications where encryption
of NMOS, so as to achieve identical flow of current in both and decryption operations get performed. Digital systems
the devices. In this circuit design threshold voltage drop is represent inputs and processed outputs in Binary format. With
eliminated from the output, i.e. when inputs a=0 and b=1 respect to combinations to be represented, Binary code
output ‘a XOR b’ is charged to VDD. Similarly for a=1 and undergoes more transition among signals as compared to Gray
b=0 the output of ‘a XOR b’ is charged to VDD. Now if any code. The Gray code is also called as Reflected Binary Code
one of the input is changing from ‘high’ to ‘low’ the output of (RBC), which was designed to prevent spurious output from
‘a XOR b’ is discharging to ‘zero’. But due to the PMOS switches. Thus the conversion from Binary to Gray can be
transistor the output of ‘a XOR b’ will discharged only to its obtained with XOR operation. In this paper, 8-bit Binary to
threshold voltage (Vtp). gray conversion is obtained.
As the circuit operates for 0.6 to 3.3V.They are
A. Under common voltage supply (above 1.8V) B : Parity Checker:
B. Less voltage supply (less than 1.8V)
Fig. 3. Parity Checker Design
A: Under common voltage supply (VDD >1.8V):
The output at ‘a XOR b’ with weak ‘0’ as shown in Table.1,
drive PMOS transistor M4, So the ‘a XNOR b’ will charge to
‘VDD’, so that transistor M3 will drive the output ‘a XOR b’
to discharge to ‘zero’. Thus, for a=0 and b=0, ‘a XOR b’
produces strong ‘0’ as shown in Table.1 and similarly for a=1
and b=1 ‘a XNOR b’ output produces a strong ‘1’.
B: For Lesser voltage supply range (VDD<1.8V):
If a=1 and b=1 the output of ‘a XOR b’ is the weak ‘0’
Since, the term Parity refers to number of 1s present in
as shown in Table.1 because of PMOS transistor which in particular stream of data. This circuit can be found useful
turn result that the PMOS transistor M4 will not turn on as irrespective of nature of code in which data is represented.
result that ‘a XNOR b’ will not charge fast. Thus the feedback When series of XOR gates are provided with Parity bit, that
circuit is not having full swing instead it has the logic with circuit functions as Parity Checker circuit. If the Parity bit is 1,
above VDD/2 and below VDD/2. even number of 1s, brings output transition and when Parity bit
So as to maintain the logical functionality the supply voltage is 0, odd number of 1s, output transition can be obtained.
is 2(Vtp) threshold voltage of PMOS transistor, the scaling of
feedback transistors must be properly done. i.e. PMOS scaling The transition in the output can be found useful so as to
will be 2.5 times that of NMOS. calculate power.

978-1-5090-4740-6/17/$31.00 ©2017 IEEE

 2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

III. SIMULATION RESULTS OF XOR GATE AND ITS Fig. 5. Simulation results of designed 8-bit Binary to Gray converter
APPLICATIONS DESIGN
Fig. 4. Simulation results of designed XOR gate.

Fig. 6. Simulation results of designed 8-bit parity checker gate.

For VDD = 1.8V, Power and Area calculation of XOR design

using various logic styles is given as below;

In this calculation, Area refers to number of transistors used

to implement the logic design and Power calculation is possible
with respect to output of logic design.

TABLE II

Power and Area Comparison (VDD = 1.8V)

No. of
Logic Style Power Dissipation
Transistors

1. CMOS 394.6uWatt 8

2. Ratioed 394.7uWatt 5

3. Dynamic 259.7uWatt 6

4. DCVSL 152.1uWatt 8

5. Pass Transistor 388.6uWatt 4

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 2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

TABLE III V. REFERENCES

Variation in Power Dissipation for designed XOR w.r.t VDD [1] Design Methodologies for High-Performance Noise-Tolerant
XOR–XNOR Circuits Sumeer Goel, Student Member, IEEE,
Sr. No. VDD Power Dissipation
Mohammed A. Elgamel, Senior Member, IEEE, Magdy A.
Bayoumi, Fellow, IEEE, and Yasser Hanafy.
[2] Rajeev kumar vimal Kant Pandey, IEEE”A New 5 Transistor
1. 0.6V 39.6 uWatt XOR-XNOR Circuit based on the pass transistor
logic”Information and communication Technologies(WICT),pp-
667-671,2011
2. 1.2V 78.9 uWatt [3] Swathi Sharma, Rajesh Mehra” Area and power Efficient Design
of XNOR-XOR Logic 65nm Technology”.
3. 1.8V 255.3 uWatt [4] K.E.Neil Weste “Principles of CMOS VLSI design: A systems
perspective”,1993.
[5] D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” in
4. 2.4V 537.1 uWatt Proc.IEEE Circuits Devices Syst., vol. 148, Feb. 2001.
[6] H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-
5. 3V 923.7 uWatt power 10-transistor full adders using XOR–XNOR gates,” IEEE
Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no.
1, pp. 25–30, Jan.2002.
[7] D. Radhakrishnan, “Design of CMOS circuits,” in Proc. IEE
With respect to methodology discussed in this paper, for Circuits Devices Syst., vol. 138, 1991, pp. 83–90.
XOR gate design using Pass transistor logic and Single [8] R. Zimmermann and W. Fichtner, “Low-power logic styles:
CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits,
feedback mechanism, requirement for number of transistors vol. 32, no.7, pp. 1079–1090, Jul. 1997.
remain the same i.e. 6. As specified, design methodology [9] Nabihah Ahamd, Rezual Hasan,IEEE “A New Design of XOR-
operates for voltage range 0.6V to 3.3V. The power XNOR gates for low power” Electronic Devices,System And
dissipation obtained for respective voltages is listed above. Application s(ICEDSA),pp-45-49,2011.
[10] W. Jyh-Ming, F.Sung-chuan, and F. Wu-Shiung,” New efficient
designs for XOR and XNOR functions on the transistor level”,
Since; Logic 1 is interpreted as Vo> VDD/2 and Logic 0 as Solid-State circuits, IEEE journals of, Vol. 29, pp. 780-786,1994.
Vo< VDD/2, There will be no change on Vo with respective [11] Lakshman, V.K.A., Sakthivel, R. Design of high performance
changes in VDD, and thereby power dissipation increases. The power efficient flip flops using transmission gates (2016)
Proceedings of IEEE International Conference on Circuit, Power
supply voltage requirement for designed logic is very low, it and Computing Technologies, ICCPCT 2016, art. no. 7530270,
starts from 0.6V, on the other side same logic implementation [12] s.w.Shiv Shankar Mishra,R.K. Nagaria and S.Tiwari.”New
with 0.6V cannot be possible with CMOS, Ratioed, Dynamic, Design Methodologies for High Speed Low Power XOR-XNOR
DCVSL, Pass transistor logic styles.

With respect to Table.2 (Power and Area Comparison for

VDD = 1.8V) the Power and area calculations have been
computed for various logic styles. The design of XOR/XNOR
is possible with all the logic styles specified, but at higher
power consumption and with larger area, when compared with
proposed structure design of XOR/XNOR logic. Therefore,
with reference to obtained results, Single feedback topology
with Pass transistor logic consumes less amount of power with
6 transistors as specified and hence it is found to be useful for
the Low Power applications.
IV. CONCLUSION
Every design with respective technology possess its own
advantages and disadvantages, thus it is necessary to combine
the topologies for betterment of design. Pass transistor logic
individually can be incorporated for XOR/XNOR design, but
for significant reduction in power, connection formed with
single feedback circuit found to be useful. The results obtained
for this particular design are shown. For applications like
‘Binary to Gray Converter’ and ‘Parity Checker’, the design is
found to be useful one. This way implemented design can also
be incorporated for various other applications wherein low
power consumption for XOR/XNOR logic is expected.

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