8086 System Bus Structure 2.

Unit II

8086 SYSTEM BUS STRUCTURE

2.1 8086 SIGNALS

(Max mode)
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3

AD12 4 37 A17/S4
AD11 5 36 A18/S5

AD10 6 35 A19/S6
AD9 7 34 BHE /S7
AD 8 8 33 MN / MX
AD7 9 32 RD (Min mode)

AD6 10 31 RQ/GT0 (HOLD)

AD5 11 8086 30 RQ/GT1 (HLDA)

AD4 12 29 LOCKI (WR)

AD3 13 28 S2 (M / IO)

AD2 14 27 S1 (DT / R)

AD1 15 26 S0 (DEN)

AD0 16 25 QS0 (ALE)

NMI 17 24 QS1 (INTA)

INTR 18 23 TEST

CLK 19 22 READY

GND 20 21 RESET

Fig.2.1. Pin Diagram of 8086

2.2 Microprocessors and Microcontrollers
A 40 pin DIP 8086 microprocessor is shown in Fig.2.1. 8086 microprocessor can operate
in two modes: Minimum mode and Maximum mode. The pins 24 to 31 have alternate functions
for every mode.
Minimum mode
MN/ MX pin is connected to +5V. Used in small systems including only one CPU.
Maximum mode
MN/ MX pin is connected to ground. Used in large systems and systems with more
than one processor.
Minimum Mode Signals:
Address/data/status
AD15 -AD0 Address/data bus Bidirectional, 3-state
A19 /S 6 -A16 /S 3 Address/status bus output,3-state
Handshaking for data read/write
RD Read from memory/IO output,3-state
READY Ready signal input
M/ IO Select memory or IO output,3-state
WR Write to memory/IO output,3-state
ALE Address latch enable output
DT/ R Data transmit/receive output
DEN Data bus enable output
BHE /S 7 Bus high enable output
Interrupt signals
INTR Interrupt request input
NMI Non-maskable interrupt input
RESET Reset input
INTA Interrupt acknowledge output
Bus access control
HOLD Hold request input
HLDA Hold acknowledge output
Others
TEST Test pin tested by WAIT instruction input
MN/ MX Minimum/maximum mode, 5V input
CLK Clock pin for basic timing signal input
VCC Power supply, +5 V
GND Ground connection, 0V
8086 System Bus Structure 2.3
Maximum Mode Signals:
Address/data/status
AD15 -AD0 Address/data bus Bidirectional, 3-state
A19 /S 6 -A16 /S 3 Address/status bus output,3-state
Handshaking for data read/write
RD Read from memory/IO output,3-state
READY Ready signal input
BHE /S 7 Bus high enable output
S2 , S1 , S0 Status/handshake bits indicating the
function of the current bus cycle output
Interrupt signals
INTR Interrupt request input
NMI Non-maskable interrupt input
RESET Reset input
Bus access control
RQ / GT1 , RQ/GT0 Request/grant pins for bus access bidirectional
LOCK Used to lock the bus, activated by output
LOCK prefix on any instruction
Others
QS 1 ,QS0 Queue status output
TEST Test pin tested by WAIT instruction input
MN/ MX Minimum/maximum mode, 0V input
CLK Clock pin for basic timing signal input
VCC Power supply, +5 V
GND Ground connection, 0V

2.1.1 Address / Data Bus (AD15–AD0)

The multiplexed Address/ Data bus acts as address bus during the first part of machine
cycle (T1) and data bus for the remaining part of the machine cycle.
2.1.2 Address/Status (A19/S6, A18/S5, A17/S4, A16/S3)
During T1 these are the four most significant address lines for memory operations.
During I/O operations these lines are LOW. During memory and I/O operations, status
information is available on these lines during T2, T3, T WAIT, T4. The status of the interrupt
 2.4 Microprocessors and Microcontrollers
enable FLAG bit (S 5 ) is updated at the beginning of each CLK cycle. Function of status bits
S 3 and S 4 as shown below:
S4 S3 Function

0 0 ES, Extra segment

0 1 SS, Stack Segment
1 0 CS, Code segment
1 1 DS, Data segment

2.1.3 Bus High Enable/Status ( BHE /S7)

During T1 the bus high enable signal ( BHE ) should be used to enable data onto the
most significant half of the data bus, pins D 15 ±D8 .
BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a
byte is to be transferred on the high portion of the bus. The S 7 status information is available
during T2, T3, and T4.

BHE A0 Characteristics
0 0 Whole word
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even address
1 1 None

2.1.4 Read ( RD )
This signal is used to read data from memory or I/O device which reside on the 8086
local bus.
2.1.5 Ready
If this signal is low the 8086 enters into WAIT state. The READY signal from memory/IO
is synchronized by the 8284A clock generator to form READY. This signal is active HIGH.
2.1.6 Interrupt Request (INTR)
It is a level triggered maskable interrupt request. A subroutine is vectored via an
interrupt vector lookup table located in system memory. It can be internally masked by
software resetting the interrupt enable bit. INTR is internally synchronized. This signal is
active HIGH.

2.1.7 TEST
This input is examined by the “Wait” instruction. If the TEST input is LOW execution
continues, otherwise the processor waits in an ``Idle’’ state. This input is synchronized
internally during each clock cycle on the leading edge of CLK.
8086 System Bus Structure 2.5
2.1.8 Non-Maskable Interrupt (NMI)
It is an edge triggered input which causes a type 2 interrupt. NMI is not maskable
internally by software. A transition from LOW to HIGH initiates the interrupt at the end of
the current instruction.
2.1.9 Reset
This signal is used to reset the 8086. It causes the processor to immediately terminate
its present activity. The signal must be active HIGH for at least four clock cycles. It restarts
execution when RESET returns LOW.
2.1.10 Clock (CLK)
This signal provides the basic timing for the processor and bus controller. The clock
frequency may be 5 MHz or 8 MHz or 10 MHz depending on the version of 8086.
2.1.11 VCC
It is a +5V power supply pin.
2.1.12 Ground (GND)
Two pins (1 and 20) are connected to ground ie, 0 V power supply.

2.1.13 Minimum/Maximum (MN/ MX )

This pin indicates what mode the processor is to operate in. The 8086 can be configured
in either minimum mode or maximum mode using this pin.
2.1.14 Minimum Mode Signals
MEMORY / IO (M/ IO )
It is used to distinguish a memory access from an I/O access. M = HIGH, I/O = LOW.
WRITE( WR )
It indicates that the processor is performing a write memory or write I/O cycle,
depending on the state of the M/ IO signal.
Interrupt Acknowledge ( INTA )
This signal indicates recognition of an interrupt request. It is used as a read strobe for
interrupt acknowledge cycles.
Address Latch Enable (ALE)
This signal is used to demultiplex the AD0 -AD15 into A0 -A15 and D0 -D15 . It is a HIGH
pulse active during T1 of any bus cycle.
Data Transmit/Receive (DT/ R )
This signal desires to use a data bus transceiver (8286/8287). It is used to control the
direction of data flow through the transceiver. A high signal on this pin indicates that 8086 is
transmitting the data and low indicates that 8086 is receiving the data.
 2.6 Microprocessors and Microcontrollers

Data Enable( DEN )

This signal informs the transceivers (8286/8287) that the 8086 is ready to send or
receive data.
Hold
This signal indicates that another master (DMA or processor) is requesting the host
8086 to handover the system bus.
Hold Acknowledge (HLDA)
On receiving HOLD signal 8086 outputs HLDA signal HIGH as an acknowledgement.
2.1.15 Maximum Mode Signals
Maximum mode operation differs from minimum mode in that some of the control
signals must be externally generated. This requires additional circuitry, however, a chip -the
8288 bus controller- designed for this purpose is available.

Status ( S 2 , S 1 , S 0 )

These three status signals indicate the type of machine cycle used. These status lines
are encoded as shown below:

S2 S1 S0 Machine cycle
0 0 0 Interrupt acknowledge
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive

Request/Grant ( RQ / GT0 , RQ / GT1 )

These pins are used by other local bus masters to force RQ / GT1 the processor to
release the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional
with RQ / GT0 having higher priority than RQ / GT1 .
8086 System Bus Structure 2.7
LOCK
This signal indicates that other system bus masters are not to gain control of the system
bus while LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix
instruction and remains active until the completion of the next instruction. This signal is
active LOW.
Queue Status (QS 1 , QS 0 )
The queue status is valid during the CLK cycle after which the queue operation is
performed. QS1 and QS0 provide status to allow external tracking of the internal 8086
instruction queue.

QS 1 QS 0 Characteristics

0 0 No operation
0 1 First byte of opcode from Queue
1 0 Empty the Queue
1 1 Subsequent byte from Queue

2.2 SYSTEM BUS STRUCTURE

Microprocessor is processing device of every computing device. It needs to
communicate with outer world. It needs to communicate with input devices to get data, it
needs to communicate with memory to process data according to instructions written in
memory and finally it needs to communicate with output devices to display the output on
output devices. To communicate with external world, microprocessor make use of buses.

System bus is a single computer bus that connects the major components of a computer
system. It consists of data bus, address bus and control bus. Figure 2.2 illustrates the
fundamental system bus architecture.

(i) Data Bus

l It is used for the exchange of data between the processor, memory and peripherals.

l It is bi-directional so that it allows data flow in both directions.

l The width of the data bus can differ for every microprocessor.

l When the microprocessor issues the address of the instruction, it gets back the
instruction through the data bus.

l When it issues the address of the data, it loads the data through the data bus.
 2.8 Microprocessors and Microcontrollers
(ii) Address Bus
l The address bus contains the connections between the microprocessor and memory
or output devices that carry the signals relating to the addresses which the CPU is
processing at that time, such as the locations that the CPU is reading from or
writing to.
l It is unidirectional.
l The width of the address bus corresponds to the maximum addressing capacity of
the bus, or the largest address within memory that the bus can work with.
l Maximum address capacity = 2 n (n=address lines).
l Address bus may be multiplexed with data bus.
(iii) Control Bus
l The control bus carries the signals relating to the control and coordination of the
various activities across the computer, which can be sent from the control
unit within the CPU.
l Microprocessor uses control bus to process data, that is what to do with the selected
memory location.
l Various operations are performed by microprocessor with the help of control bus.
l This is a dedicated bus, because all timing signals are generated according to
control signal
l Some control signals are Read, Write and Opcode fetch etc.

CPU
ALU Input and
Memory
Registers Output
and Controls

Data Bus
System Bus

Address Bus

Control Bus

Fig. 2.2. System bus architecture

8086 System Bus Structure 2.9
2.3 MIN-MAX MODE OF OPERATION
l Intel 8086 has two modes of operation. They are:
i. Minimum mode
ii. Maximum mode
l When only 8086 microprocessor is to be used in a microcomputer system, the 8086 is
used in the minimum mode of operation. In this mode, the microprocessor issues the
control signals required by memory or I/O devices.
l In a multiprocessor system it operates in the maximum mode. In this mode, the control
signals are issued by Intel 8288 bus controller.
l The pin MN/ MX (33) decides the operating mode of 8086.
l When MN/ MX = 0, maximum mode of operation.
= 1, minimum mode of operation.
l Pins 24 to 31 have different functions for minimum mode and maximum mode.
2.3.1 Minimum Mode
l For minimum mode of operation MN/ MX is connected to VCC (+5 volts).
l All control signals for controlling memory and I/O devices are generated inside the
8086 microprocessor.
l Pins 24 to 31 have the following functions:
Pin 24 = INTA (Interrupt Acknowledge)
Pin 25 = ALE (Address Latch Enable)
Pin 26 = DEN (Data Enable)
Pin 27 = DT/ R (Data Transmit / Receive)
Pin 28 = M/ IO (Memory or I/O)
Pin 29 = WR (Write)
Pin 30 = HLDA (HOLD Acknowledge)
Pin 31 = HOLD (Hold)
l In this mode , peripheral devices can be used with the microprocessor without any
special consideration.
l A single 8086 is in this mode. The remaining components in this mode are,
Latches (8282) –3 numbers
2.10 Microprocessors and Microcontrollers
Transceivers (8286) – 2 numbers
Clock generator (8284)
Memory or I/O devices.
l The 8086 has multiplexed address/data signals and address / status signals. Latches
are used for demultiplexing and these latches are enabled by using the ALE signal. 3
numbers of latches (Intel 8282/8283) are used as address latches.
l The data bus should be provided with data transceivers to drive the data on the bus.
Transceivers are controlled by two signals: DEN , DT/ R .
l The signal DEN is used as an output enable signal.
l The signal DT/ R is used as direction control. It indicates that valid data is available
on the data bus which indicates the direction of data ie, from or to the processor.
l Two numbers octal bus transceivers (Intel 8286/ 8287) are used as data transceivers.
l A clock generator generates the clock from the crystal oscillator and then shapes it and
divides to make it more precise so that it can be used as an accurate timing reference
for the system. The clock generator (Intel 8284) does the following functions:
i. Clock generation
ii. RESET synchronization
iii. READY synchronization
iv. Peripheral clock generation
A quartz crystal of frequency 15 MHz is connected to X 1 and X2 of 8284.
The status of M/ IO , RD and WR signals decides the type of data transfer as shown
in Table 2.1.
Table 2.1 Read / Write operation
M/ IO RD WR Operation

0 0 1 I/O Read
0 1 0 I/O Write
1 0 1 Memory Read
1 1 0 Memory Write

l HOLD and HLDA signals are used to interface other bus masters like DMA controller.
l INTA (Interrupt Acknowledge) signal is issued by the microprocessor on receiving
any interrupt signal. Fig. 2.3 shows the minimum mode 8086 system.
8086 System Bus Structure 2.11
Crystal Vcc
Oscillator

CLK MN/MX RD
RESET WR
M/IO RAM

EPROM
From Interrupt
Controller INTR STB Address I/O Devices
ALE Interrupt
OE
To Interrupt GND 8282 Controller
Controller INTA Latch
BHE
2 or 3
From DMA INTEL
HOLD
Controller 8086
To DMA CPU
Controller HLDA

8286 Data
Transceiver
DT/R T (2)

DEN OE

Fig. 2.3. Intel 8086 based computer system in minimum mode

2.3.1.1 Minimum Mode Bus Cycle

The timing diagram for Read cycle is shown in Fig.2.4 and Write cycle is shown in
Fig.2.5.
One Bus Cycle

T1 T2 T3 T4
CLK
Address, BHE OUT
A19/S6–A16/S3
and BHE/S 7 Status OUT

AD15–AD 0 Address OUT Data IN

ALE

M/IO LOW = I/O Read, HIGH = Memory Read

RD

DT/R

DEN

Fig. 2.4. Minimum Mode – Read Cycle

2.12 Microprocessors and Microcontrollers

One Bus Cycle

T1 T2 T3 T4
CLK
Address, BHE OUT
A19/S6–A16/S3
and BHE/S 7 Status OUT

AD15–AD0 Address OUT Data IN

ALE

M/IO LOW = I/O Write, HIGH = Memory Write

WR

DT/R

DEN

Fig. 2.5. Minimum Mode Write Cycle

Read Operation :
l The Read cycle begins in T 1 with the assertion of the address latch enable (ALE)
signal and also M/ IO signal. During the negative going edge of this signal, the valid
address is latched on this bus.
l The BHE and A0 Signals address low, high or both bytes. From T 1 to T 4 the M/ IO
signal indicates memory or I/O operation. At T 2 , the address is removed from the bus
and is sent to the output. The bus is then tristated.
l The RD signal is activated in T 2 . This signal causes the addressed device to enable its
data bus drivers.
l After RD goes low, the valid data is available on the data bus. After the data is accepted
by the processor, RD is raised high at the beginning of T 4 .
l At T 2 DEN is lowered to enable transceiver. At T 4 DEN is raised to disable the
transceiver.
8086 System Bus Structure 2.13
Write Operation

l The Write cycle begins in T 1 with the assertion of the ALE signal. The M/ IO signal is
asserted to indicate a memory or I/O operation.
l At T 2 , after sending the address in T 1 , the processor sends the data to be written to the
addressed location.
l The data on the bus remains until middle of T 4 state.
l The WR signal becomes active at the beginning of T 2 .

l The BHE and A0 signals are used to select the proper type of memory or I/O to be read
or written.

At T 2 DEN is lowered to enable transceiver. At T 4 it is raised to disable the transceiver.

2.3.2 Maximum Mode
l For maximum mode of operation MN/ MX pin is grounded. Fig. 2.6 shows the
maximum mode 8086 system.
l Pins 24 to 31 have the following functions:
Pins 24 & 25 : QS1, QS0 (Instruction Queue Status)

Pins 26, 27 & 28 : S0 , S1 , S2 (Status signals)

Pin 29 : LOCK

Pin 30 & 31 : RQ / GT1 , RQ / GT0 (Request / Grant)

l Request / Grant lines are used for local bus priority control. Other processors ask the
CPU through these lines to release the local bus. The BHE – A0 characteristics for
these lines are shown in Table 2.2

Table 2.2 BHE –A0 characteristics

RQ/GT BHE A0 Operation

RQ / GT 0 0 0 Word transfer

RQ / GT 0 0 1 Upper byte transfer from/to odd address

RQ / GT1 1 0 Lower byte transfer from/to even address

RQ / GT1 1 1 None
2.14 Microprocessors and Microcontrollers

Crystal GND
Oscillator

S0 MRDC
CLK MN/MX S0
S1 8288 MWTC
RESET S1
BUS IORC
S2 RAM
S2 Controller
IOWC
NC AMWC EPROM
INTA
DEN I/O Devices
LOCK AIOWC
DT/R Interrupt
ALE Controller
NC
RQ / GT1

INTEL Address Bus

DMA
RQ / GT2 STB
8086 OE Controller
CPU 8282
INTR BHE Latch
2 or 3
AD0–AD15
A16–A19

T Data Bus
OE
8286
Transceiver
(2)

Fig. 2.6. Intel 8086 based computer system in maximum mode

l In maximum mode 8086 based system, an external Bus Controller (Intel 8288) has to
be employed to generate the bus control signals.

l The important signals are :

MRDC - Memory Read Command

MWTC - Memory Write Command

IORC - I/O Read Command

IOWC - I/O Write Command

AMWC - Advanced Memory Write Command

AIOWC - Advanced I/O Write Command

The advanced signals ( AMWC , AIOWC ) are activated one clock pulse earlier. This
give slow interfaces an extra clock cycle to prepare the input data.
8086 System Bus Structure 2.15
l Three numbers of 8 bit latches (Intel 8282) are employed to demultiplex the address
lines. The latches are enabled by using the ALE signal generated by the bus controller.

l Two numbers of octal bus transceivers (Intel 8286) are used as data transceivers. The
signals DEN and DT/ R are generated by the bus controller are used as enable and
direction control respectively.

l The clock generator (Intel 8284) is used to generate clock, reset and ready signals for
8086. A quartz crystal of frequency 15 MHz is connected to 8284.

2.3.2.1 Maximum Mode Bus Cycle

The timing diagram for Read cycle is shown in Fig.2.7 and Write cycle is shown in
Fig.2.8.

One Bus Cycle

T1 T2 T3 T4
CLK
S2–S0
S2–S0 S2–S0 Inactive
BHE, A19–A16
Address/Status Float
and BHE/S7 S7–S3
Data IN D15–D0
Address/data
AD15–AD0 A15–A0

*ALE
*MRDC
or IORC

*DT/R

*DEN

*8288 Bus Controller Outputs

Fig.2.7. Maximum Mode – Read Cycle

2.16 Microprocessors and Microcontrollers

One Bus Cycle

T1 T2 T3 T4
CLK
S2–S0
S2–S0 S2–S0 Inactive
BHE, A19–A16
Address/Status Float
and BHE/S S7–S3
Data IN D15–D0
Address/data
AD15–AD0 A15–A0

*ALE
*AMWC
or AIOWC
*MWTC
or IOWC

*DEN

*8288 Bus Controller Outputs

Fig. 2.8. Maximum Mode – Write Cycle

l The status signals S2 , S1 and S0 are set at the begining of bus cycle. When
S2 = S1 = S0 =1, (inactive-passive), the bus controller will output a pulse on its ALE
and apply a required signal to its DT/ R pin at T 1 .

l At T 2 , the bus controller will set DEN = 1, therefore transceiver is enabled. For an
input, bus controller will activate MRDC or IORC . These signals are activated until
T 4 . For an output, it will activate AMWC or AIOWC . These signals are activated
from T 2 to T 4 and MWTC or IOWC is activated from T 3 to T 4 .

l The status signals S2 , S1 and S0 are remain active during T 1 and T 2 and become
inactive during T 3 and T 4 .

2.4 SYSTEM DESIGN USING 8086

The system design starts with specifications. The specification of the system includes
the following:
1. I/O devices
2. Memory requirement
8086 System Bus Structure 2.17
3. System clock frequency
4. Peripheral devices required
5. Application
1. I/O devices
The popular input device used in single board microcomputer system is 8279 - keyboard
and display controller.
The popular output devices are,
LED display
LCD
Printer
Floppy disk / CD
CRT terminal
Intel 8279 is used for LED display. The LCD and printer are interfaced using ports.
Intel 8272 or 82072 floppy disk controller and Intel 8275 CRT controller are popularly used
in 8086 system.
2. Memory requirement
The memory of the system is splitted between EPROM and RAM. The memory capacity
of EPROM and RAM are estimated based on the applications and work to be performed. The
popular EPROM used in 8086 based system are 2708 (1K x 8), 2716 (2K x 8), 2732 (4K x 8),
2764 (8K x 8) and 27256 (32K x 8). The popular static RAM used in 8086 based system are
6208 (1K x 8), 6216 (2K x 8), 6232 (4K x 8), 6264 (8K x 8) and 62256 (32 K x 8).
3. System clock frequency
The 8086 does not have an internal clock circuit. Hence clock has to be supplied from
an external device. The Intel 8284 clock generator is employed to generate the clock. An
external quartz crystal has to be connected to 8284 to generate the clock signal. The frequency
of quartz crystal should be thrice the internal clock frequency of 8086.
4. Peripheral devices
The peripheral devices required for a system depends on its applications. Some of the
peripheral devices that can be interfaced to 8086 based system are,
H Intel 8253 - Programmable Interval Timer
2.18 Microprocessors and Microcontrollers

H Intel 8251 - USART

H Intel 8255 - Programmable Peripheral Interface
H Intel 8279 - Keyboard / Display controller
H Intel 8257 - DMA controller
H ADC, DAC etc.
5. Application
The specifications of the microprocessor itself depends on the applications for the
proposed system and the nature of work. The I/O device, memory, peripheral device are all
depends on the nature of work to be performed by the system.

2.5 MINIMUM MODE SYSTEM CONFIGURATION

The design example for minimum mode system configuration is given here with the
following features.
i. 8086 in minimum mode
ii. 64 K Byte EPROM
iii. 64 K Byte RAM
Solution :
1. Whenever the 8086 is reset, its value is set to FFFF H and IP value is set to 0000H.
This corresponds to physical address FFFF0 H.
Now 64 K byte EPROM is to be interfaced with 8086.
64 K Bytes means FFFF H bytes. Hence the EPROM memory should start from,
FFFFF – FFFF = F0000 H
Of the 64 K bytes, 32 K bytes will be at EVEN address and 32 K bytes will be at ODD
address. Hence two EPROM chips (27256) are needed, each of 32 K bytes capacity-
one for storing bytes at EVEN address and other for storing ODD address bytes.
EPROM address range = F0000H to FFFFF H
EVEN address starts at F0000H and
ODD address starts at F0001 H
2. To address 32 K bytes, 15 address lines are needed.
32K = 32 x 1024 = 32768 = 2 15
8086 System Bus Structure 2.19
3. Each EPROM chip (27256) has a chip select CS , input. When this input is asserted
low, the addressed byte in a device will be output on the data bus. The decoder
(74LS138) makes sure that the CS input of only one EPROM device at a time is low..
4. If the decoder (74LS138) is enabled by making its G1 and G 2 inputs low and its G1
input high, then only one output of the device will be low at a time. Address line A16
is connected to the G1 .
5. The output that will be low is determined by the 3 bit address applied to the C, B and
A select inputs.
If ABC = A19 A18 A17 = 111, then the Y7 output will be low and all the other outputs
will be high. This will assert the CS input to EPROM
If ABC = A19 A18 A17 = 001, then the Y1 output will be low and RAM will be
selected.

+Vcc

A19 A G1 Y0
A18 B Y1 To RAM
A17 C
Y2

Y3
Y4
A16 G1 Y5
RD G2 Y6
Y7 To EPROM
74LS138

Fig.2.9. Decoder

6. As 32 K bytes EPROM and RAM need 15 address lines, A1 to A15 lines are used. A0
and BHE are used to select even and odd memory banks respectively..
7. RAM address range = 00000H – 0FFFF H
EVEN address starts at 00000 H and
ODD address starts at 00001 H
Fig. 2.10 shows the interface between 8086 and EPROM, RAM memory chips and
Table 2.3 shows the address for memory chips.
 2.20
AD15 A0
AD0 A15
ALE
D0
8086 D15

G1 MEMR
RD A MEMW
WR B IOR
M/IO C IOW
G1 G2

OE D8–D8 A1 –A15 OE D0–D7 A1–A15 OE D8–D15 A1–A15 OE D0–D7 A1–A15

Clock Generator Vcc EPROM (27256) EPROM (27256) RAM (62256) RAM (62256)
8284A CS CS CS CS
Vcc G1
A19

Microprocessors and Microcontrollers

A18
A17 Y7
A16 A0 A0
BHE Y1
74LS373

Fig.2.10. Interfacing 64 k RAM and 64 k EPROM with 8086 in minimum mode

 8086 System Bus Structure
Table 2.3. Memory Map

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hex
Address Memory

1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0000H Even
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFFEH EPROM 1

0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F0001H Odd
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH EPROM 2

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H Even
1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0FFFEH RAM 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H Odd
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0FFFFH RAM 2

2.21
2.22 Microprocessors and Microcontrollers
2.6 MAXIMUM MODE SYSTEM CONFIGURATION
A design example for maximum mode system configuration is given here with the
following features.
i. 8086 CPU working at 4.77 MHz
ii. 8087 Math Co-processor is connected
iii. 64 kB of EPROM for storing the system software
iv. 64 k B of RAM
Solution :
1. Since a math co-processor is to be connected, 8086 should be in Maximum Mode.
2. To get 8086 working at 4.77 MHz, 8284A clock generator with oscillator is to be
connected.
3. Two numbers of 32 KB EPROM (EVEN and ODD)
Two numbers of 32 KB RAM (EVEN and ODD)
For 32 KB EPROM/RAM, 15 address lines are used (2 15 = 32 KB)
Address lines = A1 –A15
A0 and BHE are used to select EVEN and ODD memory banks respectively..
4. EPROM address range = F0000 H to FFFFF H
EVEN address starts at F0000 H and ends at FFFFE H
ODD address starts at F0001 H and ends at FFFFF H
5. RAM address range = 00000 H to 0FFFF H
EVEN address starts at 00000 H and ends at 0FFFEH
ODD address starts at 00001 H and ends at 0FFFF H
6 In maximum mode the following signals are decoded externally using bus controller
(8288) :

DT/ R - Data Transmit / Receive

DEN - Data Enable
ALE - Address Latch Enable
MRDC - Memory Read Control

MWTC - Memory Write Control

IORC - I/O Read Control
IOWC - I/O Write Control
8086 System Bus Structure 2.23
2.7 MEMORY AND I/O INTERFACING IN 8086 BASED SYSTEM
The 8086 based system design example for memory and I/O interface with 16 kB
EPROM and 16 kB RAM is given. The system require 8279 for Keyboard/Display interface
and 8255 for I/O ports.
Solution :
The 16 kB EPROM is implemented in 2 x 8 kB. One of the 8 kB EPROM is mapped as
even bank and other as odd bank. The address lines A1 –A13 are connected to each EPROM IC
(2764) to select internal locations of EPROM.
The 16 kB RAM is implemented in 2 x 8 kB. One of the 8 KB RAM is mapped as even
bank and other as odd bank. The address lines A1 –A13 are connected to each RAM IC (6264)
to select the internal locations of RAM.
The memory and I/O interface in 8086 is shown in Fig. 2.11. The address line A1 of
8086 is connected to address line A0 of 8279 and the address lines A1 and A2 of 8086 are
connected to address lines A0 and A1 of 8255 to provide the required internal addresses. 2 to
4 decoders are used to generate CS signals. A18 and A19 as input and each decoder produce
four decoded output signals. One of decoder is enabled by address line A0 and the ouput of
this decoder are used as CS signal for even bank memory ICs 8279 and 8255. The other
decoder is enabled by the control signal BHE and the output of this decoder are used as CS
signals for odd bank memory ICs. The addresses allotted to memory and I/O devices are
shown in Table 2.4.
2.8. I/O PROGRAMMING
I/O programming discuss the ways in which information can be trasferred between
input-output devices or mass storage devices and the CPU or memory. The three modes of
transfer of device data,commands and status are,
(i) Programmed I/O
(ii) Interrupt driven I/O
(iii) DMA transfer
Programmed I/O : The program determines which interfaces need servicing bt testing
the ready bits in their status registers. Programmed testing of ready bits or signals is known
as polling.
Interrupt driven I/O: An external interrupt is sent to the CPU from the interface when
the interface has data to input or is ready to accept data and the I/O operation is performed
by an interrupt routine.
 2.24
D0–D1

A0–A19
Latches

WR

WR

WR

WR
8086 and

A1–A13

A1–A13
D8–D13

A1–A2
A1–A13

A1–A13
D8–D15

D0–D7

D0–D7

D0–D7
D0–D7
Buffers

RD

RD

RD

RD
A1
RD

RD
I/O0–I/O7

I/O0–I/O7
A0–A12

A0–A12

A0–A12

A0–A12

D0–D7

D0–D7
O0–O7
BHE

O0–O7

A0–A1
A0

WR

WR
WE

WE
OE

OE

OE

OE

RD

RD
RD WR

8 kB 8 kB 8 kB 8 kB 8279 8255
RAM EPROM RAM EPROM
6264 2764 6264 2764
Odd Odd Even Even
CS CS CS CS CS CS

A18
A OBCS0
Y0
2-to-4 Decoder
A19 OBCS1
B Y1
OBCS2
Y2
BHE OBCS3

Microprocessors and Microcontrollers

E Y3

EBCS0
A18 Y0
A
2-to-4 Decoder

A19 EBCS1
B Y1
EBCS2
Y2
A0
E EBCS3
Y3

Fig. 2.11. Memory and I/O interface in 8086

 8086 System Bus Structure
Table 2.4. Address location

Binary Address
Device Decoder Unused Input To Memory/IO Device Hexa
Input Address Lines Address Pins Address
A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A7 A6 A5 A4 A3 A2 A1 A0
8 KB RAM 0 0 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000
Memory 0 0 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00002
Even 0 . 0 x . x x x 0 . 0 0 . 0 0 0 0 . 0 0 0 0 . 1 0 0 00004

RAM Address Range

..

00000H to 03FFFH
. . . . . .
. . . . . . .
0 0 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 0 03FFE
8 KB RAM 0 0 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001
Memory 0 0 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00003
Odd 0 . 0 x . x x . x 0 0 0 0 . 0 0 0 0. 0 0 0 1. 0 1 00005
..
. . . . . . .
. . . . . .
0 0 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 03FFF
8 KB 1 1 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC000
EPROM 1 1 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 FC002

EPROM Address Range

Memory 1 . 1 x . x x . x 0 0 0 0 . 0 0 0 0. 0 0 0 1. 0 0 FC004

FC000H to EFFFFH
. . . . . ..
Even . . . . . . .
.
1 1 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FC00E
8 KB 1 1 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 1 FC001
EPROM 1 1 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 FC003
Memory 1 . 1 x . x x . x 0 0 0 0 . 0 0 0 0. 0 0 0 1. 0 1 FC001
Odd . . . . . .
. . . . . .
1 1 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFF
8279
Data
Register 0 1 x x x x x x x x x x x x x x x x 0 0 40000
Control
Register 0 1 x x x x x x x x x x x x x x x x 1 0 40002
8255
Port-A 1 0 x x x x x x x x x x x x x x x 0 0 0 80000
Port-B 1 0 x x x x x x x x x x x x x x x 0 1 0 80002
Port-C 1 0 x x x x x x x x x x x x x x x 1 0 0 80004
Control
Register 1 0 x x x x x x x x x x x x x x x 1 1 0 80006

2.25
2.26 Microprocessors and Microcontrollers
DMA transfer: The interface requests the use of the bus by sending a signal through
the control line and makes the necessary transfer without the help of the CPU.
2.8.1 PROGRAMMED I/O
Programmed I/O consists of continually examining the status of an interface and
performing an I/O operation with the interface when its status indicates that it has data to be
input or its data-out buffer register is ready to receive data from the CPU.
(i) Read input in programmed I/O mode
Each input is read after first testing whether the device is ready with the input (a state
reflected by a bit in a status register) or whether the device input buffer is not empty. The
program waits for the ready status by repeatedly testing the status bit and till all targeted
bytes are read from the input device. The program is in busy state only after the device gets
ready else in wait state. Fig.2.12 illustrates the input read by the processor in programmed
I/O mode.

Next step of the

Program program

1 No
2 Yes
Read status bit and 3
test whether the Yes
device is ready Read bytes Test more bytes
with the data to be read

Input Not
Ready
4

Wait for a period

Fig. 2.12. Input read by the processor in programmed I/O mode

(ii) Output write in programmed I/O mode

Each output written after first testing whether the device is ready to accept the bytes at
its output register or output buffer is empty. The program waits for the ready status by
repeatedly testing the status bit and till all the targeted bytes are written to the device. The
program in busy state only after the device gets ready else wait state.
8086 System Bus Structure 2.27

Next step pf the

Program program

1
No
2 Yes
3
Read status bit and
test whether the Yes Test more bytes
device is ready Write bytes
to be written

Output buffer
Not Full
4

Wait for a period

Fig. 2.13. Output write in Programmed I/O mode

2.8.2 Interrupt driven I/O

There are several ways of combining with interrupt I/O, some involving only software,
some only hardware, and some a combination of the two. They are,
i.) Polling
ii.) Daisy chaining
iii.) Interrupt priority management hardware
(i) Polling
Polling is the most common and simplest method of I/O control. It requires no special
hardware and all I/O transfers are controlled by the CPU programme. Polling is a synchronous
mechanism, by which devices are serviced in sequential order.
Polling is constantly testing a port to see if data is available. i.e, the CPU polls (asks)
the port if it has data available or if it is capable of accepting data. Polling notifies the part
of the computer containing the I/O interface that a device is ready to be read or otherwise
handled but does not indicate which device. The interrupt controller must poll (send a signal
out to) each device to determine which one made the request.
The polling technique has the following limitations:
1. It is wasteful of the processors time, as it needlessly checks the status of all
devices all the time.
2.28 Microprocessors and Microcontrollers
2. It is inherently slow, as it checks the status of all I/O devices before it comes
back to check any given once again.
3. When fast devices are connected to a system, polling may simply not be fast
enough to satisfy the minimum service requirements,
4. Priority of the device is determined by the order in the polling loop, but it is
possible to change it via software.
(ii) Daisy chaining
It is a simple hardware means of attaining a priority scheme. It consists of associating
a logic circuit with each interface and passing the interrupt acknowledge signal through
these circuits as shown in Fig.2.14. The priority of an interface is determined by its position
on the daisy chain. The closer it is to the CPU the higher its priority.
This is significantly faster than a pure software approach. A daisy chain is used to
identify the device requesting service.
Daisy chaining is used for level sensitive interrupts, which act like a wired ‘OR’ gate.
Any requesting device can take the interrupt line low, and keep it asserted low until it is
serviced.

Device 1 Device 2 Device 3

Interface Interface Interface

Interrupt
Interrupt
acknowledge
CPU and bus request
Daisy chain Daisy chain Daisy chain
control logic
logic Open Logic Logic
collector
driver
INTA

INTR

+5V

Fig.2.14. Daisy chain

Because more than one device can assert the shared interrupt line simultaneously,
some method must be employed to ensure device priority. This is done using the interrupt
acknowledge signal generated by the processor in response to an interrupt request. Each
device is connected to the same interrupt request line, but the interrupt acknowledge line is
8086 System Bus Structure 2.29
passed through each device, from the highest priority device first, to the lowest priority
device last.
After preserving the required registers, the microprocessor generates an interrupt
acknowledge signal. This is gated through each device. If device 1 generated the interrupt, it
will place its identification signal on the data bus, which is read by the processor, and used
to generate the address of the interrupt-service routine. If device 1 did not request the servicing,
it will pass the interrupt acknowledge signal on to the next device in the chain. Device 2
follows the same procedure, and so on.
(iii) Interrupt priority management hardware
A more flexible hardware priority arrangement can be held by designing a programmable
interrupt priority management circuit and including it in the bus control logic. This is the
fastest system. The duty is placed on the requesting device to request the interrupt, and
identify itself. The identity could be a branching address for the desired interrupt-handling
routine.
If the device just supplies an identification number, this can be used in conjunction
with a lookup table to determine the address of the required service routine. Response time
is best when the device requesting service also supplies a branching address.
2.8.3 Direct Memory Access Block Transfer
A DMA controller allows devices to transfer data to or from the system’s memory
without the intervention of the processor.
During any given bus cycle, one of the system components connected to the system
bus is given control of the bus. This component is said to be the master during that cycle and
the component it is communicating with is said to be the slave. The CPU with its bus control
logic is normally the master, but other specially designed components can gain control of the
bus by sending a bus request to the CPU. After the current bus cycle is completed the CPU
will return a bus grant signal and the component sending the request will become the master.
Taking control of the bus for a bus cycle is called cycle stealing. Just like the bus
control logic, a master must be capable of placing addresses on the address bus and directing
the bus activity during a bus cycle. The components capable of becoming masters are
processors (and their bus control logic) and DMA controllers. Sometimes a DMA controller
is associated with a single interface, but they are often designed to accommodate more than
one interface.
The 8086 microprocessor receives bus requests through its HOLD pin and issues grants
from the hold acknowledge (HLDA) pin. A request is made when a potential master sends a
1 to the HOLD pin. Normally, after the current bus cycle is complete the 8086 will respond
by putting a 1 on the HLDA pin. When the requesting device receives this grant signal it
2.30 Microprocessors and Microcontrollers
becomes the master. It will remain master until it drops the signal to the HOLD pin, at which
time the 8086 will drop the grant on the HLDA pin. One exception to the normal sequence is
that if a word, which begins at an odd address is being accessed, then two bus cycles are required
to complete the transfer and a grant will not be issued until after the second bus cycle.
When a DMA controller becomes master it places an address on the address bus and
sends the interface the necessary signals to cause it to put data on, or receive data from, the
data bus. Since the DMA controller determines when the bus request is dropped, it can
return control to the CPU after each data byte is transferred and then request control again
when the next data byte is ready, or it can retain control until the entire block is moved. The
former is the usual case because this allows the CPU to continue its work until the next data
byte is available.

Address Bus

4
5
CPU
Memory I/O I/O DMAC
Interface
HOLD
HLDA

7 1

2 3
6
8 9 Data Bus

Control Bus

Fig.2.15. Data transfer with a DMA Controller

During a block input byte transfer, the following sequence occurs as the data byte is
sent from the interface to the memory:
1. The interface sends the DMA controller a request for DMA service.
2. A Bus request is made to the HOLD pin (active High) on the 8086 microprocessor and
the controller gains control of the bus.
3. A Bus grant is returned to the DMA controller from the Hold Acknowledge (HLDA)
pin (active High) on the 8086 microprocessor.
4. The DMA controller places contents of the address register onto the address bus.
5. The controller sends the interface a DMA acknowledgment, which tells the interface
to put data on the data bus. (For an output it signals the interface to latch the next data
placed on the bus.)
8086 System Bus Structure 2.31
6. The data byte is transferred to the memory location indicated by the address bus.
7. The interface latches the data.
8. The Bus request is dropped, the HOLD pin goes Low, and the controller relinquishes
the bus.
9. The Bus grant from the 8086 microprocessor is dropped and the HLDA pin goes Low.
10. The address register is incremented by 1.
11. The byte count is decremented by 1.
12. If the byte count is non-zero, return to step 1, otherwise stop.
2.9 MULTIPROGRAMMING
Multiprogramming can execute several jobs concurrently by switching the attention
of the CPU back and forth among them. This switching is usually prompted by a relative
slow input, output storage request that can be handled by a buffer, spooler or channel freeing
the CPU to continue processing.
The code for two or more processes is in memory at the same time and is executed in
a time-multiplexed fashion in multiprogramming.
Multiprogramming enable the CPU to be utilized more efficiently. If the operating
system can quickly switch the CPU to another task whenever the being worked in requires
relatively slow input, output or storage operations, then CPU is not allowed to stand idle.
This mean that more can be accomplished a given amount of time. For example, if a
disk drive that task can be delegated to channel and the CPU can be put to work in another
program while the data are being read in multiprogramming is thus an effective way the fast-
working CPU most busy with computations while slower input, output and storage operation
are being carried out.
Advantages of multiprogramming
l It increases CPU utilization.
l It decreases total read time needed to execute a job.
l It maximizes the total job throughput of a computer.
Disadvantages of multiprogramming
l It is fairly sophisticated and more complex.
l A multiprogramming operating system must keep track of all kinds of jobs it is
concurrently running.
2.32 Microprocessors and Microcontrollers
(i) Single Program

Run Wait Run Wait

Time

(ii) Multi-Programming with Two Programs

Program A Run Wait Run Wait

Program B Wait Run Wait Run Wait

Run Run Run Run

Combined Wait Wait
A B A B
Time

(iii) Multi-Programming with Three Programs

Program A Run Wait Run Wait

Program B Run Wait Run Wait

Program C Wait Run Wait Run Wait

Run Run Run Run Run Run

Combined C Wait C Wait
A B A B
Time

2.9.1 Process Management

In a single-processor multiprogramming system, two or more processors reside in the
memory and share the CPU, but the CPU can execute only one of these processes at a time.
In a simple multiprogramming system there are three states that the processes can be in, with
each process being in exactly one of these states at any given time.
8086 System Bus Structure 2.33
Dispatch
Creation Termination
Ready Running

Timeout

Unblocking Blocking

Blocked

Fig: 2.16. States and Transitions

The life-cycle of a process can be described by a state diagram which has states
representing the execution status of the process at various times and transitions that represent
changes in execution status. The state diagram for a process captures its life-cycle. The
states represent the execution status of the process; the transitions represent changes of
execution state.
Each active process has its own execution status, so there is a state diagram for each
process. There are relationships between the states of various processes that are maintained
by the operating system.
2.9.2 States
Ready: A process in the ready state has all of the resources that it needs for further
execution except for a processor. It is normally held in a ready queue until a processor
becomes available.
Running: A process in the running state has all of the resources that it needs for further
execution, including a processor.
Blocked: A process that needs some resource other than a processor for further
execution is in a blocked state. It is usually placed in a queue waiting for the needed resource.
2.9.3 Transitions
The transitions of a process represent changes of its execution state. The transitions
can be described in terms of their causes and the resulting actions taken by the operating
system.
Creation
l The creation transition is caused by a syscall for loading a program.
l A process control block is created for the program. It is initialized so that the
process starts with cleared registers and PC set to the program’s start (main)
2.34 Microprocessors and Microcontrollers
address. Usually the operating system sets up three open files: standard input,
standard output, and standard error.
Dispatch
l A process is dispatched when a processor is free to execute the process and the
operating system has scheduled the process to run next. Scheduling involves
selecting one of the ready processes to run next. The choice is often based on
which ready process has gone the longest time since it last had a running execution
status, but the choice may also involve prioritization of processes.
l Saved information about the process’s register and PC contents is loaded into
the processor. The PC contents are typically loaded by executing a jump
instruction which, in effect, resumes execution of process code from where it
left off.
Timeout
l A timeout is triggered by an external interrupt from a timer device.
l Information about the process’s register and PC contents is saved into the PCB
for the process. The process then goes into the ready state, where it enters a
queue with other ready processes. The operating system will the schedule one of
the ready processes and dispatch it.
Blocking
l A blocking transition is caused by the process making an operating system request
(syscall) that must be satisfied before it can continue executing. The most common
type of request is a request for input.
l The operating system will initiate an action to satisfy the request. For example,
for file input from a disk, the operating system will send a signal to the disk
initiating the fetch of a block from the disk. The process is put into a blocked
state, where it cannot execute until its request is satisfied.
Unblocking
l The unblocking transition is triggered by satisfaction of the request that lead to
blocking. For example, if a process requested file input from a disk, the
satisfaction will occur several milliseconds later when the disk sends an external
interrupt indicating that it is ready to transfer the requested block.
l After the operating system has handled the request satisfaction it puts the process
into the ready state, entering it into the ready queue. In the file read example,
handling the request means storing the block contents in a file structure for the
process.
8086 System Bus Structure 2.35
Termination
l The termination transition may be triggered by an exit syscall from the process
(normal termination) or by a processor exception (abnormal termination).
l The operating system frees up any resources used by the process. If the
termination is abnormal an error message is displayed.

2.10 MULTIPROCESSOR CONFIGURATIONS

Multiprocessor

A multiprocessor system will have two or more processors that can execute instructions
or perform operations simultaneously.

Need for Multiprocessor Systems

1. Due to limited data width and lack of floating point arithmetic instructions, 8086
requires many instructions for computing even single floating point operation.
For this Numeric Data Processor (8087), can help 8086 processor.
2. Some processor like DMA controllers can help 8086 with low level operations,
while the CPU can take care of the high level operations.
Advantages
1. Several low cost processors may be combined to fit the needs of an application
while avoiding the expense of the unneeded capabilities of a centralized system.
2. It is easy to add more processor for expansion as per requirement.
3. When a failure occurs, it is easier to replace the faulty processor.
4. In a multiprocessor system implementation of modular processing of task can
be achieved.
Basic Multiprocessor Configurations
1. Co processor configuration
2. Closely coupled configuration
3. Loosely coupled configuration

2.11 COPROCESSOR CONFIGURATION

In coprocessor configuration both the CPU (8086) and external processor (Math
Co-processor 8087) share entire memory and I/O sub system. They also share same bus
control logic and clock generator. 8086 is the master and 8087 is the slave.
2.36 Microprocessors and Microcontrollers
8087
Coprocessor
8086

Wakeup the Coprocessor

ESC Monitor the

(Escape) 8086

Execute Deactivate the host’s

the 8086 TEST pin and execute the
instructions specified operation

Activate the
WAIT TEST pin
Wake up the
8086

Fig. 2.17. Interaction between 8086 and Coprocessor

Coprocessors add instructions to the instruction set. An instruction to be executed by

the coprocessor is indicated by an escape (ESC) prefix or instruction.
1. The 8086 fetches the instructions.
2. The coprocessor monitors the instruction sequence and captures its own
instructions.
3. The ESC is decoded by the CPU and coprocessor simultaneously.
4. The CPU computes the 20 bit address of memory operand and does a dummy
read. The coprocessor captures the address of the data and obtains control of the
bus to load or store as needed.
5. The coprocessor sends BUSY (high) to the TEST pin.
6. The CPU goes to the next instruction and if this is an 8086 instruction, the CPU
and coprocessor execute in parallel.
7. If another coprocessor instruction occurs, the 8086 must wait until BUSY goes
low ie, TEST pin become active. To implement this, a WAIT instruction is put
in front of most 8087 instructions by the Assembler.
8. The WAIT instruction does the operations ie, wait until the TEST pin is active.
8086 System Bus Structure 2.37
9. The coprocessor also makes use of Queue Status (QS 0 –QS 1 ) of the 8086
instructions queue.
QS 1 QS 0 Operation
0 0 No action
0 1 First byte of current instruction taken
from queue
1 0 Queue flushed
1 1 Byte other than first byte taken from queue
Fig. 2.17 shows the interaction between 8086 and 8087.
2.12 CLOSELY COUPLED CONFIGURATION
Coprocessor and closely coupled configurations are similar in that both the 8086 and
the external processor (8089) share :
Memory
I/O system
Bus and Bus control logic
Clock generator
The interaction between 8086 and coprocessor or independent processor is shown in
Fig. 2.18.

8086

Bus
Clock
control System Bus
generator
Logic
Coprocessor
or
Independent
Processor

Memory I/O

Fig. 2.18. Closely Coupled Configuration

The main difference between coprocessor and closely coupled configuration is, no
special instruction WAIT or ESC is used. The communication between 8086 and independent
processor is done through memory space.
As shown in Fig.2.19, the 8086 sets up a message in memory and wakes up independent
processor by sending command to one of its ports. The independent processor then accesses
2.38 Microprocessors and Microcontrollers
the memory to execute the task in parallel with the 8086. When task is completed the external
processor informs the 8086 about the completion of task by using either a status bit or an
interrupt request.
Set up
message

8086 8089
Independent
Wake up
Wait for Processor
independent processor
with an OUT request
instruction

Fetch
message

Execute
the 8086’s program
sequence
Perform
assigned task

Wait for
Notify CPU
Ready or Interrupt
of completion
request

Fig. 2.19. Interaction between 8086 and 8089

2.13 LOOSELY COUPLED CONFIGURATION

In loosely coupled configuration a number of modules of 8086 can be interfaced through
a common system bus to work as a multiprocessor system. Each module in the loosely coupled
configuration is an independent microprocessor based system with its own clock source, and
its own memory and I/O devices interfaced through a local bus. Each module can also be a
closely coupled configuration of a processor or coprocessor. The block diagram of a loosely
coupled configuration of 8086 is shown in Fig. 2.20.
Advantages
1. Better system throughput by having more than one processor.
2. The system can be expanded in modular form. Each processor is an independent unit
and normally on a separate PC board. One can be added or removed without affecting
the others in the system.
3. A failure in one module normally does not affect the breakdown of the entire system
and faulty module can be easily detected and replaced.
8086 System Bus Structure 2.39
4. Each processor may has its own local bus to access dedicated memory or I/O devices
so that a greater degree of parallel processing can be achieved.
Bus allocation schemes:
i. Daisy chaining
ii. Polling method
iii. Independent Priority
Module - 1

Clock
8086/8088
Generator

Local Bus Local Bus System Bus

Control Logic Control Logic

Local Local
Memory I/O
Devices

Module - 2 System
Memory

Clock
8086/8088
Generator
System Bus

Local Bus
Local Bus System Bus
Control Logic Control Logic

Local Local
Memory I/O
Devices

Module - 3 System
I/O devices

Clock
8086/8088
Generator

Local Bus Local Bus System Bus

Control Logic Control Logic

Local Local
Memory I/O
Devices

Fig. 2.20. Loosely coupled configuration

2.40 Microprocessors and Microcontrollers
2.13.1 Daisy Chaining
In daisy chaining method all masters make use of the same line for bus request. In
response to a bus request, the controller sends a bus grant if the bus is free. The bus grant
signal serially propagates through each master until it encounters the first one that is requesting
access to the bus. This master blocks the propagation of the bus grant signal, activates the
busy line and gains control of the bus. Therefore any other requesting module will not receive
the grant signal and hence cannot get the bus access.
This bus allocation scheme is simple and cheaper. But failure of any one master causes
the whole system to fail and arbitration is slow due to the propogation delay of bus grant
signal is proportional to the number of masters. The connection diagram for daisy chaining
method is shown in Fig.2.21.

Master 1 Master 2 Master N

Bus access Bus access Bus access

logic logic logic

Controller

Fig. 2.21. Daisy Chaining Method

2.13.2 Polling Method

In polling method, the controller sends address of device to grant bus access. The
number of address lines required is depend on the number of masters connected in the system.
For example, if three masters are connected in the system, one address line is required. In
response to a bus request, controller generates a sequence of master addresses. When the
requesting master recognizes the address, it activates the busy line and begins to use the bus.
The priority can be changed by altering the polling sequence stored in the controller.
Another one advantage of this method is, if one module fails entire system does not fail.
The connection diagram for polling method is shown in Fig.2.22.
8086 System Bus Structure 2.41

Master 1 Master 2 Master N

Bus access Bus access Bus access

logic logic logic

Controller

Fig, 2.22 Polling Method

2.13.3 Independent Priority

In the independent priority scheme each master has a separate pair of bus request
(BRQ) and bus grant (BGR) lines and each pair has a priority assigned to it. The built in
priority decoder within the controller selects the highest priority request and asserts the
corresponding bus grant signal. Synchronization of clocks must be performed once a master
is recognized. Master will receive a common clock from one side and pass it to the controller
which will derive a clock for transfer.
Due to separate pairs of bus request and bus grant signals, arbitration is fast. The
connection diagram for independent priority method is shown in Fig.2.23.

Master 1 Master 2 Master N

Bus access Bus access Bus access

logic logic logic

Controller

Fig. 2.23. Independent Priority Method

2.14 INTRODUCTION TO ADVANCED PROCESSORS

After the 8086 microprocessor, Intel moved to 80186, 80286, 80386, 80486 and
Pentium. This section is presenting the features of protected mode of x86 processor, Pentium
2.42 Microprocessors and Microcontrollers
processors, powerPC processors and multi-core processors. The generation of Intl processors
is illustrated in Table 2.4.
Table 2.4. Intel family processors
Generation Microprocessor Features
PI 8086 16-bit registers and data bus, real mode only
8088 Same as 8086 with 8-bit external data bus
P2 80286 Added protected mode
P3 80386Dx 32-bit registers and buses, added virtual 8086 mode
80386Sx Same as 80386Dx with 16-bit external data bus
P4 80486Dx Same as 80386Dx with integrated FPU and L1 cache
80486Sx Same as 80486Dx without coprocessor
80486Dx2 and Same as 80486Dx with faster (2x or 3x) internal clock
80486Dx4
P5 Pentium Classic Dual instruction pipelines, 64 bit external data bus
Pentium MMX Same as Classic with support for MMX
P6 Pentium pro Dynamic execution, L2 cache in same package, no MMX
Pentium II Same as Pro new cartridge package, MMX support
Celeron Same as Pentium II but no integrated L2
Pentium III Same as Pentium II with SSE support
Pentium 4 Microburst architecture
P7 Itanium 64-bit registers, 128 bit instruction bundles with explicit
parallelism, 128 bit data bus, 64 bit address bus

2.14.1 Protected mode operation of x86 family

The first processor in the 80x86 family was the 16-bit 8086, which was capable of
addressing one Megabyte of memory, a significant improvement over the 8-bit machines
available in the late 1970s. Twenty address lines were provided on the processor to access
the 1MB of memory. The advanced processors that followed the 8086, beginning with the
80286, all contained additional address lines. The 80386, 80486, and Pentium all contain 32
address lines, giving them the ability to access 232, or 4 GB of memory. This large addressing
space allows the advanced Intel Microprocessors to perform many operating system chores-
such as multitasking- that are difficult, or even impossible, on the 8086.
8086 System Bus Structure 2.43
Beginning with the 80286, the advanced Intel Microprocessors all contained the ability
to operate in two different modes of operation, Real mode and Protected mode. In real mode,
the advanced processors, including the Pentium, simply operate like very fast 8086, with the
associated 1 MB memory limit. Real mode operation is automatically selected upon power-
up. So a Pentium-based PC that boots up into DOS is operating in real mode (DOS is a real
mode operating system).
In protected mode, the full 4 GB of memory is available to the processor, as are special
privileged instructions and many other architectural goodies, including support for
multitasking, virtual memory addressing, memory management and protection, and control
over the internal data and instruction cache.The Windows operating system runs in protected
mode to take advantage of these improvements. Writing programs that runs in protected
mode requires special background knowledge of operating systems theory.

X86 Family

Real Mode Protected Mode

Virtual 8086 mode

Fig.2.24. Modes of x86 processor

2.14.2. Pentium Processors

The Pentium family of processors originated from the 80486 microprocessor. The term
‘’Pentium processor’’ refers to a family of microprocessors that share a common architecture
and instruction set. The first Pentium processors were introduced in 1993. It runs at a clock
frequency of either 60 or 66 MHz and has 3.1 million transistors.
The features of Pentium architecture are
l Improved instruction execution time
l Bus cycle pipelining
l Address parity .
l Internal parity checking
l Functional redundancy checking
2.44 Microprocessors and Microcontrollers
l Execution tracing
l Performance monitoring
l System management mode
l Virtual mode extensions
The Pentium processor operates at a very high speed. It also overcomes many
performance bottlenecks associated with earlier X86 processors. This enhanced performance
is achieved by it due to its superscalar architecture.
The important features of Pentium architecture are
v Wider (64-bit) Data Bus: With its 64-bit-wide external data bus the Pentium
processor can handle up to twice the data load of the Intel486 processor at the
same clock frequency.
v Superscalar Architecture: Dual Instruction Pipeline
The Intel486 processor can execute only one instruction at a time. With
superscalar execution, the Pentium processor can sometimes execute two
instructions simultaneously.
v Dynamic Branch Prediction Logic: The Pentium processor fetches the branch
target instruction before it executes the branch instruction.
v Enhanced Floating Point Unit: The Pentium processor executes individual
instructions faster through execution pipelining, which allows multiple
floatingpoint instructions to be executed at the same time.
v Dedicated Instruction and Data Cache: The Pentium processor has two separate
8 KB caches on chip-one for instructions and one for data-which allows the
Pentium processor to fetch data and instructions from the cache simultaneously.
v Write-Back MESI Protocol in Data Cache: When data is modified; only the
data in the cache is changed. Memory data is changed only when the Pentium
processor replaces the modified data in the cache with a different set of data.
8086 System Bus Structure 2.45

Code Cache Branch Prediction

8 KB

Pre-fetch Buffer Pipelined Floating

Memory Point Unit
U Pipe V Pipe
Interface
Integer ALU Integer ALU

Register Set
Multiplier
Adder
8 KB
Data Cache Divider

Fig . 2.25. Superscalar Architecture of Pentium

The Pentium processor has two primary operating modes,

1. Protected Mode: In this mode all instructions and architectural features are
available, providing the highest performance and capability. This is the
recommended mode that all new applications and operating systems should target.
2. Real-Address Mode: This mode provides the programming environment of the
Intel 8086 processor, with a few extensions. Reset initialization places the
processor in real mode where, with a single instruction, it can switch to protected
mode.
The five stages of Pentium’s basic integer pipeline are,
1. Pre-fetch/Fetch : Instructions are fetched from the instruction cache and aligned
in pre-fetch buffers for decoding.
2. Decode1 : Instructions are decoded into the Pentium's internal instruction format.
Branch prediction also takes place at this stage.
3. Decode2 : Same as above, and microcode ROM kicks in here, if necessary. Also,
address computations take place at this stage.
4. Execute : The integer hardware executes the instruction.
5. Write-back : The results of the computation are written back to the register file.
2.46 Microprocessors and Microcontrollers

Pre-fetch Instruction

Decode Instruction and

generate control word

General control word General control word

Generate data memory address Generate data memory address

Access data cache Access data cache

Calculate ALU result Calculate ALU result

Write back result Write back result

U Pipe V Pipe

Fig.2.26. Pentium pipeline stages

Floating Point Unit

There are 8 general-purpose 80-bit floating point registers. Floating point unit has 8
stages of pipelining. First five are similar to integer unit. Since the possibility of error is
more in floating point unit (FPU) than in integer unit, additional error checking stage is
there in FPU. The floating point unit is shown in Fig.2.27.

Exponent Result Mantissa Result

FRD

FEXP FADD FEXP

FDD

FAND/FMUL

Fig.2.27. Floating Point Unit

8086 System Bus Structure 2.47
FRD - Floating Point Rounding
FDD - Floating Point Division
FADD - Floating Point Addition
FEXP - Floating Point Exponent
FAND - Floating Point And
FMUL - Floating Point Multiply
2.14.3 64-bit processors in personal computers
In 1990, IBM introduced microprocessor based on POWER architecture with UNIX
operating system. PowerPC was second generation POWER architecture. It has RISC
architecture. RISC architecture tries to keep the processor as busy as possible. Salient features
of RISC architecture are
l Fixed length instructions (4 byte instructions). This allows single decoding
mechanism
l Mostly single cycle instruction execution
l Less number of instructions
PowerPC was created in 1991 by Apple-IBM-Motorola alliance. Originally intended
for personal computers, PowerPC CPUs have since become popular embedded and high-
performance processors as well. It is largely based and compatible with POWER
microprocessor. Design features of PowerPC are as follows.
l Broad range implementation
l Simple processor design
l Superscalar architecture
l Multiprocessor features
l 64-bit architecture
l Support for operation in both big-endian and little-endian mode. PowerPC can
switch from one mode to another at run time.
l Separate set of floating point instructions for
l Separate set of Floating Point Registers for floating-point instructions
Motorola PowerPC 601 was the first PowerPC. Few of its features are
1. 64-bit microprocessor
2. 32-bit address lines
2.48 Microprocessors and Microcontrollers
3. Can handle integer data of 8, 16 and 32 bits
4. RISC architecture with 4 byte instruction length
5. PC 601 has virtual memory addressing of 4 Peta bytes.
2.14.4 Multi-core processor
A multi-core processor is a single chip that contains more than one microprocessor
core. Each core can simultaneously execute processor instructions in parallel. This effectively
multiplies the processor’s potential performance by the number of cores, if the software is
designed to take advantage of more than one processor core. Some components, such as bus
interface and cache, may be shared between cores. Because the cores are physically close to
each other, they can communicate with each other much faster than separate (off-
chip)processors in a multiprocessor system, which improves overall system performance. A
simplified view of multi-core architecture is shown in Fig.2.28.

Core 1 Core 2 Core 3 Core 4

ALU ALU ALU ALU

BUS INTERFACE

Fig.2.28. Multi-core architecture

In 2005, AMD released the first native dual-core processor, the Athlon X2. Intel released
the Pentium D. As of 2012, dual-core and quad-core processors are widely used in home
PCs and laptops, while quad, six, eight, ten, twelve, and sixteen-core processors are common
in the professional and enterprise markets with workstations and servers.
Sun Microsystems has released the Niagara and Niagara 2 chips, both of which feature
an eight-core design. High-end Intel Xeon processors that are on the LGA 771, LGA1336,
and LGA 2011 sockets and high-end AMD Opteron processors that are on the C32 and G34
sockets are dual processor capable, as well as the older Intel Core 2 Extreme QX9775 also
used in an older Mac Pro by Apple and the Intel Skulltrail motherboard. AMD's G34
motherboards can support up to four CPUs and Intel’s LGA 1567 motherboards can support
up to eight CPUs.
8086 System Bus Structure 2.49
MODEL QUESTIONS
PART A
1. When the 8086 processor is in minimum mode and maximum mode?
2. Explain the BHE and LOCK signals of 8086.
3. Which pin is used to activate minimum mode of operation in 8086 ?
4. List the signals of 8086 for minimum mode operation.
5. List the signals of 8086 for maximum mode operation.
6. What is the function of TEST pin in 8086 ?
7. What is the use of ALE signal?
8. What is the use of HOLD and HLDA signals?
9. Why we use MN/MX pin in 8086?
10. What is the use of latch signal on the AD0–AD15 bus in an 8086 system?
11. What are the advantages of multiprogramming ?
12. What are the disadvantages of multiprogramming ?
13. List the states of multiprogramming.
14. Define closely coupled configuration.
15. Define loosely coupled configuration.
16. What are the features of closely coupled configuration?
17. What is meant by loosely coupled configuration?
18. Discuss the advantages of multiprocessor systems.
19. What are the advantages of loosely coupled configuration?
20. What is Daisy chaining?
21. What is polling?
22. Name the three bus allocation schemes used in loosely coupled multiprocessor system.
23. What are the three basic multiprocessor configurations that the 8086 can support?
24. What is a coprocessor?
25. What are the features of 8087?
26. Name the flags available in status word of 8087.
27. What are the functional units available in 8087?
28. What is a tag?
29. Write the data types of 8087.
2.50 Microprocessors and Microcontrollers
30. What is the need of 8089?
31. What are the channel registers in 8089?
32. What is CCP in 8089?
33. Differentiate minimum and maximum mode of 8086.
34. What is Daisy Chaining?
35. What do you meant by pipelining?
36. List any four 32 bit processor.
37. List any four 64 bit processor.
38. What do you meant by multi-core architecture ?

PART B
1. Sketch the block diagram showing 8086 minimum mode system and explain.
2. Sketch the block diagram showing 8086 maximum mode system and explain.
3. Draw and explain the timing diagrams of input and output transfers of 8086 in minimum
mode.
4. Draw and explain the timing diagrams of input and output transfers of 8086 in maximum
mode.
5. Draw and explain the minimum mode write cycle and read cycle timing diagrams.
6. Draw and explain the maximum mode write cycle and read cycle timing diagrams.
7. Interface four 8K RAM and two 8K EPROM with 8086. Interface the RAM bank at a
segment address 0B00 H and the EPROM bank at physical address F800 H.
8. Explain in detail about the multiprocessor system.
9. Explain i) Programmed IO, ii) Interrupt driven IO.
10. Explain daisy chaining.
11. Explain data transfer with a DMA controller.
12. Explain multiprogramming with neat diagram.
13. Explain the various transitions of multiprocessor.
14. With neat diagram explain closely coupled configuration.
15. With neat diagram explain loosely coupled configuration.
16. Explain how co-processor works and interacts with 8086.
17. Discuss in detail about the interconnecting topologies of a multiprocessor system.
18. Discuss about the multiprocessor configuration of 8086.
8086 System Bus Structure 2.51
19. Assume that a loosely coupled multiprocessor system consists of an 8086 with a local
memory in one module and in another module two 8089’s with local I/O bus. Determine
the major bus interfacing devices required for each module.
20. With a block diagram explain the architecture of 8087.
21. Explain the interconnection between 8086 and 8087 in detail.
22. Explain the 8087 coprocessor data format.
23. Explain the architecture of 8089 with neat diagram.
24. Explain the communication between 8086 and 8089.
25. Explain the minimum mode of operations of 8086 with a neat sketch.
26. Explain multi-microprocessor configuration methods.
27. Write down interfacing and operation of 8086 CPU module in MIN and MAX modes
with diagrams.
28. Draw the timing diagram of INTA cycle of 8086 and explain.
29. Write notes on advanced microprocessors.
30. Explain superscalar architecture of Pentium processor.
2.52 Microprocessors and Microcontrollers

ANNA UNIVERSITY QUESTIONS

Part A and Part B questions collected from
Anna University Question papers
(Nov/Dec 2006 to May/June 2013)
8086 System Bus Structure 2.53
PART A

May/Jun 2013
1. What is the function of LOCK and RQ/GT signals.
2. When the 8086 processor is in minimum mode and maximum mode?

May/Jun 2012
1. What are called assembler directives? Give two examples.

Nov/Dec 2011
1. What are the features of closely coupled multiprocessor systems?
2. What do you mean by CCW in an I/O Processor?

May/Jun 2011
1. How does co-processor identify the instructions meant for it?
2. Name the signals used by the processor to communicate with an I/O processor.
3. When the 8086 processor is in minimum mode and maximum mode?

Nov/Dec 2010
1. List the pointer and index registers of 8086 Architecture.
2. Identify the addressing modes involved in the following 8086 instructions: MOV AX,
0005H; MOV AX, 50H [BX][S1].

May/Jun 2010
1. Compare closely coupled configuration with loosely coupled configuration.
2. Mention the need for co-processor in a microprocessor based system

May/Jun 2009
1. What are the three basic multiprocessor configurations that the 8086 can support?

Nov/Dec 2008
1. What does it imply if the states of 8086 signals - BHE and A0 are at 0 and 1, respectively?

Apr/May 2008
1. Explain why the processor utilization rate can be improved in a multiprocessor system
by an instruction an instruction queue.
2. What information is conveyed when QS 1 , QS 0 bits are 01?
2.54 Microprocessors and Microcontrollers
3. Explain the BHE and LOCK signals of 8086.

Nov/Dec 2007
1. What is a Coprocessor?
2. What is the use of ALE signal?
3. What is the use of HOLD and HLDA signals?

4. Why we use MN/ MX pin in 8086?

Nov/Dec 2006
1. What is the use of latch signal on the AD0 –AD15 bus in an 8086 system?

Apr/May 2006
1. What are the advantages of a loosely coupled configuration in a multiprocessor system?
2. What are the signals differentiate ‘maximum mode’ and ‘minimum mode’ operation of
8086?

PART B

Nov/Dec 2013
1. What are the difference between memory mapped I/O and I/O mapped I/O. (6)
2. Draw and explain the timing diagram of write cycle in 8086 in minimum mode. (8)

May/Jun 2013
1. Describe the maximum mode of operation of 8086. (8)
2. Explain the 8086 basic bus cycle timing diagram. (6)

Nov/Dec 2012
1. Compare Closely Coupled configuration with Loosely coupled configuration. (8)
2. How is the communication between CPU and IOP being done? (8)
3. Describe the Maximum Mode Signals, Bus Cycles and Maximum Mode System
configuration of 8086 Microprocessor in detail. (16)

May/Jun 2012
1. Explain how I/O processor communicates between the CPU and I/O peripherals with
an example? (8)
8086 System Bus Structure 2.55
2. Draw the pin diagram of 8086 CPU and explain the functions of the pins in minimum
and maximum mode of operation of 8086. (10)
3. Describe the circuit suitable for generation of multiple wait states for 8086 CPU module.
(6)

Nov/Dec 2011
1. Discuss the schemes used to solve the bus arbitration problem in multiprocessors.(6)
2. Explain the bus structure of 8086 microprocessor. (8)
3. How does one configure 8086 in maximum mode and minimum mode? Explain. (8)

May/Jun 2011
1. Explain the salient features of 8087 co-processor units in architectural diagram. (8)
2. Draw the architecture of 8089 I/O processor and explain its functionalities. (8)

Nov/Dec 2010
1. Distinguish between loosely coupled and closely coupled multiprocessor systems with
suitable examples.

May/Jun 2010
1. Draw the internal block diagram of 8087 Co-processor and explain it with 8087 control
word and status word formats. (12)
2. Give two examples for packed decimal data transfers and integer data transfers of an 8087
Co-processor. (4)

May/Jun 2009
1. Explain the minimum and maximum mode operations of 8086 with neat diagram. (16)
2. Explain the memory addressin in 8086 (8)
3. What is bus arbitration? Explain briefly the various bus arbitration schemes. (8)

Nov/Dec 2008
1. Explain the basic bus access control and arbitration schemes used in multiprocessor
systems. (8)
2. What happens when 8086 is operated in maximum mode? List the signals that are
unique in this mode. (8)
3. Explain the maximum mode operation of 8086. (12)
2.56 Microprocessors and Microcontrollers
Apr/May 2008
1. Discuss about the multiprocessor configurations of 8086. (16)
2. Assume that a loosely coupled multiprocessor system consists of an 8086 with a local
memory in one module and in another module two 8089’s with local I/O bus. Determine
the major bus interface devices required for each module.
3. Draw and discuss the configuration diagram for the maximum mode operation of 8086.
(16)

Nov/Dec 2007
1. Discuss in detail about the interconnecting topologies of a multiprocessor system.
(16)
2. Discuss the software aspects of a multiprocessor system. (12)
3. Explain the I/O addressing capability of 8086. (4)
4. Explain about the different Interconnection topologies in multi microprocessor systems.
(16)
5. Explain in details about the maximum and minimum mode operation of 8086 system
with their respective timing diagram. (16)

Apr/May 2007
1. Explain the maximum mode operation of 8086 (12)
2. Explain the Minimum mode operation of 8086. (12)
3. Explain the function of following 8086 signals.
(a) HLDA

(b) RQ/GTO

(c) DEN
(d) ALE
4. Draw and explain in block diagram showing 8086 in maximum mode configuration.
(12)

Nov/Dec 2006
1. Explain the MIN/MAX mode operation of an 8086 processor. (10)

Apr/May 2006
1. Write a brief note on 8086 base loosely coupled system configuration. (8)
2. Explain the minimum mode configuration of 8086 processor. (8)
8086 System Bus Structure 2.57
TWO MARKS QUESTION AND ANSWERS
1. What are two operating modes of 8086?
The processor operates in two modes
l Minimum mode-Single Processor Configuration
l Maximum mode-Multiprocessor Configuration
2. State the significance of LOCK signal in 8086?
This output pin indicates that other system bus master will be prevented from gaining
the system bus, while the LOCK signal is low. The LOCK signal is activated by the
LOCK prefix instruction and remains active until the completion of the next instruction
3. State the function of queue status lines QS0 AND QS1 in 8086 microprocessor?
These lines give information about the status of the code- prefetch queue. These are
active during the CLK cycle after which the queue operation is performed. These are
encoded as shown in table
QS1 QS0 INDICATION
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte from the queue

4. What is the function of the BHE signal in 8086?

BHE is output during the first part of machine cycle. LOW signal on BHE pin indicates
access to high- order memory bank governed by data bits AD15 AD8; otherwise access
is only to the low order memory bank governed by data bits AD7 –AD0. BHE and A0
decide the memory bank and type of access.
5. What is the use of MN/MX Pin in 8086.
The logical level at this pin decides whether the processor is to operate in either
minimum or maximum mode.
6. Give the functions of READY and TEST pins of 8086.
READY is an input signal to the processor, used by the memory or I/O devices to get
extra time for data transfer or to introduce wait states in bus cycles.
TEST is used in conjunction with WAIT instruction. The instruction puts the 8086 in
idle states which end only when the TEST input goes low.
2.58 Microprocessors and Microcontrollers
7. Mention the use of HOLD and HLDA pin 8086
HOLD request. This signal, when low, indicates that another master has requested for
direct memory access. When HOLD becomes low, it indicates that direct memory access
is no more required.
HLDA: the microprocessor sends high signal on HLDA to indicate acknowledgement
of DMA request. It then tristate the buses and control signals. When HOLD becomes
low, the microprocessor makes HLDA low and regains the control of buses.
8. What are the three groups of signals in 8086?
The 8086 signals are categorized in three groups. They are:
i. The signals having common functions in minimum and maximum mode.
ii. The signals having special functions for minimum mode.
iii. The signal having special functions for maximum mode.
9. List the Bus allocation schemes?
l Daisy chaining
l Polling method
l Independent method
10. What are the advantages of the multiprocessor system? [May/June 2007]
l High level performance can be attained when parallel processing.
l Robustness can be improved by isolating system functions.
11. Explain why the processor utilization rate can be improved in a multiprocessor
system by an instruction queue? [May/June 2008]
The processor has to fetch the instruction from memory before decode and execute it.
Fetching the instruction from memory takes considerable amount of time and processor
has to wait and processor has to wait during this time, reducing its utilization rate. The
instruction queue mechanism before the execution so that processor need not have to
wait for instruction fetch, improving the utilization rate.
12. What are the multiprocessor configuration methods?
l Co processor
l Loosely coupled
l Closely coupled
13. Write a program to add a data byte located at offset 0500H in 2000H segment to
another data byte available at 0600H in the same segment and store the result at
0700H in the same segment.
8086 System Bus Structure 2.59
MOV AX, 2000H ; initialize DS with value MOVDS, AX; 2000H
MOV AX, [500H] ; Get first data byte from 0500H offset
ADD AX, [600H] ; Add this to the second byte from 0600H
MOV [700H], AX ; store AX in 0700H
HLT ; Stop.
14. Distinguish between the maximum and minimum mode of operation of the 8086
processor. [Nov/Dec 2009]
S.No. Minimum mode Maximum mode
1. Used for Single Processor system. Used for Multiple Processor system.
2. Control signals RD(low), WR(low), Control signals IORC(low), IOWC(low),
M/IO(low), ALE,DEN(low) and MRDC(low), MUTC(low), ALE, DEN
DT/R(low), are generated by and DT/R(low), are generated by bus
Microprocessor controller 8288.
3. Less control signals are required. More control signals are required.
4. Less costly. More Costly.
5. System is low. System is fast.

15. Compare closely coupled configuration with loosely coupled configuration.

[Apr/May 2010]
S.No Closely coupled configuration Loosely coupled configuration
1. Shared memory multiprocessor system Distributed memory multiprocessor
system
2 Several processors share a common Each processor has its own local
memory memory
3 Well suited and more efficient for More efficient when the interaction
higher degree of interaction tasks between the tasks are minimal

16. What is DMA? What are the advantages of DMA?

The direct data transfer between I/O device and memory is called DMA. Using DMA,
bulk data transfer can take place between the memory and I/O device bypassing the
microprocessor.
17. What is Multiprogramming? [NOV/DEC 2015]
If mor e than one pr ocess is car r ied out at the same time, it is known as
Multiprogramming.
2.60 Microprocessors and Microcontrollers
To improve the utilization of CPU and I/O devices we are designing to process a set of
independent programs concurrently by single CPU. This technique is known as
Multiprogramming.
18. Define Cycle Stealing?
Cycle stealing is a method of accessing computer memory (RAM) or bus without
interfering with the CPU. It is similar to direct memory access (DMA) for allowing I/
O controllers to read or write RAM without CPU intervention.
19. Define bus. Why bus request and cycle stealing are required? [APR/MAY 2015]
A set of wires used for transferring information between the components in a computer
system is called a Bus.
DMA controllers can operate in a cycle stealing mode in which they take over the
bus for each byte of data to be transferred and then return control to the CPU. They
can also operate in burst mode in which a block of data is transferred before
returning bus control to the CPU.
20. Schematically show, how synchronization is made between 8086 and its
coprocessor. [NOV/DEC 2015]
Coprocessor (i.e.8087)
8086/8088

Wakeup the Coprocessor

ESC Monitor the

(Escape) 8086 / 8088

Execute Deactivate the host’s

the 8086 TEST pin and execute the
instructions specified operation

Activate the
WAIT TEST pin
Wake up the
8086
8086 System Bus Structure 2.61
21. Draw the read cycle timing diagram for minimum mode.

CLK

T1 T2 T3 TW T4

ALE

ADD/STATUS BHE. A19–A16 s7–s3

A15–A0 Bus reserved

ADD/DATA D15 –D0
for data in

RD

DEN

DT/R

22. Draw the Memory write cycle timing diagram for Maximum Mode.
One bus cycle
T1 T2 T3 T4 T1

Clk

ALE

S2–S0 Active Inactive Active

ADD/Status BHE S7–S3

ADD/Data A15–A0 Data out D15–D0

AMWC or AIOWC

MWTC or IOWC

DT / R
DEN
2.62 Microprocessors and Microcontrollers
23. What is daisy chain bus arbitration?
Only single bus arbiter performs the required arbitration and it can be either a
processor or a separate DMS controller. There are three arbitration schemes which
run on centralized arbitration. a) Daisy Chaining ” It is a simple and cheaper method
where all the masters use the same line for making bus requests.
24. How many caches are there in Pentium microprocessor?
The Pentium processor has only one level of cache, referred to as Level 1 (L1). The
L1 cache is located on-chip and is divided into separate pieces; one for data and one
for code, each at 8KB.
25. What is the latest microprocessor?
Intel’s latest and sixth-gener ation chip is called the Pentium Pro. All Intel
microprocessors are backward compatible, which means that they can run programs
written for a less powerful processor.