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Adc

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Mohamed Yasser
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57 views18 pages

Adc

Uploaded by

Mohamed Yasser
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Zz] Anode 9 - To - Digitel-Convertey- (ADC) * Signed types: Senalog signaf 9- digited signod > My siod guoatity Vories with time | —» Binary digit! sins use tue In smobth onl continuous Fashion | discrete Voltage level to replesent > Value is Continue sly Changing, | binary 4 or 0 —> sequence of fixed-width sqnave AAS we ft Ee a = 5 L___t t ae ee ADC: is @ circuit thet Gnverts a canfinnous Voltage Value (analog) to a binary value (digit) that Can be Under stood by a digit device hich cau) then be used Por digiteh amputation. —> these ADc circuits Can be found as an individual ADC TCs by than selves or embedded into a mictocenttelley- digited te anctog converter (DAC):- are used in trans forming, tyonsmitted 0 Stored data or the results of digit processing , backx to ‘reel worl” exe elements of Conmwnication system :~ ( Seurce]—s [ile transducer} STK |chonne/| J Px\-s|e7e trensiuccr| [/p tronsducer + convert the message produced by a source fo aform suitable Fer the ammmication system ( analog fo digital) ofp tronsgucer: anverts the received signal back into a uSefuf quantity OR» converts digits electriod signad into the form desited by the syste Conalog ) ex: : i/P Homsducer” + Speech waves —+ microphone —, Voltage (Medwation process) ofp Hensincer + Yolfaqe —s loud speukers ( Demedulation Process) [za] *Ih Converting, an anelog signed to on epui\etent Sequence of ‘o' and “4” Giigitel signod) we go through three processes: 4- Sam pling 2- Quentizetion — 3- Coling ( symbol to bit maprer + these three processes are the Port of mediation process. (FCM) > Medulodion : pulse cole molmtetion the process of Gnverting. the message (signal te a form snitble Por the system 4 Sampling :- —> @nver ting. cntinuens-time anole signal to on ~ sampling rote’ refers to the mumber of samples Perseand taken Prom a cantinuons signal t cnvert it into adigitll signed sthe higher the seampling rete, the more accurate the digiled representetisn of the analog. signed. this Sampling rede must be a least) twice the hivhest Prepancy to accurelely represent the stynal. Fe > 2 Finny > Nyquist rete: CFy)—> this Is the minimum sampling rate repuired fo actarately repte sent a Signed without oMasing . it is equad fo besice the maximun frquot Cf of the signal sox > EF Ina Fy, =2 Frnay i> ky | * Tes sample period \za] * aliasing problem — the signed in frequency demain A tot time demain + : GH eriginnd signed in Prep demain (spectrum) : Nyquist Yote=2Fin oF f5+Fr — Fe-Fn =f = 2 Fin = Gy > minimum cepuirement For reconstruction of signed F5- fin < fim oF <2 Fm —> reconstruction net possible because of aliasing Probl + thet Is , the sampling Frequency must be rere tren teice the Value of the highest frequancy aliasing can Guse distortion of the signed overlapping, is Glled aliasing, (2] Quantization : — onverting discrete-time anedeg signal to discrete time digit signe % step size of a quai ZEN is: the size op the smallest change or increm between adjacent oufPud Yolues» a an step size (4) = Yee Lt No-of Guontlzation level = 9” ms Nove bits in ADG —s (resolution) exe \ Be) assume thet of Values of the enolod input fo asithin a vonge of o1s 7 and we have a lo-bit A/D Ser. system ¥ Nevof quontizetion Levels *L" = oe = ort levels % stepsize ‘a's 222 - 4.9829 mV Tory CKt 3bit System '- ls Le=2°=8 level Kay Aa 2Xmay * Jt . QuentizZation error: the x difference betacen the actied input signed and the quantized output signad x the step size of the guonfizer is directly prePortionad to the Quantization error; A smaller step size leds tog “ 4 smMer quan tiZzetion effer — this is because @ smaller step SiZC Beds Aime Se they require more pins te interface with MCU or other digitod device: — i Case of ib-bit porellel ADC chip, we need IbPINS for the dats Path — in order to save pins, many 12- and 16-bit ADCs use pins Do:D7 fo send out the upper end lower bytes of the binory data —> Parellel ADCs usually offer higher accuracy » beCause they con sample and hold the inpod signed over longer periels of times, allowing fo befio resolution and mar Precision - Nee wR cs RD —> the ability to semple an} bel on input signe! far knger rericds oF time Con be imporfeat in applications where the signal chenges slouly ever time or where it Is necessary to Gpture speafiC features in the signal Por cxomple, in sclentiFic experiments or medicod menitering systems, It may be necessary fo samph end hel the inprd signal over severed minutes er hours fo capture importont informotion or detect pattern. —s porallel ADEs are often used in high-speed data systems or other applicatens where fast chversion rates csith high accuracy are required. # disad vonboes of Patollel ADCs -amplexity — — requiring more campnents — ~ lar¥er In size — GNSuM jag, more Pooler. [21 El serial Acs:- > Seriel ADCs are simpler in design compared te Parallel nes. They convert one bit cH et atime using a single Gnversien — oHL chenned, HIE eaten easier te ! MAX MZ implement end less eXPENSIVE + A7 —) ni > the Inpad sad is sampled using an analog. =e AT Imeltiplexer thet selects the appropri Channel fer conversion Din “SHDN ss Pr] — the Gorverted digitel data is then Wansmitted Serially thrugh a single eutPu * fin . —> thet means that insite the serial ADC, there Is a paroltel-in~ Seried out shift register ves pen sible fer sending oud the binary dots one Lit at a time —+ Se,» moye cpu time is necded fo gef the Gnverted dota frem the Adc beause the cpu must get data one bit ata time, instead of in one single read eperatin as with the porelel ADC. cs sa ‘po Dot —> ohe of the Main advonfages of serial ADCs is their low power Gnsumption because they process only one bit at a time , this maker them ided Por battery-operated devices where fover fPictency Is Critial. — serial ADCs may have lower actuyacy Jue to their limited sampling Fate ond te solution when Compared ith parcel ADC,» —> Serled ADCs Vequive fewer pins and are often smaller and less expensive then pareflel ADCs » they are wel suited far application cuhere space and @st ave importaat and data speed is not critiod Sane 1331 Re Solution +_ — resolution in AIDC referes to the amber of bits (8, ler 12. 1b, 2) thet con be used to represent a digited Vale for cach enalog input Voltage Level. — the resolution determines he an ADC can divide up the tany of Possible anedeg infu veltage inte discrete steps, which affects tS a Ccupagy. —> HNigher--reselution ADCs provide 4 smaller step size (quanti zotion lever — step size is the smallest change tot canbe discerned by aa AIDC > ee Gn contro] the step size es'th the help of Vreg + > Veg Is the mezinum inpied Velloge used For Comporing, the input Voltage: — > the input voltage an be ered or less thon Vreg eX if Vp =$V and n- bif ho: of. steps step size g a o56 5/256 =19-53mV Jo 2”. Jozy Slory = 4.388mV 12 2” = 4096 = l2my 6 2! = £5,536 =o-076mvV €x for controlling the step size in 3-bit ADC —_, 2% 256 Vreg step size G-0oT 5/256 = 19-53 my 4oaV 4/256 = 1§-62 my Zo0oV 2/256 = I-71 mV 256V 296/256 lo mV Z0ov 2/256 = 7.8)mv — > In Je-blt ADC ——se"=|-24 G:00V G /\o24 = 4.38 mV 44.096 ax Y 4.096 /Jor = mY av Z/jory4y - 293 mv 2567 256/lor4% = 25 mV (uy 4 @nNer sien Time :- —s is JePined as the time it takes the ADC te anvert the anoled, input to a digital number. = the anversien time is dicteded by the clock seurce omeckd » the ADC in addition to the meted used Par deta Gnversbn and technology used in the fabrication of the ADC X digital dada ouf Pat — in g-bit ADC —» ue have a-bit digihd dofa —s D0: D7 — in je-bit ADC —> De: DI Via enalog inpet vltage . Nin mi Dawg = sep size (Weg /2") TF ee TT * ADC Types: — porate design flash ADC) —= DAC based design —» remp 4 SAR, tacking, — integrator basef designs single~slepe , dual - slope > sigma-delta design Csp) — piptined design - (=) _intestetor biference > a Cer inpaf_ Bit-outto — Ddfa-sigma ADC: low- middle speed (Few K5Ps) . ; . low Pass 7 High resdatin—~ nets —) ile st ¥ Delle sigma (xe) ADCs are a tyre ot over sompliny, analog te digitel Gnverter thot uses a technique Called sigma-delfa modulodion — the kesic principle is to take muttple measurements of the onaleg. signal and then average these measurements over time. his process effectively INCheases the reselutlen of the amverter by reducing quonfiZahion noiScap with the help of neise shaping ,cshich refers to 4 technigue Used chere the quantization noise is pushed out of the Preqvancy benJ. this 1's dene by Using. 9 feed back loop that integredes the error betucen the input an) ont pt» Xtey it works:. d- the input analog signed is sampled at a much highey~ rete then the Nyquist rafe, this is dene fe inazase the resolution of the ADC ond fe reduce the quontiZeden error. 2- the oversampled signal Is passed Hhreugh a delta-sigma medwlefoy-. the modulator is a Peed bacls loop thet Onsists of a digit fo analog enverter (DAC) and a @mparater. the DAC generodes a referenle Voltage that is ampared to the oversampled signal by the Gmparabr. the output of the Omparafor iso 41-bit digitel signed that has a high Prequoncy Palse density efFectively quontizes the signal ith a high resolution. - the outpt of the delta sigma modulator is then passed through a digit) Fille” thet Performs neise shaping - the digited filter removes the high Frepuancy noise Prom phe oversampled signed and shifts it to the higher Prequancy » where it an be easily filtered out. the outPot of the digited Fier Is a high-resolution digited signal that accurately represents the input enaleg signod 3. Ainally, the Jigited sighel is processed by « microcentrller or a dig ited signal pleceser (DSP) te exhact the desired information from the slanod % Defla-sigma ADCs ave. widely used in Medial andia appliotits there high~reselufion ond high. aCuracy ADCs ove repuyed. [22 2)Flash ADC. (parallel ADCs) —> Is the fastest tyfe of ADC and use larye numbers of comparators. An w-bit flash ADC Gnsists of(2") resistor and (2"=4 ) comparators « vin Br bit Plash ADC Vere Wo —l V7 Veltage = divider = |__ fBe ayouit ms [a] Binary ont Pat Ss }——_ Bs 7 “% \y 2g ao N, s _ Fk mln _ RAR _ ye RAR # Meg =e Veh Voz Fe XMep= % Vrep Vez Vee Vz= % Vref resolution = 11S = wee — each amperatr Compares the input vellage allth the YePerence \eltage, — if the input Vellge is greeter than the refeten Ce \eltege , then the out Prt of thot partiodar mparafoy will become high » and if thet is het the case, then it alll remain Leos. —> based on the Comforotor oufputs, this encoder gives the binary le (82Z/ — Prinity encler » it delermines the Input olith the highest privily and generates on oufPd Gde thet reprecents that inputs ¥ AdVentoges + — PoStest ADC —> suitable Per lorge bandesidth a pplicatiens eg. -satellite Communication - Radar processing -oscillo scope —> Catch every rapid Change x disadvan tayes . —> High power Gnsump tion —slimited resolution (3:12 bit) ~s large Die Area (2"1 comPartor) = HIgh cost 3- Succesrive Approximation Apc. (SAR) Digital 4o Analog. Nef onverter (DAC) aamporafoy ie Gntrol |_s} S¥CCesive Approx imation] qi, Resister analog input | | | Velioge Binary ont Pat + SAR» succesive APPrexjmation Register —> middle - fast speed (<5MsPS) mega. samples - per- Secend —> middle resolution —» 9: /4 Bits —s this ADC aeplies a "Binary Search algorithm” —» the number of onversion steps is equed to the number of bits tn the ADC Hews it werks 1- te ADC samples the oneleg input signed and heldS the Value ina sample-and-held circuit. 2. The ADC initiclizes a digi ted ovtPut Yolue fo Zero and sets a most signifiant bit (Ms?) te 1- 3-The ADC converts the current digi ted onfPat Voduc to an analog VeHage ond Gmpores It cith the input Voltage. if the input velfege i's Beater then the digi tel ovtPrt Voltage , the corresponding Lit is set tot other wise , the bit is set fo 0. 4. The ADC repeats step 2 For the next bit, Gntinue prom the (MSB) te the least significant bit (LSIB) S- after al bifs have been defermined. the ADC oufPots the Yemem, ~ Nin Vin = aniafeg inpot Voltage er Dg = Step size” “Wee 72™) Sigitel date <7 . out put i exe step size = le my teselutin—» g-bit SAR ADC Input velfage = I 4- + MsB=1 timry [Looe ecco | : decimal Iza Vin = Dont * Step SiZe = 128 ¥ Jomy =|-28 mV ————— tt (4:23 > Vin) > (28 > 1) — Clear bit bie’ > Vin = S4 elomv = SHomy —, Gtomv <1Vv L 64 | vs bit 6 1s Kept since it smaller than 177 inpot aii aoe — > Vin= 960 my <1V _, bits is kept see anj Soon —> iP the Vohe of Vin =4V cle Let the bit =4 — the Pinel result is 1100100 —» Joc —>]eo % omy = 4-7 eB # Basi schematic £ SAR Switched -Cefacilor ADC (b-bit ADC) —> the Copa toy Velues ate binary cleighled Prom Cs C/2.~--- C/z"* (C4 C/a----C/t) sand the last tee capaciters have the same Value of C/2". — the Gnversion precess is per formed in three steps 1- sample mede 2- Hold mode 2-tedis tribution mode (the actual @nversien) 1- sample mode». — The bus switch Sp is Switched fo the input Voltage (Vin) » and S is closed fo Ground. > the apecitor switches (#55 250) ate tuned fo the commen bus IB and oll capacitors ore charged to Vin —> the foted Charge of Qin =Vin ¥20 Is stored on the Capact fers 2- Held mode :- —> Selitch Sy is open chile the Suitches (ss: $0) are camected fs ground » thet Hoy making. the Voltage ot the inverting mporator inp Vo =~Vin+ This meons that the scuitched Cap circuit olveady has q bullt-in somple-ond=held fmction ee Nin The — oH re S— wie omecte/ £ tf fe the gromd 3- Redistribution mede :- 7 ref. Ss 4c & Nea Nine i eb > aS c — the Plrst Gnvetsion step , gonnects C (the Largest apaciter) wsing Saitch Ss te the reference Velloje yep), which cerrespends te the Pul- Stole ronge CFSR) of the ADC ,ohich refers te the maximum voltage Yenge jt Con measure. —> Gpacity [ce] forms a 4:4 capacitence divider esith the remaining, Capacitors Connected fe greund « the ComParafor inpud Voltage becomes Ve =(-Vin) + Wge «This Voltage (Ve) is Gmpared with the potential Voltage of (ov) af the non-inverting input. there fore if — [Vin] > gl —S Ve <0 —> the Comparstor cuffed —» high (4) IP Min] < Yel —s Ve So —» the comparator oud Pof —s low (0) 3 IF Vy Comparatar onfpot) High , Scsitch Ss Yemains connected te Vrep Fer the rest ef Gnversion —> If Vo —slow, Ss is Switched back fo ground. —+ This process Is repented Por switches (s4 te SL), except(so) remeins Connected to ground for the entite Conversion time. —>At each step, the charge on the copaci ter is redistributed based on the Comparetor oufPut and the Sattch Connections. This determines the Value of the Corresponding, bit- __s Arter ofl bits have been determined, the conver fed digitd Yolue represents the analog inpet voltage (Vin) —» this methed dees nef require a IDAC ond uses only Copaa'tors and comparaders te Perform the anafog to digited Gnversion- ai) * ADC Vesult formatting :~ Clo-bit) —> the Je-bit A/D Conversion con be supplied in tee Prmot fing - - Let justified -right justipied lft hit? bite hit ESSS2F1 Py Ty ee Apc high registel Ape low resister * Cledete the ADC teselt in de cimel formes . —> it looks bike a normal Gnversich From binaty Pormat to decimal format: ext the reset = Wi UAL WIL) = ss right sustified ADC lew = III Il = 299 Apc high= |) —> =3 —> 2? <<8 = 3% 2°= 78 ADC resp = leo + high = 295+7é2 = 1027 So: ra 2* the ADC Value = ADC-low + (ADC_High % 245) LM35 “Temperature sensor inktfacing —s LM35 is a temperature sensor thot Can measure femperedile jin the renge of -S5¢ to I50C _s it is a 3-terminel device thet prevides an analog Voltage proper tinal te the temperedure —> the higher the tempereture, the higher is the ovlPut Volkge. > the ota onedog Veltage con be converted to digited Porm using ADC se theft a micrecntober on process I'ts LM 2 Vee. supply vellege CHV se) 35 —» the sensitivily of LM39 I's lomv / degree celsius As temperature increases, out put \ellage alse increases. We st GND eg: 250 mV —> 45 me 3 38'C @ > assuming thet the Vee= SV and vehave a fo-bit A/D system So: Step. Size = ae = 5 = 4.98 mv Te een analog Velbge = step.size * ADC. result ex: ADC. res veltoge ° ov \o23 Sv aoe x WX = 256 * So }.25 ene [x]—s the eqnivolent voltage te the ADC-resmlt X the off4 Veltege ronge of LNz5 —+ ee have 2 basiC Gnnecfichs for LM3S —» Basic temPerofute measure setup | _, pull ronge tamperodwe measure setup + Vec (4V +20v) i omy + Jomv/*c Nout = [SeeMV—a [50% = 2GemV—326T. rh 8a — (bit $v) -952 mV—» 85 Nout = Step. size % ADC. result demperohve = buf /Jomv ow 9? XHow fo imptove the reselution of ADC? —>1- ever sampling : tae multiple samples and a\erage them byether. this con effectively increase the resolution of the ADC by the number of samples faofen Breexample, if an ADC has a yesolution of [o bits an) you oversample by « factor of Jo, the cffective tesolution of the ADC will be lov bits —+ 2- Averaging : take multiple measurements of the same signal and aVerage them together. - this con effectively increase the te solution ef the AIDC, buf it is net as effective as over sumphing - For example, ifan ADC has 4 resolution of lo-bits and you ave rge le measurements together, the effective resolution of the ADC ill be jo.2 bits — > 3. Decrease skpsize: reduce the change in aneleg veltege thet atrespends to a single bit change , effectively increasing the resolution because smaller chonges in analog Voltage an be defected - —s4- Digital Post-Processing : useng Dsp techniques which Inchide interpolation , decimedion , reconstructian 7 inker polation adding new samples betaeen the existing samples -decimotion : yemoving samples Prem the signal - reaans Fraction : reconstruct ing the signal From the samples. x inter Polation ond decimedbn con Inctease the veselution of an ADC by @ factor efuod to the number of new samples added or removed: xYe Onstruction : Con increase the resolution by the facter a equal fo the number of somples used to veanstrucf the signad- > over sampling and averaging Can increase the reselotion of an ADC —> digital post prcesing an Further enhance the ADCS ferfrmence. —> oversampling Is the mest effective way Jo improve tevlution, but it Con also be expansive: —» Averaging is a less expensive opti but tet as effective as over sompling —> the best methed depends on the aPfliaticn and a\ailoble pe sourfes . Ler?) steps fer using the ADC te ferferm an A/|D Gnversion 1- congigure port :- - disable pin oufpet driver - Gnfigure pin as anelog ( disable the input buffer) 2- configure the ADC medie r- - select ADC Conversion Clock - Gnfique bltage reference ~ select ADC inpud Channef - select vesulf Format - select Acquisition delay - tun on AIDC medde 3. configure ADC interrupt (optional ) - clear ADC interrupt Plog - eneble ADC interrupt — enable peripheral interropt — crable globe interrupt obit the required acquisition Hime S- stort the Gnversion 4 - obi} For ADC @nvetsion to amplete by oné of the follocting : - Pe lling —eat ting fer the AIDC inlerrwpt T- ved ADC result B- Clear the ADC interrupt Flog ( repuired If interrupt isenobled ) ——rté~—~—O—C—C~C—CsSCizsCSC

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