Single Supply, Rail-to-Rail

Low Power, FET-Input Op Amp

Data Sheet AD824
FEATURES PIN CONFIGURATION
Single supply operation: 3 V to 30 V OUT A 1 14 OUT D
Very low input bias current: 2 pA –IN A 2 13 –IN D
Wide input voltage range +IN A 3 AD824 12 +IN D
Rail-to-rail output swing TOP VIEW
V+ 4 (Not to Scale) 11 V–
Low supply current per amplifier: 500 µA +IN B 5 +IN C
10
Wide bandwidth: 2 MHz –IN B 6 –IN C
9

00875-001
Slew rate: 2 V/µs OUT B 7 OUT C
8
No phase reversal
Figure 1. 14-Lead SOIC (R Suffix)
APPLICATIONS
Photo diode preamplifier
Battery powered instrumentation
Power supply control and protection
Medical instrumentation
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifier

GENERAL DESCRIPTION
The AD824 is a quad, FET input, single supply amplifier, The FET input combined with laser trimming provides an input
featuring rail-to-rail outputs. The combination of FET inputs that has extremely low bias currents with guaranteed offsets
and rail-to-rail outputs makes the AD824 useful in a wide below 1 mV. This enables high accuracy designs even with high
variety of low voltage applications where low input current is source impedances. Precision is combined with low noise,
a primary consideration. making the AD824 ideal for use in battery powered medical
The AD824 is guaranteed to operate from a 3 V single supply equipment.
up to ±15 V dual supplies. AD824AR-3V parametric Applications for the AD824 include portable medical
performance at 3 V is fully guaranteed. equipment, photo diode preamplifiers, and high impedance
Fabricated on Analog Devices, Inc., complementary bipolar transducer amplifiers.
process, the AD824 has a unique input stage that allows the The ability of the output to swing rail-to-rail enables designers
input voltage to safely extend beyond the negative supply and to build multistage filters in single supply systems and maintain
to the positive supply without any phase inversion or latch-up. high signal-to-noise ratios.
The output voltage swings to within 15 mV of the supplies. The AD824 is specified over the extended industrial (−40°C to
Capacitive loads to 350 pF can be handled without oscillation. +85°C) temperature range and is available in narrow 14-lead
SOIC package.

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD824 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Input Characteristics .................................................................. 12
Applications ....................................................................................... 1 Output Characteristics............................................................... 12
Pin Configuration ............................................................................. 1 Applications Information .............................................................. 13
General Description ......................................................................... 1 Single Supply Voltage-to-Frequency Converter ..................... 13
Revision History ............................................................................... 2 Single Supply Programmable Gain Instrumentation
Specifications..................................................................................... 3 Amplifier ..................................................................................... 13

Electrical Specifications ............................................................... 3 3 V, Single Supply Stereo Headphone Driver ......................... 14

Absolute Maximum Ratings ............................................................ 6 Low Dropout Bipolar Bridge Driver ........................................ 14

Thermal Resistance ...................................................................... 6 A 3.3 V/5 V Precision Sample-and-Hold Amplifier .............. 15

ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 16

Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 16

Theory of Operation ...................................................................... 12

REVISION HISTORY
4/15—Rev. D to Rev. E
Change to Figure 1 Caption ............................................................ 1

5/14—Rev. C to Rev. D
Updated Format .................................................................. Universal
Removed 16-Lead SOIC Package (Throughout) .......................... 1
Deleted Wafer Test Limits Section ................................................. 5
Deleted AD824 SPICE Macro-model Section ............................ 15
Changes to Ordering Guide .......................................................... 16

2/03—Rev. B to Rev. C
Deleted N Package .............................................................. Universal
Edits to General Description........................................................... 1
Edits to Absolute Maximum Ratings ............................................. 5
Edits to Ordering Guide .................................................................. 5
Edits to Figure 4 .............................................................................. 12
Edits to Figure 8 .............................................................................. 13
Updated Outline Dimensions ....................................................... 16

1/02—Rev. A to Rev. B
Edits to Electrical Specifications................................................. 2, 3
Edits to Absolute Maximum Ratings ............................................. 5
Edits to Ordering Guide .................................................................. 5
Deleted Dice Characteristics ........................................................... 5

Rev. E | Page 2 of 16
Data Sheet AD824

SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
At VS = 5.0 V, VCM = 0 V, VOUT = 0.2 V, TA = 25°C; unless otherwise noted.

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A) VOS 0.1 1.0 mV
TMIN to TMAX 1.5 mV
Input Bias Current IB 2 12 pA
TMIN to TMAX 300 4000 pA
Input Offset Current IOS 2 10 pA
TMIN to TMAX 300 pA
Input Voltage Range −0.2 +3.0 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2 V 66 80 dB
VCM = 0 V to 3 V 60 74 dB
TMIN to TMAX 60 dB
Input Impedance 1013||3.3 Ω||pF
Large Signal Voltage Gain AVO VO = 0.2 V to 4.0 V
RL = 2 kΩ 20 40 V/mV
RL = 10 kΩ 50 100 V/mV
RL = 100 kΩ 250 1000 V/mV
TMIN to TMAX, RL = 100 kΩ 180 400 V/mV
Offset Voltage Drift ΔVOS/ΔT 2 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH ISOURCE = 20 µA 4.975 4.988 V
TMIN to TMAX 4.97 4.985 V
ISOURCE = 2.5 mA 4.80 4.85 V
TMIN to TMAX 4.75 4.82 V
Output Voltage Low VOL ISINK = 20 µA 15 25 mV
TMIN to TMAX 20 30 mV
ISINK = 2.5 mA 120 150 mV
TMIN to TMAX 140 200 mV
Short Circuit Limit ISC Sink/source ±12 mA
TMIN to TMAX ±10 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 100 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 70 80 dB
TMIN to TMAX 66 dB
Supply Current/Amplifier ISY TMIN to TMAX 500 600 µA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BWP 1% distortion, VO = 4 V p-p 150 kHz
Settling Time tS VOUT = 0.2 V to 4.5 V, to 0.01% 2.5 µs
Gain Bandwidth Product GBP 2 MHz
Phase Margin φo No load 50 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 16 nV/√Hz
Current Noise Density in f = 1 kHz 0.8 fA/√Hz
Total Harmonic Distortion THD f = 10 kHz, RL = ∞, AV = +1 0.005 %

Rev. E | Page 3 of 16
AD824 Data Sheet
At VS = ±15.0 V, VOUT = 0 V, TA = 25°C; unless otherwise noted.

Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A) VOS 0.5 2.5 mV
TMIN to TMAX 0.6 4.0 mV
Input Bias Current IB VCM = 0 V 4 35 pA
TMIN to TMAX 500 4000 pA
IB VCM = −10 V 25 pA
Input Offset Current IOS 3 20 pA
TMIN to TMAX 500 pA
Input Voltage Range −15 +13 V
Common-Mode Rejection Ratio CMRR VCM = −15 V to 13 V 70 80 dB
TMIN to TMAX 66 dB
Input Impedance 1013||3.3 Ω||pF
Large Signal Voltage Gain AVO VO = −10 V to +10 V;
RL = 2 kΩ 12 50 V/mV
RL = 10 kΩ 50 200 V/mV
RL = 100 kΩ 300 2000 V/mV
TMIN to TMAX, RL = 100 kΩ 200 1000 V/mV
Offset Voltage Drift ΔVOS/ΔT 2 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH ISOURCE = 20 µA 14.975 14.988 V
TMIN to TMAX 14.970 14.985 V
ISOURCE = 2.5 mA 14.80 14.85 V
TMIN to TMAX 14.75 14.82 V
Output Voltage Low VOL ISINK = 20 µA –14.985 –14.975 V
TMIN to TMAX –14.98 –14.97 V
ISINK = 2.5 mA –14.88 –14.85 V
TMIN to TMAX –14.86 –14.8 V
Short Circuit Limit ISC Sink/source, TMIN to TMAX ±8 ±20 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 100 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 15 V 70 80 dB
TMIN to TMAX 68 dB
Supply Current/Amplifier ISY VO = 0 V 560 625 µA
TMIN to TMAX 675 µA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BWP 1% distortion, VO = 20 V p-p 33 kHz
Settling Time tS VOUT = 0 V to 10 V, to 0.01% 6 µs
Gain Bandwidth Product GBP 2 MHz
Phase Margin φo 50 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 16 nV/√Hz
Current Noise Density in f = 1 kHz 1.1 fA/√Hz
Total Harmonic Distortion THD f =10 kHz, VO = 3 V rms, RL = 10 kΩ 0.005 %

Rev. E | Page 4 of 16
Data Sheet AD824
At VS = 3.0 V, VCM = 0 V, VOUT = 0.2 V, TA = 25°C; unless otherwise noted.

Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A−3 V) VOS 0.2 1.0 mV
TMIN to TMAX 1.5 mV
Input Bias Current IB 2 12 pA
TMIN to TMAX 250 4000 pA
Input Offset Current IOS 2 10 pA
TMIN to TMAX 250 pA
Input Voltage Range 0 1 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 1 V 58 74 dB
TMIN to TMAX 56 dB
Input Impedance 1013||3.3 Ω||pF
Large Signal Voltage Gain AVO VO = 0.2 V to 2.0 V;
RL = 2 kΩ 10 20 V/mV
RL = 10 kΩ 30 65 V/mV
RL = 100 kΩ 180 500 V/mV
TMIN to TMAX, RL = 100 kΩ 90 250 V/mV
Offset Voltage Drift ΔVOS/ΔT 2 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH ISOURCE = 20 µA 2.975 2.988 V
TMIN to TMAX 2.97 2.985 V
ISOURCE = 2.5 mA 2.8 2.85 V
TMIN to TMAX 2.75 2.82 V
Output Voltage Low VOL ISINK = 20 µA 15 25 mV
TMIN to TMAX 20 30 mV
ISINK = 2.5 mA 120 150 mV
TMIN to TMAX 140 200 mV
Short Circuit Limit ISC Sink/source ±8 mA
ISC Sink/source, TMIN to TMAX ±6 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 100 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V, 70 dB
TMIN to TMAX 66 dB
Supply Current/Amplifier ISY VO = 0.2 V, TMIN to TMAX 500 600 µA
DYNAMIC PERFORMANCE
Slew Rate SR RL =10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BWP 1% distortion, VO = 2 V p-p 300 kHz
Settling Time tS VOUT = 0.2 V to 2.5 V, to 0.01% 2 µs
Gain Bandwidth Product GBP 2 MHz
Phase Margin φo 50 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 16 nV/√Hz
Current Noise Density in 0.8 fA/√Hz
Total Harmonic Distortion THD f = 10 kHz, RL = ∞, AV = +1 0.01 %

Rev. E | Page 5 of 16
AD824 Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 4.
Parameter1 Rating Table 5. Thermal Resistance
Supply Voltage ±18 V Package Type θJA1 θJC Unit
Input Voltage −VS − 0.2 V to +VS 14-Lead SOIC (R) 120 36 °C/W
Differential Input Voltage ±30 V 1
θJA is specified for the worst case conditions, that is, θJA is specified for device
Output Short Circuit Duration to GND Indefinite soldered in circuit board for SOIC package.
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C ESD CAUTION
Lead Temperature Range (Soldering 60 sec) 300°C
1
Absolute maximum ratings apply to packaged parts unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

VCC

I5 I6
R1 R2 Q18 Q29
R9

Q21 Q27
Q4 Q6
C3
J1 J2 Q5
+IN Q19 Q20
Q7 R7

C4
R13 R15 Q22 Q23
C2 VOUT
–IN

Q24 Q25
Q8
C1
Q2 Q3
Q31

R12 R14 Q28 Q26

R17
I1 I2 I3 I4
00875-002

VEE

Figure 2. Simplified Schematic of 1/4 AD824

Rev. E | Page 6 of 16
Data Sheet AD824

TYPICAL PERFORMANCE CHARACTERISTICS

VS = ±15V VS = 5V
80 NO LOAD 80 NO LOAD

60 60
GAIN (dB)

GAIN (dB)
40 40

45 45

PHASE (Degrees)
PHASE (Degrees)
20 90 20 90

135 135

0 180 0 180

100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M

FREQUENCY (Hz) FREQUENCY (Hz)

100 100
90 90

10 10
0% 0%
00875-003

00875-005
50mV 1µs 50mV 1µs

Figure 3. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, Figure 5. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V,
No Load No Load

VS = ±15V VS = 5V
80 CL = 100pF CL = 220pF
60

60 40

PHASE (Degrees)
45
GAIN (dB)

GAIN (dB)

40 20 90

45
PHASE (Degrees)

135

20 90 0 180

135

0 180 –20

100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M

FREQUENCY (Hz) FREQUENCY (Hz)

100
100
90
90

10 10
0% 0%
00875-004

00875-006

50mV 1µs 50mV 1µs

Figure 4. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, Figure 6. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V,
CL = 100 pF CL = 220 pF

Rev. E | Page 7 of 16
AD824 Data Sheet

VS = 3V
60 NO LOAD

40 t 9.950µs

PHASE (Degrees)
45 100
GAIN (dB)

90

20 90

135

0 180

10
0%

–20
5V 2µs

1k 10k 100k 1M 10M

FREQUENCY (Hz)

t 10.810µs

100 100
90 90

10 10
0% 0%
00875-007

00875-009
50mV 1µs 5V 2µs

Figure 7. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V, Figure 9. Slew Rate, RL = 10 kΩ
No Load

100
VS = 3V
90
60 CL = 220pF

VOUT
40
PHASE (Degrees)

45
GAIN (dB)

10
0%
90

00875-010
20
5V 100µs
135

0 180 Figure 10. Phase Reversal with Inputs Exceeding Supply by 1 V

0.8
–20

0.7
1k 10k 100k 1M 10M
FREQUENCY (Hz) 0.6
OUTPUT TO RAIL (V)

0.5

0.4
100
90 SOURCE
0.3

0.2
SINK
0.1
10
0%
0
00875-008

00875-011

50mV 1µs 1µ 5µ 10µ 50µ 100µ 500µ 1m 5m 10m

LOAD CURRENT (A)
Figure 8. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V, Figure 11. Output Voltage to Supply Rail vs. Sink and Source Load Currents
CL = 220 pF

Rev. E | Page 8 of 16
Data Sheet AD824
14
COUNT = 60

12

10

NUMBER OF UNITS
3V ≤ VS ≤ ±15V
8
NOISE DENSITY (nV/√Hz)

60
6

40
4

20 2

00875-015
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

00875-012
5 10 15 20 OFFSET VOLTAGE DRIFT (µV/°C)
FREQUENCY (kHz)

Figure 12. Voltage Noise Density Figure 15. TC VOS Distribution, −55°C to +125°C, VS = 5 V, 0 V

0.1 150
RL = ∞ VS = 5V, 0V
AV = +1
125

INPUT OFFSET CURRENT (pA)

VS = +3V 100
0.01
THD + N (%)

75
VS = +5V

50
VS = ±15V
0.001
25

0.0001 –25
00875-013

00875-016
20 100 1k 10k 20k –60 –40 –20 0 20 40 60 80 100 120 140
FREQUENCY (Hz) TEMPERATURE (°C)

Figure 13. Total Harmonic Distortion Figure 16. Input Offset Current vs. Temperature

280 100k
COUNT = 860 VS = 5V, 0V

240
10k
INPUT BIAS CURRENT (pA)

200
NUMBER OF UNITS

1k

160
100
120

10
80

1
40

0 0.1
00875-014

00875-017

–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 20 40 60 80 100 120 140
OFFSET VOLTAGE (mV) TEMPERATURE (°C)

Figure 14. Input Offset Distribution, VS = 5 V, 0 V Figure 17. Input Bias Current vs. Temperature

Rev. E | Page 9 of 16
AD824 Data Sheet
120 1k

100
COMMON-MODE REJECTION (dB)

INPUT VOLTAGE NOISE (nV/√Hz)

80 100

60

40 10

20

0 1

00875-018

00875-021
10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 18. Common-Mode Rejection vs. Frequency Figure 21. Input Voltage Noise Spectral Density vs. Frequency

–40 120

100

POWER SUPPLY REJECTION (dB)

–60
80
THD (dB)

–80 60

40
–100
20

–120 0
00875-019

00875-022
100 1k 10k 100k 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 19. THD vs. Frequency, 3 V rms Figure 22. Power Supply Rejection vs. Frequency

100 100 30

80 80 25
PHASE MARGIN (Degrees)
OPEN-LOOP GAIN (dB)

OUTPUT VOLTAGE (V)

60 60 20
±15V

40 40 15

3V, 0V
20 20 10

0 0 5

–20 –20 0
00875-020

00875-023

10 100 1k 10k 100k 1M 10M 1k 3k 10k 30k 100k 300k 1M

FREQUENCY (Hz) INPUT FREQUENCY (Hz)

Figure 20. Open-Loop Gain and Phase vs. Frequency Figure 23. Large Signal Frequency Response

Rev. E | Page 10 of 16
Data Sheet AD824
–80

–90

–100
CROSSTALK (dB)

5V 5µs
–110
100
1 TO 4 90

–120

1 TO 2 1 TO 3
–130

10

–140 0%

00875-024

00875-027
10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 24. Crosstalk vs. Frequency Figure 27. Large Signal Response

10k 2750

VS = ±15V
2500
1k
OUTPUT IMPEDANCE (Ω)

SUPPLY CURRENT (µA)

2250
100

2000
VS = +3V, 0V
10
1750

1
1500

0.1
1250

0.01 1000
00875-025

00875-028
10 100 1k 10k 100k 1M 10M –60 –40 –20 0 20 40 60 80 100 120 140
FREQUENCY (Hz) TEMPERATURE (°C)

Figure 25. Output Impedance vs. Frequency, Gain = +1 Figure 28. Supply Current vs. Temperature

1k
VS = ±15V
VS = 3V, 0V
OUTPUT SATURATION VOLTAGE (mV)

100

20mV 500ns
VOL – VS
100
90

10 VS – VOH

10
0% 1
00875-029
00875-026

0.01 0.1 1 10
LOAD CURRENT (mA)

Figure 26. Small Signal Response, Unity Gain Follower, 10 kΩ||100 pF Load Figure 29. Output Saturation Voltage

Rev. E | Page 11 of 16
AD824 Data Sheet

THEORY OF OPERATION
INPUT CHARACTERISTICS positive supply by more than 300 mV or if an input voltage will
be applied to the AD824 when ±VS = 0 V. The amplifier will be
In the AD824, n-channel JFETs are used to provide a low offset, damaged if left in that condition for more than 10 seconds. A
low noise, high impedance input stage. Minimum input 1 kΩ resistor allows the amplifier to withstand up to 10 V of
common-mode voltage extends from 0.2 V below −VS to 1 V continuous overvoltage and increases the input voltage noise by
less than +VS. Driving the input voltage closer to the positive a negligible amount.
rail causes a loss of amplifier bandwidth.
Input voltages less than −VS are a completely different story. The
The AD824 does not exhibit phase reversal for input voltages up amplifier can safely withstand input voltages 20 V below the
to and including +VS. Figure 30a shows the response of an −VS as long as the total voltage from the +VS to the input termi-
AD824 voltage follower to a 0 V to 5 V (+VS) square wave input. nal is less than 36 V. In addition, the input stage typically maintains
The input and output are superimposed. The output tracks the picoamp level input currents across that input voltage range.
input up to +VS without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output waveform. OUTPUT CHARACTERISTICS
For input voltages greater than +VS, a resistor in series with the The unique bipolar rail-to-rail output stage of the AD824
noninverting input prevents phase reversal at the expense of swings within 15 mV of the positive and negative supply
greater input voltage noise. This is illustrated in Figure 30b. voltages. The approximate output saturation resistance of the
AD824 is 100 Ω for both sourcing and sinking. This can be used
1V 2µs
to estimate output saturation voltage when driving heavier
100
90 current loads. For instance, the saturation voltage is 0.5 V from
either supply with a 5 mA current load.
For load resistances over 20 kΩ, the input error voltage of the
AD824 is virtually unchanged until the output voltage is driven
10 to 180 mV of either supply.
GND 0%

1V
If the output of the AD824 is overdriven to saturate either of the
output devices, the amplifier will recover within 2 μs of its input
(a) returning to the amplifier’s linear operating region.
1V 1V 10µs Direct capacitive loads will interact with the amplifier’s effective
100
output impedance to form an additional pole in the amplifier’s
+VS 90
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 6 and Figure 8 show the
pulse response of the AD824 as a unity gain follower driving
10 220 pF. Configurations with less loop gain, and as a result less
GND 0%
loop bandwidth, will be much less sensitive to capacitance load
1V
effects. Noise gain is the inverse of the feedback attenuation
(b) factor provided by the feedback network in use.

RP
5V Figure 31 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component
VIN
VOUT
values, the circuit drives 5,000 pF with a 10% overshoot.
00875-030

+VS
0.01µF
8

Figure 30. (a) Response with RP = 0; VIN from 0 V to +VS; 1/4 100Ω
(b) VIN = −200 V to + VS + 200 mV; VOUT = 0 V to + VS; RP = 49.9 kΩ VIN AD824
0.01µF VOUT
Because the input stage uses n-channel JFETs, input current 4
CL
during normal operation is positive; the current flows out from –VS

the input terminals. If the input voltage is driven more positive

20pF
than +VS − 0.4 V, the input current reverses direction as internal
00875-031

device junctions become forward biased. This is illustrated in 20kΩ

Figure 10. Figure 31. Extending Unity Gain Follower Capacitive Load Capability
Beyond 350 pF
Use a current-limiting resistor in series with the input of the
AD824 if there is a possibility of the input voltage exceeding the
Rev. E | Page 12 of 16
Data Sheet AD824

APPLICATIONS INFORMATION
SINGLE SUPPLY VOLTAGE-TO-FREQUENCY Table 6. AD824 In Amp Performance
CONVERTER Parameter VS = 3 V, 0 V VS = ±5 V
The circuit shown in Figure 32 uses the AD824 to drive a low CMRR 74 dB 80 dB
power timer, which produces a stable pulse of width, t1. The Common-Mode Voltage Range −0.2 V to +2 V −5.2 V to +4 V
positive going output pulse is integrated by R1 and C1 and used 3 dB BW
as one input to the AD824, which is connected as a differential G = 10 180 kHz 180 kHz
integrator. The other input (nonloading) is the unknown G = 100 18 kHz 18 kHz
voltage, VIN. The AD824 output drives the timer trigger input, tSETTLING
closing the overall feedback loop. 2 V Step (VS = 0 V, 3 V) 2 μs
10V 5 V (VS = ± 5 V) 5 μs
U4
REF02 Noise @ f = 1 kHz
C5
0.1µF 2 VREF = 5V G = 10 270 nV/√Hz 270 nV/√Hz
6
G = 100 2.2 μV/√Hz 2.2 μV/√Hz
3 5 RSCALE ** CMOS OUT2
10kΩ 74HCO4 C3
0.1µF
4 U3B U3A
4 3 2 1 5µs
OUT1
U2 100
CMOS 555 90

R2 U1 R3* 4 8
499kΩ C1
116kΩ R V+
1% 0.01µF
2% 6 THR 3
R1 1/4 OUT
499kΩ 2 TR
1% AD824 5
7 DIS CV 10
C6 0%
390pF GND

00875-033
0V TO 2.5V 5%
FULL SCALE 1 1V
C2 (NPO) C4
0.01µF 0.1µF
2%
Figure 33. Pulse Response of In Amp to a 500 mV p-p Input Signal;
VS = 5 V, 0 V; Gain = 10
NOTES
fOUT = VIN/(VREF × t1), t1 = 1.1 × R3 × C6 = 25kHz fS AS SHOWN.
R1 R2 R3 R4 R5 R6
* = 1% METAL FILM, <50ppm/°C TC 90kΩ 9kΩ 1kΩ 1kΩ 9kΩ 90kΩ OHMTEK
00875-032

** = 10%, 20T FILM, <100ppm/°C TC PART #1043

VREF
t1 = 33µs FOR fOUT = 20kHz @ VIN = 2.0V

Figure 32. Single Supply Voltage-to-Frequency Converter

G = 10 G = 100 G = 100 G = 10
Typical AD824 bias currents of 2 pA allow MΩ range source
impedances with negligible dc errors. Linearity errors of 0.01% +VS

full scale can be achieved with this circuit. This performance is 0.1µF
2 6
obtained with a 5 V single supply, which delivers less than 3 mA 1/4 1 1/4 7
to the entire circuit. RP
1kΩ 3
AD824
5
AD824
VOUT
VIN1 11
RP
SINGLE SUPPLY PROGRAMMABLE GAIN VIN2
1kΩ

INSTRUMENTATION AMPLIFIER R6
(G = 10) VOUT = (VIN1 – VIN2)(1 + ) + VREF
R4 + R5
The AD824 can be configured as a single supply instrumenta-
R5 + R6
tion amplifier that is able to operate from single supplies down (G = 10) VOUT = (VIN1 – VIN2)(1 + ) + VREF
00875-034

R4
to 5 V or dual supplies up to ±15 V. AD824 FET inputs bias FOR R1 = R6, R2 = R5 AND R3 = R4

currents of 2 pA minimize offset errors caused by high Figure 34. A Single Supply Programmable Instrumentation Amplifier
unbalanced source impedances.
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of
5 ppm/°C.

Rev. E | Page 13 of 16
AD824 Data Sheet
3 V, SINGLE SUPPLY STEREO HEADPHONE DRIVER LOW DROPOUT BIPOLAR BRIDGE DRIVER
The AD824 exhibits good current drive and THD + N The AD824 can be used for driving a 350 Ω Wheatstone bridge.
performance, even at 3 V single supplies. At 1 kHz, total Figure 36 shows one half of the AD824 being used to buffer the
harmonic distortion plus noise (THD + N) equals −62 dB AD589—a 1.235 V low power reference. The output of 4.5 V
(0.079%) for a 300 mV p-p output signal. This is comparable can be used to drive an ADC front end. The other half of the
to other single supply op amps that consume more power and AD824 is configured as a unity-gain inverter and generates the
cannot run on 3 V power supplies. other bridge input of –4.5 V. Resistors R1 and R2 provide a
In Figure 35, each channel’s input signal is coupled via a 1 µF constant current for bridge excitation. The AD620 low power
Mylar capacitor. Resistor dividers set the dc voltage at the instrumentation amplifier is used to condition the differential
noninverting inputs so that the output voltage is midway output voltage of the bridge. The gain of the AD620 is pro-
between the power supplies (1.5 V). The gain is 1.5. Each half of grammed using an external resistor RG and determined by:
the AD824 can then be used to drive a headphone channel. A 49.4 k Ω
G= +1
5 Hz high-pass filter is realized by the 500 µF capacitors and the RG
headphones, which can be modeled as 32 Ω load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz to 20 kHz) are delivered to the headphones. +VS

3V 49.9kΩ
R1
+1.235V 20Ω
1/4
0.1µF 0.1µF TO ADC
1µF 95.3kΩ AD589 AD824 REFERENCE INPUT
MYLAR
CHANNEL 1 26.4kΩ, 1% +VS
1/4
47.5kΩ AD824 10kΩ 350Ω
500µF 1% 350Ω 3
7
6
95.3kΩ L 350Ω 350Ω RG AD824
4.99kΩ
10kΩ 5
10kΩ 2
HEADPHONES 4
1%
32Ω IMPEDANCE VREF
10kΩ 10kΩ
1% –VS
R 1/4
–4.5V +VS +5V
4.99kΩ AD824
R2 0.1µF 1µF
1µF 20Ω GND
47.5kΩ 1/4

00875-036
MYLAR AD824 –VS 0.1µF 1µF
500µF
00875-035

CHANNEL 2 –VS –5V

Figure 36. Low Dropout Bipolar Bridge Driver

Figure 35. 3 Volt Single Supply Stereo Headphone Driver

Rev. E | Page 14 of 16
Data Sheet AD824
A 3.3 V/5 V PRECISION SAMPLE-AND-HOLD A design consideration in sample-and-hold circuits is voltage
AMPLIFIER droop at the output caused by op amp bias and switch leakage
currents. By choosing an JFET op amp and a low leakage CMOS
In battery-powered applications, low supply voltage operational
switch, this design minimizes droop rate error to better than
amplifiers are required for low power consumption. Also, low
0.1 µV/µs in this circuit. Higher values of CH will yield a lower
supply voltage applications limit the signal range in precision
droop rate. For best performance, CH and C2 should be
analog circuitry. Circuits like the sample-and-hold circuit
polystyrene, polypropylene or Teflon capacitors.
shown in Figure 37 illustrate techniques for designing precision
analog circuitry in low supply voltage applications. To maintain These types of capacitors exhibit low leakage and low dielectric
high signal-to-noise ratios (SNRs) in a low supply voltage absorption. Additionally, 1% metal film resistors were used
application requires the use of rail-to-rail, input/output throughout the design.
operational amplifiers. This design highlights the ability of the In the sample mode, SW1 and SW4 are closed, and the output is
AD824 to operate rail-to-rail from a single 3 V/5 V supply, with VOUT = −VIN. The purpose of SW4, which operates in parallel
the advantages of high input impedance. The AD824, a quad with SW1, is to reduce the pedestal, or hold step, error by
JFET-input op amp, is well suited to sample-and-hold circuits injecting the same amount of charge into the noninverting
due to its low input bias currents (3 pA, typical) and high input input of A3 that SW1 injects into the inverting input of A3. This
impedances (3 × 1013 Ω, typical). The AD824 also exhibits very creates a common-mode voltage across the inputs of A3 and is
low supply currents so the total supply current in this circuit is then rejected by the CMR of A3; otherwise, the charge injection
less than 2.5 mA. from SW1 creates a differential voltage step error that appears at
3.3V/5V 3.3V/5V
VOUT. The pedestal error for this circuit is less than 2 mV over
R1 AD824 0.1µF the entire 0 V to 3.3 V/5 V signal range. Another method of
50kΩ
3 4 reducing pedestal error is to reduce the pulse amplitude applied
1
2
A1 to the control pins. To control the ADG513, only 2.4 V are
R2 FALSE GROUND (FG)
50kΩ
11
R4 required for the on state and 0.8 V for the off state. If possible,
2kΩ
use an input control signal whose amplitude ranges from 0.8 V
3.3V/5V
13
to 2.4 V instead of a full range 0 V to 3.3 V/5 V for minimum
15 14
ADG513 pedestal error.
SW2 16
R5
2kΩ 10 11
Other circuit features include an acquisition time of less than
AD824 SW3 9 3 µs to 1%; reducing CH and C2 will speed up the acquisition
5
FG CH
500pF
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
7 2 3
A2
6 SW1 1
10 is 80 kHz.
8
A3 +
9
V The ADG513 was chosen for its ability to work with 3 V/5 V
7 6 – OUT
SW4 8
AD824 supplies and for having normally open and normally closed
AD824 4 5
C2 precision CMOS switches on a dielectrically isolated process.
FG 500pF
12 SW2 is not required in this circuit; however, it was used in
14
SAMPLE/ A4 FG parallel with SW3 to provide a lower RON analog switch.
00875-037

13
HOLD

Figure 37. 3.3 V/5.5 V Precision Sample-and-Hold Circuit

In many single supply applications, the use of a false ground

generator is required. In this circuit, R1 and R2 divide the
supply voltage symmetrically, creating the false ground voltage
at one-half the supply. Amplifier A1 then buffers this voltage
creating a low impedance output drive. The sample-and-hold
circuit is configured in an inverting topology centered around
this false ground level.

Rev. E | Page 15 of 16
AD824 Data Sheet

OUTLINE DIMENSIONS
8.75 (0.3445)
8.55 (0.3366)

14 8
4.00 (0.1575) 6.20 (0.2441)
1
3.80 (0.1496) 7 5.80 (0.2283)

1.27 (0.0500) 0.50 (0.0197)

BSC 45°
1.75 (0.0689) 0.25 (0.0098)
0.25 (0.0098) 8°
1.35 (0.0531)
0.10 (0.0039) 0°
COPLANARITY SEATING
0.10 0.51 (0.0201) 0.25 (0.0098) 1.27 (0.0500)
PLANE
0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

060606-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 38. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD824AR-14 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824AR-14-3V −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824AR-14-3V-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824AR-14-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824AR-14-REEL7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-3V −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-3V-RL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-REEL7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
1
Z = RoHS Compliant Part.

©2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00875-0-4/15(E)

Rev. E | Page 16 of 16