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MATH MODEL ON ERROR DETECTION AND CORRECTION

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 07 Issue: 05 | May 2020 www.irjet.net p-ISSN: 2395-0072

MATH MODEL ON ERROR DETECTION AND CORRECTION

Mukunda D S1, Poornachandra prakash2, Manoj kumar P A3, Pavan kalyan V4, Prof.Pavan
kumar E5

1-5Department of Electronics and Communication, Sai Vidya Institute of Technology, Bengaluru, India

----------------------------------------------------------------------***---------------------------------------------------------------------
Abstract
Communication is a powerful tool that aids us to connect
with people. In today’s world digital communication has
made our life much easier. But in the process of digital
communication, the messages transmitted are often
vulnerable to noise. In other words, the information signal
sent from the transmitter gets corrupted even before
receiving back at the receiver. Hence the receiver must be
Fig 1: Error in digital system
capable of detecting the random error bits added to the
original data. These random error bits are due to
In digital transmission these errors are called as bit
environmental interferences and physical defects or even
errors. These bit errors are likely to occur in the memory
due to technology scaling and variations in parameters
of the digital circuits. Memories are the most important
and noise levels.
component for storing as well as retrieving any digital
data that are needed at particular time (Shobha & Kavya,
This paper describes mathematical error
2015, p. 1). Types of embedded memory include ROM,
detection/correction models (techniques) that can be
SRAM, DRAM, flash memory etc. Based on error
utilized to protect the system against various types of
impacting on memory, there are 2 types,
errors. These detection/correction models have their own
performance, complexity levels and requires a lot of effort
 Soft errors
to achieve the maximum efficiency in the digital
transmission. This paper enumerates many error detection  Hard errors
and correction math models that allow reliable delivery of
Soft errors are transient and consist of a bit flip in the
digital data across unreliable communication channels.
memory without permanent effect on the storing
capacity to store the data.
Keywords: bit flip, errors memory, error detection and These errors are typically caused by high energy
correction, parity, hamming code. neutrons generated by collision of cosmic rays with
atoms in the atmosphere. The error is soft because the
circuit/device is not permanently damaged by this
INTRODUCTION radiation. The frequency of soft error occurrence soft
error rate depends on the way in which the device is
In most cases, we assume that the digital circuits are manufactured and the location in which they operate.
more immune to noise and they process the information
correctly. But there are interferences which affects Errors that persist in the memory are called hard errors.
occasionally the value of the digital signal. In digital If the device/memory is affected by these types of hard
system, the analog signals will manipulate themselves errors, it loses all its capability to store the data and can
into digital bits they are often called as Digital stream. no longer be used for read/write operation. A read
These interferences which arise will change the value of operation will always yield to 0 or 1 value regardless the
the sequence from logic 0 to 1 or from logic 1 to logic 0. previous bit value written. These errors are caused by
We sometimes prosaically call this a bit flip (Ashenden, the manufacturing defects or from the electrical
2008, p. 58) . This change in the position of the bits leads malfunctions after prolonged use.
to catastrophic errors in the output.
If signal is carrying binary encoded data, any change, can
During transmission, when the input data is not matched alter the meaning of the data (Shobha & Kavya, 2015, p.
with the output data, it is termed as error. 1). Based on this change of data during transmission,
there are two types of errors,
Fig below, illustrates the occurrence of error in the  Single bit error
encoder and decoder of the digital system:  Burst error

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Single bit error means only one bit is changed from bit 0 constitute to a code and are called Error detecting codes
to bit 1 or from bit 1 to bit 0 (“Computer Network | Error and the technique is called Error detection.
Detection - javatpoint,” n.d.). Occurrence of these errors
is parallel communication as data is transferred bitwise Some popular techniques for error detection are:
in single line and that single line can be corrupted. 1.One dimensional Parity check
2. Two-dimensional Parity check
Fig below shows occurrence of single burst error: 3. Cyclic redundancy check

1. One dimensional Parity check

One technique that is commonly used for detecting error

is parity, which deals with counting the number 1’s
present in a code word. Parity error checking deals with
increasing the code length by adding one extra bit, called
the parity bit. In the even parity scheme, the parity bit in
each code word is set to 0 or 1 to make sure that the total
number of 1 bits is even (For example, if the original
Fig 2: Single bit error code word is 1110, the augmented code word is 11101)
whereas odd parity scheme sets the parity bit to ensure
Burst error is the change in multiple/set of bits of data that the total number of 1 bits is odd, for example, if the
sequence from transmitter to receiver. These types of original code word is 1010, the augmented code word is
errors are common in both serial and parallel 10101 (Ashenden, 2008, p. 60), (Subiya Yaseen, Hussain
communication. Burst error is calculated from first bit Ahmed, & Kehkeshan Jallal , 2013, pp. 1–3).
change to last bit change (2019).
In an even parity scheme, valid code words have even
Fig below illustrates burst error occurrence: parity, and invalid code words have odd parity. If the
error causes a 0 bit to change to 1, the number of 1 bit is
increased by one, and the parity becomes odd. Similarly,
if error changes a 1 bit to 0, the number of 1 bit is
decreased by one, and parity becomes odd. So in order to
check whether a bit has flipped or not, we simply count
the number of 1 bits, including the parity bit. If the count
obtained is odd, parity has been reversed (Ashenden,
2008, p. 60).Indicating that an error has occurred.
Fig 3: Burst error
This scheme below shows the illustration of parity
With this knowledge, the errors can exist in multiple checking:
ways and affect the process of transmission. Especially
the memory is more susceptible to bit errors than logic
circuits using flip-flops, registers for storage.

At last it becomes more common and important to

include some error detection and correction techniques
both in memory and logic circuits to overcome these
errors.

ERROR DETECTION TECHNIQUES

Memories are more vulnerable to bit errors than using

flip-flops and registers for storage, due to the storage
density and how long the data stored in memories, it is
Fig 4: One dimensional parity check
more obvious to include some techniques of error
detection in memory circuits than in flip-flops and
registers. The circuit which adds a parity bit is called Parity
generator. The circuit which verifies the parity is called
Parity checker.
The process of identifying the errors that are present in
the transmitted data is called error detection. We use Here are some of the example code words illustrating
even and odd parity:
some redundancy bits to find these errors, by adding to
the data before it is transmitted. These redundancy bits

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Fig 5: Even and Odd parity

Fig 8: Parity checking in DRAM

2. Two-dimensional Parity check

In a simple parity check, the parity check bits are

calculated only for each row. In two-dimensional parity
check technique we calculate parity bits for both rows
and also for columns then, both are sent along with the
data. At the receiver we compare the sent and received
parity bits.

The figure below illustrates the same:

Fig 6: Parity Checker [1], Fig 7: Parity generator [1]

In DRAM memory systems the use of parity memory is to

Fig 9: Two dimensional parity check
provide single-bit error detection capability.

Figure below illustrates the generation of a parity bit for Drawbacks of parity
data written to DRAM: parity, indicating either an even
or an odd number of ‘1’ bits in the data [2] The problem of using parity technique to check for
errors is that it only allows us to detect a single bit flip in
a code word, it does not allow us to identify which bit is
flipped, nor does it allow us to detect an even number of
bit flips (Ashenden, 2008, p. 240). If the interference
(error) flips two, four, six, or any even number of bits
parity is preserved, so we miss that error (Ashenden,
2008, p. 240). However, in practical applications, the
probability of changing of multiple bits is extremely less.
If the application requires only detecting the error,
parity method is most suitable.
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Volume: 07 Issue: 05 | May 2020 www.irjet.net p-ISSN: 2395-0072

3. Cyclic Redundancy Check (CRC)

These types of codes are used for error detection and

error correction and also for encoding (2019). Consider a
linear block code (n, K), k is the length of the message
(the number of information bits). n indicates the total
length of the transmitted message after adding check
bits. They can be easily designed using shift-registers
with feedback connections. With every cyclic shift we
can generate a new code word.

CRC Code Generation

This data unit has occurred with a remainder and
 CRC is based on binary division (“Error Detection therefore rejected.
in Computer Networks,” 2019).
 CRC involves the process of adding redundancy
bits called ‘redundancy check bits’ to the end of the These CRC techniques are exclusively in digital
data and make the resulting data exactly divisible communication systems. CRC codes are capable of
without any remainder. providing high and effective level of protection.

We can add some more zeros to the original data based

For one bit and two bit errors, the probability of CRC is
on the requirement of check bits. The new binary data
100 %, burst error of length n – 1, has the probability of
sequence is divided (modulo 2- division) with a new
CRC error detecting 100 %, burst error of length n + 1,
code of the length n + 1, here n represents the number of
has the probability of error detecting 1 – (1/2) n-1, burst
check bits which is added to the original data. If any
error of length greater than n – 1, the probability of
reminder, we add it to the dividend to get a new cyclic
error detecting is 1 – (1/2) n (2019).
code. The generated code word is completely divisible
that is used in generation of code (2019).
ERROR CORRECTION TECHNIQUES
 If we do not get any remainder, the data unit is
The basic error correction techniques consists of two
presumed to be correct and is accepted.
types (2019), they are:
 If any remainder occurs, we conclude that the data is 1. Single bit error correction
corrupted and it is rejected. 2. Burst error correction

The methodology is described as below: Single bit error correction is a method of correction
single bit error.
Burst error correction is a method of correction of burst
error.

I. Alpha Numeric Codes

These codes represent alphabets, numbers, punctuation

mark and mathematical symbol. They are implemented
in input output devices like printers, keyboard and
monitor etc.

The types of alphanumeric codes (2019) are:

1. Morse Code
2. Baudot code
3. Hollerith code
4. ASCII Code
5. EBCDIC Code
Fig 10: Cyclic Redundancy Check
6. Unicode Code
Example for CRC 1. Morse code
Even before computer and digital electronics era, Morse
code was very popular code. Morse code is used in
telecommunication as a telegraphic code.

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 07 Issue: 05 | May 2020 www.irjet.net p-ISSN: 2395-0072

2. Baudot code
This code is invented in 1870 by Emile Baudot; this code
uses 5 elements to represent the alphabet. This is most
commonly used in teleprinters.

3. Hollerith code
This was developed by Herman Hollerith in 1896. It is
also called as punched card codes, because the 12-bit
code is punched on card for transmitting information.

4. ASCII Code
American Standard Code for Information Interchange
(1&1 IONOS Inc., 2020) is most commonly used
alphanumeric code. This was invented in 1967. ASCII
code is 7-bit code, it has 128 characters. They are 26 Fig 12: Hamming encoder and Decoder
lower case letter, 26 upper case letter, 33 special
characters and symbols, 33 control characters and 10 Hamming codes are calculated using matrices. These
digits. matrices are code generator matrix (G), parity matrix (P)
and parity check matrix (H).
5. EBCDIC Code
Extended Binary Coded Decimal Interchange code was Generator matrix (G): It is a matrix whose rows form
first developed by the company called IBM. It is 8-bit basics for a linear code (Hamming code).
code, it can represent 256 characters. They are 26 lower
case letter, 26 upper case letter, 33 special characters Parity matrix (P): It is a matrix which describes the linear
and symbols, 33 control characters and 10 digits. In relations that the code must satisfy.
EBCDIC code numbers are represented by 8421.
Parity check matrix (H): The parity matrix along with the
6. UNICODE Identity matrix is termed as parity check matrix.
The drawback of ASCII code and EBCDI codes are, they
do not suit to all languages and they do not have enough The computation of Hamming codes using code
generator matrix and parity check matrix is as illustrated
characters to represent each and every data. This is
in the below example: Ex: The parity check bits of a (7, 4)
overcome by UNICODE. UNICODE uses different
characters to represent every number and it is LBC are given below, the data bits to be sent are 1101.
compatible with all languages and it can represent all Find the hamming code constructed at the encoder and
decoder. [3]
types of data. It is 16-bit code; it can represent 65536
different characters.

II. Hamming Code

Hamming code is used detect the error and correct it in

the data. This code uses the parity bits in the code word
that depends on number of information bits. The extra
bits added to the data sequence are called as redundancy
bits. Redundancy bits are placed at particular position to
remove the error. Sol: Given, (n, K) = (7, 4)
n= code word length;
Hamming code can correct single- and double-bit errors. K= message bits;
Basic Structure of Hamming Encoder and Decoder n-K= parity bits =7-4=3;
(Chauhan, 2016) are as shown below:
From above data we can get Generator Matrix as:

Codeword, [C] = [D]*[G]

Where D= data

G=generator matrix

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 07 Issue: 05 | May 2020 www.irjet.net p-ISSN: 2395-0072

The general form of Generator matrix is,

Where I is Identity matrix S= [1 0 0].

From the generator matrix, the parity matrix is obtained

as below, The syndrome pattern is in the 1st row of the H
transpose, which indicates that the 1st bit in received
code is corrupted. Corrected code word is [0 1 0 0 1 0
1]. Thus, data obtained is same as the data transmitted
using hamming code.

SIMULATION USING XILINX ISE DESIGN SUIT.14

From generator matrix we get parity check matrix (H):

Encoding:

The hamming codeword transmitted is [0 1 0 0 1 0 1].

Fig 13: Hamming Encoder

Decoding:

If no error during transmission then the [received

code=transmitted code.] If there is an error, then we
multiply r and to obtain syndrome pattern.

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Fig 14: Test bench Code (encoder)

Fig 15: RTL Schematic and Simulation Output

(encoder)

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Fig 16: Hamming decoder

Fig 18: RTL schematic and Simulation Output

(decoder)

CONCLUSION

Coding techniques gives us the required protection for

the information against a noise. This Error detection and
correction mechanisms are widely used today and one of
the effective techniques which exist in the world. It
reduces the effect of errors caused due to bit change. And
it always keeps the receiver in the error free version. In
this paper we have tried to illustrate all possible error
detection, correction controlling mechanisms.

Fig 17: Test bench code (Decoder)

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ACKNOWLEDGMENT

I cannot express enough thanks to my college Sai Vidya

Institute of Technology (SVIT) for their continued
support and encouragement and also I offer my sincere
appreciation for the learning opportunities provided by
Visveshwaraya Technological University (VTU).

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