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毕业设计

This document discusses implementing RS-485 communication using an HDLC protocol on an FPGA board. It introduces the RS-485 standard and describes a circuit with sending and receiving modules. The sending module packages 485 serial data using HDLC protocol. The receiving module unpackages the HDLC data and sends the 485 serial data. The design is implemented on an FPGA board using Verilog and simulated to verify data transfer over 485 serial using the HDLC protocol.

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augustodaleffe
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38 views31 pages

毕业设计

This document discusses implementing RS-485 communication using an HDLC protocol on an FPGA board. It introduces the RS-485 standard and describes a circuit with sending and receiving modules. The sending module packages 485 serial data using HDLC protocol. The receiving module unpackages the HDLC data and sends the 485 serial data. The design is implemented on an FPGA board using Verilog and simulated to verify data transfer over 485 serial using the HDLC protocol.

Uploaded by

augustodaleffe
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ABSTRACT

RS-485 serial communication mode was widely applied in multipoint communication


aspect due to its simple structure, higher communication speed, longer transmission distance
and other advantages. This paper introduced RS-485 Communication Standard firstly, and
then applied HDLC protocol to implement 485 interface circuit on the basis of 485. Finally,
it used Verilog language to take RTL level description and complete verification on FPGA
development board.
The 485 interface circuit in this paper included a sending module and a receiving module.
Functions mainly completed by the sending module were to receive 485 serial data and send
the data through HDLC protocol after being packaged. Functions mainly completed by the
receiving module were to receive the data packaged through HDLC protocol and send the
data through 485 serial after the HDLC data unpackaging was completed. In simulation
verification and FPGA debugging, the HDLC packaged data output by sending module was
also returned to HDLC receiving circuit of receiving module. Additionally, it took data
sending and receiving through 485 serial to complete simulation and FPGA verification.

Keywords: the 485 interface circuit; the HDLC protocol; Field-Programmable Gate Array;
Verilog Hardware Description Language
1

1.1
1.1.1

1.1.2
1.1.3
1.1.4

1.2
2

2.1
2.1.1

2.1.2

2.2
3

3.1

HDLC 485

485
HDLC
3.2
3.3

3.3.1

a.
b.
3.3.2

a.
b.
c.
d.

e.
a.
b.
c.
d.
e.
f.
g.
h.
3.4

3.5
3.5.1

a.
b.

c.
d.
3.5.2
3.5.3

3.5.4
4

4.2

4.3

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