School of

Electronics and Communication Engineering

Mini Project Report

on

UNIVERSAL ASYNCHRONOUS
RECEIVER AND TRANSMITTER
[UART]

By:

1. Rohit.S.Kademani USN:01FE20BEC080
2. Darshan.S.Katagihallimath USN:01FE20BEC087
3. Manoj PM USN:01FE20BEC038

Semester: V, 2022-2023
Under the Guidance of

Dr.Saroja.V.Siddamal

1
 K.L.E SOCIETY’S
KLE Technological University,
HUBBALLI-580031
2022-2023

SCHOOL OF ELECTRONICS AND COMMUNICATION

ENGINEERING

CERTIFICATE

This is to certify that project entitled “Universal Asynchronous Receiver And

Transmitter [UART]” is a bonafide work carried out by the student team of”Rohit.S.
Kademani (USN:01FE20BEC080), Darshan.S.Katagihallimath (USN:01FE20
BEC087), Manoj PM(USN:01FE20BEC038)”. The project report has been ap-
proved as it satisfies the requirements with respect to the mini project work prescribed
by the university curriculum for BE (V Semester) in School of Electronics and Commu-
nication Engineering of KLE Technological University for the academic year 2022-2023.

Dr. Saroja.V.Siddamal Dr. Nalini C. Iyer Dr.Basavaraj.S.A

Guide Head of School Registrar

External Viva:

Name of Examiners Signature with date

1.

2.

2
 ACKNOWLEDGMENT
For effective completion of ”Design of Universal Asynchronous Receiver And Transmitter” would
be unfinished without co-ordination, co-operation and collective effort of all the members.A
broad spectrum of feedback and inspiration from a variety of people is recognized in this study.

We are extremely thankful to our esteemed institute KLE TECHNOLOGICAL UNIVER-

SITY, Hubballi which has provided us an opportunity to fulfill the desire to reach our goal.

We are grateful to Dr.Nalini Iyer, Head of School of Electronics and Communication En-
gineering for facilitating us in completing this project and expanding the department’s resources.

It’s our honour to express our heartfelt gratitude to Dr.Saroja V Siddamal, project head
for her invaluable contributions, capable guidance, support, whole hearted cooperation for our
project

Finally yet importantly, we would like to thank all those either directly or indirectly made
a difference in the project.

Rohit.S.Kademani USN:01FE20BEC080
Darshan.S.Katagihallimath USN:01FE20BEC087
Manoj PM USN:01FE20BEC038

3
 ABSTRACT

Communication Protocols are a set of rules that allow two or

more communication systems to communicate data via any
medium. A controller takes input from devices like motors,
actuators, sensors etc.. and process to give expected output.One
of the hardware communication protocol is UART which utilizes
asynchronous serial communication protocol with desirable speed
and high performance. UART is an asynchronous device which
does not require clock pulse for transmiting and receiving the
data. UART is a physical device which is used in embedded and
development board for serial data transfer.UART is a complex
circuit which involves different modules such as APB(advanced
peripheral bus) for transmiting and reveiving of data from the
peripherals, Baud generator for giving tick signal for the finite
state machines to operate, Transmit and receive state machines
for transmitting and receiving of data, Data buffer to store the
data.

4
Contents

1 Introduction 9
1.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Literature survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Problem statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Application in Societal Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Project Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 System design 11
2.1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Implementation details 12
3.1 Specifications and system architecture . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 Baud generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.3 Data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Results and discussions 17

4.1 Result Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Conclusions and future scope 18

5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Future scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

References 18

5
List of Tables

6
List of Figures

2.1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Baud generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7
Chapter 1

Introduction

UART stands for Universal Asynchronous Receiver/Transmitter.It’s not a communication

protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A
UART’s main purpose is to transmit and receive serial data.A universal asynchronous
receiver-transmitter (UART) is a computer hardware device for asynchronous serial
communication in which the data format and transmission speeds are configurable.It sends
data bits one by one, from the least significant to the most significant, framed by start and
stop bits so that precise timing is handled by the communication channel.

1.1 Objectives
1. Transmission Of Data From APB Slave To The Peripherals Using Data Buffers And
Transmit State Machine(TSM).

2. Receiving Of Data From The Peripherals To APB Slave Using Data Buffers And Receive
State Machine(RSM).

3. These Two Tasks Are Done Using A Baud Generator Without Using A Master Clock(i.e,
Asynchronous).

1.2 Literature survey

This paper proposed the suitable supported device families and the core versions associated
with the release notes and the supported interfaces available with APB slave interface and
advanced high peripheral bus (APB)master memory interface along with the device utilization
and performance data for the core implemented using the devices.Memory requirements of the
FPGA memory block based on the parameter settings[1].

This paper also gives the functionl block diagram of the interface with description and the
details of the parameters on APB and other control interface signals and fixed mode of options
based on character size, parity, baud rate, fractional part of baud value.

Configuration of the registers of the coreUARTapb programmer model is discussed , which

consists of transmit data register, receive data register and three control register for storing
baud value and status register which provides the information on the status of
CoreUARTapb.The APB interface allows access to the CoreUARTapb internal registers, FIFO
and internal memory.APB interface is synchronous with clock[4].

8
 This paper has the timing diagram of the UART which is broken down into a few basic
functions transmit data, receive data and errors. Errors are based on parity error, overflow
error and framing error.Framing error is based on two modes no legacy mode and legacy mode.
In Normal(non-legacy)mode RXRDY and framing error signal are one system clock cycle
apart, framing error signal gets asserted one system clock cycle before assertion of RXRDY
signal and the framing error is cleared using read operation. In legacy mode after the assertion
of RXRDY signal the framing error signal gets asserted. when the data is available RXRDY
signal gets asserted and check for the blocks missing in the data frame and as same in the
normal mode the error is cleared using a read operation.

The paper also gives the information about testbench operation and modification for both
VHDL and verilog. The testbench is provided as bus functional model(BFM) to coreUARTapb
block that in turn is connected via serial UART interfaces.This testbench instantiates AMBA
bus functional model for APB master that controls the operation of coreUARtapb through
read and write to access internal registers.

1.3 Problem statement

Design Of Universal Asynchronous Receiver And Transmitter [UART]

1.4 Application in Societal Context

UART is primarily used by embedded systems, microcontrollers, and computers as a hardware
communication protocol between devices. UART is one of the communication protocols that is
readily available and employs just two wires for both transmission and receiving.Establishing
communication between 900-meter-distance computers. data transfer via the serial port of a
computer.The creation of baud rates for various purposes that aid in determining the rate of
data transfer Wireless data communication will be implemented by a microcontroller. GPS
and Bluetooth modules.

1.5 Project Planning

Loading of Baud Value and Data to APB slave.APB Assigns the Baud Value to Baud
Generator and loads the Data into the Transmitter Data Buffer.Baud Generator Generates
Stick to sync Transmitting and Receiving .Transmit State Machine Transmits the Data to the
peripheral Receive State Machine Receives the Data from the Peripheral Received data is
loaded into The Receiver Data Buffer.From the Receiver Data Buffer Data is received Through
APB.

9
Chapter 2

System design

2.1 Functional block diagram

Figure 2.1: Functional block diagram

10
Chapter 3

Implementation details

3.1 Specifications and system architecture

UART is designed for 30MHz clock frequency.
The baud rate at which the baud generator is working at baud rate of 9600 bits/sec.
Using
baud rate and the clock frequency we have calculated baud value which is 194 decimal(C2 hex)[3].

3.1.1 APB interface

Figure 3.1: APB interface

The Advanced Microcontroller Bus Architecture (AMBA) protocol family includes the
Advanced Peripheral Bus (APB). It defines a low-cost interface that is designed to use the

11
least amount of power and have a simple interface. Use the APB protocol to connect to
low-bandwidth peripherals that do not need the high performance of the AXI protocol because
it is not pipelined. To make it easier to integrate APB peripherals into any design flow, the
APB protocol links a signal transition to the rising edge of the clock. It requires at least two
cycles for each transfer[2].

3.1.2 Baud generator

Figure 3.2: Baud generator

It refers to the rate at which data is conveyed in the form of bits per second or signal units
per second from the transmitter to the receiver. The more quickly data can be conveyed, the
greater the baud rate. i,e. 9600 bits/sec

3.1.3 Data buffer

Figure 3.3: Data buffer

The work of the data buffer is to store the input value from the APB slave until the signal is
sent to the data buffer to give the data out to transmit state machine for transmission of data.
In our design data buffer size is of 32 bit[2].

12
3.1.4 Transmitter

Figure 3.4: Transmitter

The transmitter works only when there is a tick signal generated by the baud
generator.Transmitter takes 32 bit parallel input from the data buffer and transmits serial data
of 1bit each to apb slave.

3.1.5 Receiver

Figure 3.5: Receiver

The receiver works only when there is a tick signal generated by the baud generator.Receiver
receives a serial data from the apb slave and stores the data value in receive data buffer.
Through receive data buffer a 32 bit parallel output will come out as output.

13
3.2 Algorithm
STEP1: Loading of Baud Value and Data to APB slave
STEP2: APB Assigns the Baud Value to Baud Generator and loads the Data into the
Transmitter Data Buffer
STEP3: Baud Generator Generates Stick to sync Transmitting and Receiving
STEP4: Transmit State Machine Transmits the Data to the peripheral
STEP5: Receive State Machine Receives the Data from the Peripheral
STEP6: Received data is loaded into The Receiver Data Buffer
STEP7: From the Receiver Data Buffer Data is received Through APB

3.3 Flowchart
Transmitter flow

14
Receiver flow

15
Chapter 4

Results and discussions

4.1 Result Analysis

16
Chapter 5

Conclusions and future scope

5.1 Conclusion
UART is designed to achieve reliable serial data communication. The transmitter and
receiver module of UART are designed using FSM concept for specified baud rate Is been
successfully simulated and synthesized

5.2 Future scope

Uart is widely used for bidirectional, asynchronous serial data transmission with no clock
involved and with less hardware complexity which leads to less power consumption.

It is used to establish connection between computers that are 900 metres apart and for data
transfer to serial ports or peripherals via microcontroller boards.One of the main advantage of
uart is it uses baud generator which determines the speed of data transmission. Arduino and
raspberry pi are some of the currently used applications of uart

17
Bibliography

[1] Liakot Ali, Roslina Sidek, Ishak Aris, Alauddin Mohd Ali, and Bambang Sunaryo Suparjo.
Design of a micro-uart for soc application. Computers & Electrical Engineering,
30(4):257–268, 2004.

[2] Padmaprabha Jain and Satheesh Rao. Design and verification of advanced microcontroller
bus architecture-advanced peripheral bus (amba-apb) protocol. In 2021 Third
International Conference on Intelligent Communication Technologies and Virtual Mobile
Networks (ICICV), pages 462–467. IEEE, 2021.

[3] KB Sowmya, Shreyans Gomes, and Vishnusai Reddy Tadiparthi. Design of uart module
using asmd technique. In 2020 5th International Conference on Communication and
Electronics Systems (ICCES), pages 176–181. IEEE, 2020.

[4] Emile Jacobus Thesnaar. Development of a radiation resistant communication node for
satellite sub-systems. PhD thesis, Stellenbosch: Stellenbosch University, 2014.

18