PRINCE DR.K.

VASUDEVAN COLLEGE OF
ENGINEERING AND TECHNOLOGY
PONMAR, CHENNAI-600 127

DEPARTMENT OF ARTIFICIAL INTELLIGENCE AND DATA SCIENCE

ENGINEERING

CS3351 – Digital Principles and Computer Organization Laboratory

NAME :
REGISTER NO :
YEAR/SEMESTER :
BRANCH :
 INDEX

Ex. Date Name of Experiment Page No Signature

No.
1a STUDY OF LOGIC GATES
VERIFICATION OF BOOLEAN
THEOREMS USING DIGITAL
1b LOGIC GATES
DESIGN AND IMPLEMENTATION OF
2 COMBINATIONAL CIRCUITS
USING GATES FOR ARBITRARY
FUNCTIONS

DESIGN OF ADDER AND

3a SUBTRACTOR USING LOGIC GATES

DESIGN OF 4-BIT ADDER AND

3b SUBTRACTOR USING IC 7483

DESIGN AND IMPLEMENTATION OF

4
CODE CONVERTORS
5a DESIGN AND IMPLEMENTATION OF
BCD ADDER

DESIGN AND IMPLEMENTATION OF

5b
ENCODER AND DECODER
DESIGN AND IMPLEMENTATION OF
6 MULTIPLEXER AND
DEMULTIPLEXER
DESIGN AND IMPLEMENTATION OF
7
3 BIT SYNCHRONOUS UP/DOWN
COUNTER
DESIGN AND IMPLEMENTATION OF
8 SHIFT REGISTER

9 SIMULATOR BASED STUDY OF

COMPUTER ARCHITECTURE
EX. NO: 1 a
DATE:
STUDY OF LOGIC GATES

AIM: -

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED: -

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8 Bread Board 1

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one
or more input and only one output.
OR, AND and NOT are basic gates. NAND and NOR are known as universal gates. Basic gates
form these gates.
AND GATE

The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is low.
OR GATE

The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE

The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.
X- OR GATE

The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.
NAND GATE

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.

PROCEDURE
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
 NOT GATE :
SYMBOL: PIN DIAGRAM:

X-OR GATE :
SYMBOL : PIN DIAGRAM :
2- INPUT NAND GATE

SYMBOL PIN DIAGRAM

3- INPUT NAND GATE

NOR GATE

RESULT:

Thus the logic gates were studied and their truth tables have been verified.
EX NO:1(b)

DATE:

VERIFICATION OF BOOLEAN THEOREMS

USING DIGITAL LOGIC GATES
AIM:
To verify the Boolean Theorems using logic gates.
APPARATUS REQUIRED:

SL. NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
As per
5. CONNECTING WIRES - required

THEORY:

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law
The binary operator OR, AND is said to be
associative if, 1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law
The binary operator OR, AND is said to be
distributive if, 1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

1. A = A

6. Idempotent Law
1. A+A = A
2. A.A = A
7. Complementary Law
 1. A+A' = 1
2. A.A' = 0
8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B

Demorgan’s Theorem
a) Proof of equation (1):
Construct the two circuits corresponding to the functions A’. B’and (A+B)’ respectively. Show that for all
 combinations of A and B, the two circuits give identical results. Connect these circuits and verify their
operations.

b) Proof of equation (2).

Construct two circuits corresponding to the functions A’+B’and (A.B)’ A.B, respectively. Show that, for
all combinations of A and B, the two circuits give identical results. Connect these circuits and verify
their operations.
 We will also use the following set of postulates:
P1: Boolean algebra is closed under the AND, OR, and NOT operations.
P2: The identity element with respect to • is one and + is zero. There is no
identity element with respect to logical NOT.
P3: The • and + operators are commutative.
P4: • and + are distributive with respect to one another. That is,
A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B) • (A + C).
P5: For every value A there exists a value A’ such that A•A’ = 0 and A+A’ = 1.
This value is the logical complement (or NOT) of A.
P6: • and + are both associative. That is, (A•B)•C = A•(B•C) and (A+B)+C = A+(B+C).
You can prove all other theorems in boolean algebra using these postulates.

PROCEDURE:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

RESULT:
Thus the above stated Boolean laws are verified.
 EX NO:2

DATE:

DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS

USING GATES FOR ARBITRARY FUNCTIONS
AIM:
To simplify the given expression and to realize it using Basic gates and Universal gates

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY
1. NAND GATE IC 7400 2
2. AND GATE IC 7408 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. NOR GATE IC 7402 2
5. BREADBOARD - 1

THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctivenormal form
(sum of min-terms) or conjunctive normal form (product of maxterms).
A Boolean function can be represented by a Karnaugh map in which each cell corresponds to a
minterm. The cells are arranged in such a way that any two immediately adjacent cells correspond to
two minterms of distance 1. There is more than one way to construct a map with this property.
 Realization using NOR gates

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT: -

Thus the combinational circuits were designed and implemented and also any
Boolean function using basic gates and universal gates were verified.
EX NO:3(a)

DATE:

DESIGN OF ADDER AND SUBTRACTOR USING LOGIC GATES

AIM:
To design and construct half adder, full adder, half substractor and full substractor circuits and
verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. BREADBOARD - 1

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’
and other from the carry ‘ C’ into the higher adder position. Above circuit is called as a carry signal
from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In
full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate
HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input
and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR
Gate, borrow output can be implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full
subtractor .The first half subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half subtractor and the second term
is the inverted difference output of first X-OR.

PROCEDURE:

(iv) Connections are given as per circuit diagram.

(v) Logical inputs are given as per circuit diagram.

(vi) Observe the output and verify the truth table.

LOGIC DIAGRAM

HALF ADDER

TRUTH TABLE

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM K-Map for CARRY

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

FULL ADDER
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC
LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B
LOGIC DIAGRAM:
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

RESULT: -

Thus the half adder, full adder, half subtractor and full subtractor circuits were designed
and their truth tables verified.
EX NO:3b

DATE:

DESIGN OF 4-BIT ADDER AND SUBTRACTOR USING IC 7483

AIM:
To design and implement the 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full adder
connected to the input carry of next full adder in chain. The augends bits of ‘A’ and the addend bits of
‘B’ are designated by subscript numbers from right to left, with subscript 0 denoting the least
significant bits. The carries are connected in chain through the full adder. The input carry to the adder is
C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data
input ‘B’ and the corresponding input of full adder. The input carry C 0 must be equal to 1 when
performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When
M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than
19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and
should appear in the form listed in the columns.
 ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,
together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
PROCEDURE:

(i) Logical inputs were given as per truth table

(ii) Observe the logical output and verify with the truth tables.
(iii) Connections were given as per circuit diagram.
LOGIC DIAGRAM:

4- BIT BINARY ADDER

LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR
PIN DIAGRAM FOR IC 7483:
LOGIC DIAGRAM:
4- BIT BINARY ADDER/SUBTRACTOR
 TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

RESULT: -

Thus the 4 bit adder and subtractor circuits were designed and their logic was verified.
EX. NO:4
DATE:
DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

AIM:

To design and implement 4-bit

(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1

2. AND GATE IC 7408 1

3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

5. IC TRAINER KIT - 1

6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes
the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits to
represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code.
 The input variable are designated as B3, B2, B1, B0 and the output variables are designated as
C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions are
obtained from K-Map for each output variable.
BINARY TO EXCESS-3 CODE CONVERTOR:

A code converter is a circuit that makes the two systems compatible even though each uses a
different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit
combination of elements as specified by code and the output lines generate the corresponding bit
combination of code. Each one of the four maps represents one of the four outputs of the circuit as a
function of the four input variables.
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.
LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

K-Map for G3:

G3 = B3
K-Map for G2:

K-Map for G1:

K-Map for G0:

TRUTH TABLE:

Binary input Gray code output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0:

TRUTH TABLE:

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0
 0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:

K-Map for E0:

TRUTH TABLE:

BCD input Excess – 3 output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x
LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1
K-Map for B:

K-Map for C:
K-Map for D:

TRUTH TABLE:

Excess – 3 Input BCD Output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

RESULT: -

Thus the code converter circuits were designed and their logic verified.
EX. NO:5a
DATE:
DESIGN AND IMPLEMENTATION OF BCD ADDER

AIM:
To design and implement 4-bit BCD adder using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 2
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - As required

THEORY:
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than
19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and
should appear in the form listed in the columns.

ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,
together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
PROCEDURE:

(i) Logical inputs were given as per truth table

(ii) Observe the logical output and verify with the truth tables.
(iii) Connections were given as per circuit diagram.
LOGIC DIAGRAM:
BCD ADDER

K MAP

Y = S4 (S3 + S2)
TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

RESULT: -
Thus the 4 bit BCD adder was designed and their logic was verified
EX. NO:5 b

DATE:

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:
To design and implement encoder and decoder using logic gates, study of IC 7445 and IC
74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2 n
input lines and n output lines. In encoder the output lines generates the binary code corresponding to
the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output
that generate the corresponding binary code. In encoder it is assumed that only one input has a value of
one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs are
zero the outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into
coded output where input and output codes are different. The input code generally has fewer bits than
the output code. Each input code word produces a different output code word i.e there is one to one
mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2 n possible outputs. 2n output values are from 0 through out
2n – 1.
 PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table

PIN DIAGRAM FOR IC 7445:

BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:
TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1
LOGIC DIAGRAM FOR DECODER:
TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

RESULT: -

Thus the encoder/decoder circuits were designed and their logic was verified
EX NO: 6

DATE:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates and study of IC
74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2 n input line and n selection lines whose bit
combination determine which input is selected.
The function of Demultiplexer is in contrast to multiplexer function. It takes information from
one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also
known as a data distributor. Decoder can also be used as Demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select
lines enable only one gate at a time and the data on the data input line will pass through the selected
gate to the associated data output line.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

PIN DIAGRAM FOR IC 74150:
CIRCUIT DIAGRAM FOR 4X1 MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

D0 = X S1’ S0’

D1 = X S1’ S0

D2 = X S1 S0’

D3 = X S1 S0
LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74154:

RESULT: -

Thus the Multiplexer/Demultiplexer circuits were designed and their logic was verified.
EX NO:7

DATE:

DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design and implement the 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter is
also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low
counter follows reverse sequence.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table

STATE DIAGRAM:

CHARACTERISTICS TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
TRUTH TABLE:

Input Present State Next State A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X

0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 1

0 0 1 0 0 0 1 0 X X 1 1 X

0 0 0 1 0 0 0 0 X 0 X X 1

1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1
K MAP

K MAP
LOGIC DIAGRAM:

RESULT: -

Thus the 3 bit synchronous up/down counter circuits were designed and their logic was
verified.
EX. NO:8

DATE:

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:

To design and implement

(i) Serial in serial out

(ii) Serial in parallel out
(iii) Paral lel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is known as shift
register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one
flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes
the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop.
The output of a given flip flop is connected to the input of next flip flop of the register. Each clock
pulse shifts the content of register one bit position to right.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

PIN DIAGRAM:
LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE (SERIAL IN PARALLEL OUT):

OUTPUT

CLK DATA QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 0

4 1 1 0 0 1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT

TRUTH TABLE (PARALLEL IN SERIAL OUT):

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1
 LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:
DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 0 1 0 1 0 1 0 1

3 0 0 0 1 0 0 0 1

4 1 1 1 1 1 1 1 1

5 0 0 0 0 0 0 0 0

RESULT: -

Thus the shift register circuits were designed and their logic was verified
EX. NO:9

DATE:

SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE

AIM:
To study the importance of simulation tools in learning computer architecture

THEORY:
Computer architecture is one of the important subjects offered at universities across the world.
Teaching in traditional way can be insufficient if the teaching focus is solely on the textbook
materials. One of the most critical aspects on teaching this discipline is how to support the theoretical
concepts of the subjects with appropriate practical experience, usually organized as laboratory
experiments. But practically, students are unable to understand the subject. For this reason, many
educators have begun using different computer architecture simulators based on hardware and
software to solve this problem [5]. There are mainly about three simulators: Logisim, CEDAR and
CPU Sim.
Logisim
Logisim is a simple software which can be used for implementing circuits with basic gates. Users of
this simulator can draw the circuits using the tool box available. The circuit automatically propagates
circuit values through the circuit by selecting the suitable tool and the user can toggle the input
conditions to learn how the circuit behaves in other situations. Students themselves were able to
understand how to connect basic gates to make simple as well as complex circuits with the help of
Logisim.
CEDAR

CEDAR is a powerful simulator in which the students can implement a complete computer and will be able to
understand the internal details of a computer more clearly. Using CEDAR Simulator students can 1) build the
entire computer hardware using fundamental logic gates; 2) write an assembler to translate the test program into
machine level program ; 3) load the program into the memory of the computer; and 4) run the test program on
these hardware. After the implementation students can see how a computer executes a program and what are the
signals generated during each clock pulse.

CPU Sim
CPU Sim is an interactive simulation tool in which the user can specify the details of the CPU to be simulated,
such as register set, memory, set of microinstructions, set of machine instructions and set of assembly language
instructions. Users of the tool can write their own machine or assembly language program and run on the CPU
they have created. It simulates the computer architecture at register transfer level so that the students will get a
better understanding about the system. User of the simulator has to specify the hardware units and the
microinstructions for the CPU and then create the set of machine instructions. Corresponding to each machine
instruction a sequence of microinstructions is to be formed.

RESULT:
Thus the importance of simulation tools in learning computer architecture is studied.