Bidirectional 12kV To 1.2kV DC-DC Converter For Renewable Energy Applications
Bidirectional 12kV To 1.2kV DC-DC Converter For Renewable Energy Applications
Bidirectional 12kV To 1.2kV DC-DC Converter For Renewable Energy Applications
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vC,S (t)
SLV,1 SLV,2 Lst,D SHV,1 SHV,2 SLV,1 SLV,2 Lst,S SHV,1 SHV,2
12000 V
12000 V
1200 V
1200 V
iL,D (t) iL,S (t) Cst,S
vLV (t) vHV (t) vLV (t) vHV (t)
CLV CHV CLV CHV
1:nD 1:nS
SLV,3 SLV,4 SHV,3 SHV,4 SLV,3 SLV,4 SHV,3 SHV,4
a) b)
Current (kA), Voltage (kV)
3
Turn-off Turn-off iL,S
2 LV side iL,D v,LV
v,LV LV side
vHV
1 vHV vC,S
Turn-off
0 HV side
Turn-off
-1 HV side
-2 I II III
I II III
-3
0 10 Ts D2,D Ts D1,D 30 40 50 0 10 Ts D2,S Ts D1,S 30 40 50
c) Time (µs) d) Time (µs)
Figure 6: HV side Zero Current Switching bidirectional topologies and modulations: a) Dual Active Bridge; b) Series Resonant
Converter; c) DAB triangular modulation with nD =13 and Lst,D =2 µH at 1 MW transferred power.; d) SRC constant frequency
modulation with nD =13, Lst,D =5.85 µH, Cst,D =12 µF at 1 MW transferred power.
In order to achieve HV-ZCS, the constraint iL,D (0)=0 must be • Over-resonant frequency: In this operating mode, the current
fulfilled, which gives a relation between D1,D and D2,D described iL,S (t) has always a phase difference with respect to the driv-
by (4). The duty cycle D1,D must be adjusted to transfer the ing voltage. This implies that, when the power is transferred
required power, thus for a power PD , the required D1,D is given from the HV to the LV side, the HV side switches will turn-
by (5). off the transformer current and thus HV-ZCS would not be
VHV · D1,D achievable.
D2,D = (4) • Under-resonant frequency: In this operating mode, only buck
nD · VLV
operation is achievable by reducing the switching frequency
nD Ts (VLV · nD − VHV )Lst,D nD VLV PD starting from resonant frequency. This means that the voltage
D1,D = (5)
Ts (VLV · nD − VHV )VHV ranges can not be covered once a turns ratio nS is selected.
In this modulation scheme, the turns ratio must be different to Constant frequency operation of the SRC converter was treated in
the input output voltage ratio VHV /VLV , otherwise no power is [18] for several state trajectories. Of special interest is the trajectory
transferred. Additionally, to achieve HV-ZCS, the turns ratio must that enables a HV-ZCS behavior, which is presented in Fig.6-d) and
be higher than the input output voltage ratio VHV /VLV . Therefore described by the following piecewise intervals:
the limitation on the turns ratio is given by:
• Interval I: The HV and the LV side bridges apply full positive
VHV voltage to the HV and LV windings of the transformer. The
(6)
nD > difference VLV −VHV /nS is applied to the resonant tank. The
VLV
current iL,S (t) through the transformer rises with a sinusoidal
The series inductance Lst,D is designed to have a certain safety
waveform and consequently the resonant capacitor voltage
margin time tSM,D in worst case between the turn-off of the HV
vC,S (t) varies sinusoidally (cf. I Fig.6-d)). The length of this
switch and the start of the next switching cycle. This in turn gives
interval is given by the duty cycle D2,S .
a relation between the turns ratio nD and the series inductance
• Interval II: The LV side bridge switches the voltage vLV (t) to
Lst,D .
With this description, the turns ratio nD and the safety margin zero, whereas turn-off losses are generated the LV side. The
tSM,D are left as design parameters. The turned-off currents, RMS voltage applied to the tank is now −VLV /nS and therefore
and average currents in the switches are calculated for a given the current decreases. As soon as current iL,S (t) reaches zero,
transferred power PD . Thereafter, an optimized design can be
reached by following the optimization process shown in Fig. 7.
DAB: PD
B. Series Resonant Converter with Constant Frequency Modulation Specifications: VHV ; VLV ; fs
SRC: PS
The SRC converter depicted in Fig.6-b), represents an attractive
DAB: nD ; tSM,D
alternative for the HV-ZCS current modulation, which led to Setup free parameters:
SRC: nS ; tSM,S ; fo
several high power DC-DC converter research efforts [14–16]. This
Parameter variation
converter consists of two full bridges interfaced by a transformer DAB: D1,D ; D2,D
Calculate operating point: i ; ioff...
with a series resonant tank composed of an inductor Lst,S and SRC: D1,S ; D2.S rms
a capacitor Cst,S . Piecewise sinusoidal current waveforms are
LV side losses Transformer losses HV side losses
obtained through the transformer with this resonant tank.
Cond. Sw. Core Copper Cond. Sw.
As has been reported in [17], the power transfer of this converter
can be controlled by adjusting the switching frequency with a 50 %
duty cycle in both fullbridges. However, given the desired HV-ZCS Efficiency optimization
behavior and the operating ranges of the system, this operating
mode is not suitable for the following reasons: Figure 7: Flow-chart of converter’s optimization process.
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TABLE II: Design parameters for the DAB and the SRC
the HV side bridge switches and applies zero voltage to the topologies.
HV side of the transformer. As the switched current at this
point is zero, the turn-off loses are negligible. The length of Parameter DAB SRC
this interval is given by the duty cycle D1,S . Turns ratio nD =13 nS =13
• Interval III: If capacitor voltage vC,S (t) is lower than the Safe M. time tSM,D =2.5 µs tSM,S =2.5 µs
low side voltage VLV and the reflected high side voltage Series inductance Lst,D =2 µH Lst,S =5.85 µH
VHV /n, then the corresponding diodes are in blocking state Series capacitor - Cst,S =12 µF
and therefore the current through the transformer stays at Resonant frequency - f0 =19 kHz
zero until the next half switching period begins. The resonant
frequency f0 is must be adjusted to enable recombination 1
or swap-out of all carriers in the HV IGBT before the next Semisouth SJEP120R063 SiC JFET
Efficiency (%)
99 Infineon IPW60R045CP MOSFET
switching cycle begins. This safety margin time is named
tSM,S . 98
Considering the time intervals in Fig.6-d), the current iL,S (t) and 97 Infineon IGW75N60T IGBT
the voltage vC,S (t) are described by the following set of equations 96
[18] for the first half switching period:
95
(VC0,S − vE,S (t)) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
iL,S (t) = − sin(ω0 t) + IL0,S · cos(ω0 t) (7) Power (MW)
Z0
vC,S (t) = (VC0,S − vE,S (t)) · cos(ω0 t) (8) Figure 9: Calculated efficiencies for DAB with triangular
+ IL0,S Z0 · sin(ω0 t) + vE,S (t) (9) modulation using different LV-side switch technologies.
1
ω0 = = 2πf0 (10) RMS and average currents in the switches are calculated for a
Lst,S Cst,S
given transferred power PS . Thereafter, an optimized design can
Lst,S be reached by following the optimization process shown in Fig. 7.
Z0 = (11)
Cst,S
C. Efficiency comparison for different LV side switches
VLV − VHV /n : 0 < t ≤ D2,S Ts
vE,S (t) = −VHV /nS : D2,S Ts < t ≤ D1,S Ts (12) With the aforementioned modulation schemes, the desired HV-
0 : D1,S Ts < t ≤ Ts /2 ZCS is achieved, where all the switching processes are performed
by the LV side switches. In this voltage range, mature technologies
The initial conditions VC0,S and IL0,S are calculated in each with high switching performances can be found. In this section, the
switching interval in order to have a continuous voltage/current efficiencies of both studied topologies considering the following
waveforms, whereas the initial conditions iL,S (0) and vC,S (0) at switch technologies are investigated:
interval I are calculated to meet with (13) and (14) respectively.
• 600 V IGBT: Infineon IGW75N60T
iL,S (0) = −iL,S (Ts /2) (13) • 600 V MOSFET: Infineon CoolMOS IPW60R045CP
• 1200 V SiC JFET: Semisouth SJEP120R063
vC,S (0) = −vC (Ts /2) (14)
These devices are single switches which require to be paralleled
The aim is to achieve HV-ZCS, which is equivalent to forcing
in order to reach the current driving capability. A total of 60
iL,S (0)=0 and solving for D2,S , thus finding the relation between
switches are paralleled to build one of the power switching device,
D1,S and D2,S given by (15). The duty-cycle D1,S is then adjusted
which will be then fitted into one power module. In the case of
to transfer a power PS through the converter as described by (19).
IGBTs and MOSFETS, the blocking capability is reached through
D2,S = a series connection of 3 groups of paralleled devices, whereas in
case of the SiC JFETs, only 2 series connected groups of devices
F1 nS vC,S (0)
− tan−1 are required. For the HV side, each of the switches is built using
F2 (nS VLV − nS vC,S (0) − nS VHV ) − nS VLV 4 series connected Press-Pack IGBTs.
nS VLV + VHV fs The safe blocking voltage distribution in the series connected
− (15)
F2 (nS VLV − nS vC,S (0) − nS VHV ) − nS VLV ω0 devices in both LV and HV sides can be achieved by addition of
F1 = sin(ω0 D1,S Ts ) (16) passive components or by using a multilevel (ML) construction
[19–21]. When considering a Neutral Point Clamped (NPC) ML
F2 = cos(ω0 D1,S Ts ) (17)
converter in two level operation, no additional losses are generated
VLV (F2 VLV nS − F2 VHV − VLV nS ) in the clamping diodes [22] and therefore the losses calculations can
vC,S (0) = (18)
2VHV + F2 VLV nS − VLV nS be performed considering an ideal series connection of switches.
D1,S = Two level operation is considered at full transferred power whereas
4fs (VLV2
VHV − VLV VHV 2
) at partial load, the staircase-type voltage of the ML topology could
cos−1 be used to increase the soft-switching range. This last case is not
VLV (4fs VHV nS VLV − 4VHV fs + PS Z0 ω0 n2S )
2
treated in this paper.
PS · Z0 ω0 (n2S VLV − 2nS VHV ) fs The losses in the LV side switches are calculated using datasheet
+ 2
(19)
VLV (4fs VHV nS VLV − 4VHV fs + PS Z0 ω0 n2S ) ω0 information whereas for the HV side switches the measured output
The same constraint as with the DAB stands for the turns ratio characteristic is used. The transformer losses are included in the
nS , (cf. (6)). The resonant frequency f0 is chosen to have a defined efficiency calculations considering the matrix transformer construc-
tSM,S in worst-case operation. This frequency is usually in the tion presented in Section IV, which represents a worst case in terms
range f0 =0.8..0.9fs [13]. The series capacitor Cst,S should be of losses. In the case of the SRC converter, the losses in the series
large enough to avoid conduction of the diodes during interval III. capacitor are included in the transformer losses.
With (7)-(18) the operation of the converter is described, leaving The parameters used to perform the efficiency comparison be-
nS , tSM,S and Cst,S as design parameters. The turned-off currents, tween both converters are shown in Table II.
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Losses (kW)
Switching
7.5 Switching
Switching
5
Copper
Switching Copper Copper
Cond. Cond.
2.5 Cond. Cond.
Cond.
Cond. Core Core Core
0
a) LV side Trafo. HV side b) LV side Trafo. HV side c) LV side Trafo. HV side
Figure 8: Loss distribution at power P = 1 MW for the SiC JFET LV switch solution and the matrix transformer design: a) DAB with
trapezoidal modulation; b) DAB with triangular modulation; c) SRC with constant frequency.
1 Litz wire
HVwinding 100kV dry-type
Efficiency (%)
99
potted isolation
98 U-Cores
97
Semisouth SJEP120R063 SiC JFET
96 Infineon IPW60R045CP MOSFET
Infineon IGW75N60T IGBT
95
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Power (MW)
Figure 10: Calculated efficiencies for SRC with constant
frequency modulation using different LV-side switch technologies.
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100kV Isolated
HV Cable 100kV isolated
HV Cable
Chambered
construction l
for heat extraction 120mm Fan 6 LV copper
120mm Fan foil winding
Figure 12: Shell-type transformer. Size: Figure 13: Matrix transformer. Size: Outer Diam.= 396 mm,
358 mmx324 mmx163 mm. Core losses: 1.83 kW, Copper losses Height=120 mm. Core losses: 2.23 kW, Copper losses 2.28 kW.
1.93 kW.
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