Tca 9545 A
Tca 9545 A
TCA9545A
SCPS204D – JANUARY 2014 – REVISED NOVEMBER 2019
TCA9545A Low Voltage 4-channel I2C and SMbus Switch With Interrupt Logic and Reset
Functions
1 Features 2 Applications
•
1 1-of-4 Bidirectional translating switches • Servers
• I2C bus and SMBus compatible • Routers (telecom switching equipment)
• Four active-low interrupt inputs • Factory automation
• Active-low interrupt output • Products with I2C slave address conflicts (e.g.
• Active-low reset input multiple, identical temp sensors)
• Two address terminals, allowing up to four
devices on the I2C bus 3 Description
The TCA9545A is a quad bidirectional translating
• Channel selection via I2C bus, in any combination
switch controlled via the I2C bus. The SCL/SDA
• Power-up with all switch channels deselected upstream pair fans out to four downstream pairs, or
• Low RON switches channels. Any individual SCn/SDn channel or
• Allows voltage-level translation between 1.8-V, combination of channels can be selected, determined
by the contents of the programmable control register.
2.5-V, 3.3-V, and 5-V buses
Four interrupt inputs (INT3–INT0), one for each of the
• No glitch on power-up downstream pairs, are provided. One interrupt (INT)
• Supports hot insertion output acts as an AND of the four interrupt inputs.
• Low standby current An active-low reset (RESET) input allows the
• Operating power-supply voltage range of TCA9545A to recover from a situation in which one of
1.65 V to 5.5 V the downstream I2C buses is stuck in a low state.
Pulling RESET low resets the I2C state machine and
• 5.5 V Tolerant inputs
causes all the channels to be deselected, as does the
• 0 to 400-kHz Clock frequency internal power-on reset function.
• Latch-Up performance exceeds 100 mA per JESD
The pass gates of the switches are constructed such
78 that the VCC terminal can be used to limit the
• ESD Protection exceeds JESD 22 maximum high voltage, which will be passed by the
– 4000-V Human-body model (A114-A) TCA9545A. This allows the use of different bus
voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V
– 1500-V Charged-device model (C101)
parts can communicate with 5-V parts, without any
additional protection. External pull-up resistors pull
the bus up to the desired voltage level for each
channel. All I/O terminals are 5.5 V tolerant.
Device Information
ORDER NUMBER PACKAGE BODY SIZE
TCA9545APWR TSSOP (20) 6,5mm x 4,4mm
Channel 0
VCC SD0
SDA SC0 Slaves A0, A1...AN
I2C or SMBus SCL INT0
INT
Master Channel 1
SD1
(e.g. µProcessor) RESET SC1 Slaves B0, B1...BN
INT1
TCA9545A
Channel 2
SD2
SC2 Slaves C0, C1...CN
INT2
A0
A1 Channel 3
GND SD3
SC3 Slaves D0, D1...DN
INT3
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9545A
SCPS204D – JANUARY 2014 – REVISED NOVEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 12
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 12
3 Description ............................................................. 1 8.5 Programming........................................................... 12
8.6 Control Register ...................................................... 15
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation ........................ 17
9.1 Application Information............................................ 17
6 Specifications......................................................... 4
9.2 Typical Application .................................................. 17
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4 10 Power Supply Recommendations ..................... 20
10.1 Power-On Reset Requirements ........................... 20
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information .................................................. 4 11 Layout................................................................... 22
6.5 Electrical Characteristics........................................... 5 11.1 Layout Guidelines ................................................. 22
6.6 I2C Interface Timing Requirements........................... 6 11.2 Layout Example .................................................... 22
6.7 Switching Characteristics .......................................... 7 12 Device and Documentation Support ................. 23
6.8 Interrupt and Reset Timing Requirements ................ 7 12.1 Receiving Notification of Documentation Updates 23
6.9 Typical Characteristics .............................................. 8 12.2 Support Resources ............................................... 23
7 Parameter Measurement Information .................. 9 12.3 Trademarks ........................................................... 23
12.4 Electrostatic Discharge Caution ............................ 23
8 Detailed Description ............................................ 11
12.5 Glossary ................................................................ 23
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11 13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision C (July 2019) to Revision D Page
PW package
20-Pin TSSOP
Top View
A0 1 20 VCC
A1 2 19 SDA
RE SET 3 18 SCL
INT0 4 17 INT
SD0 5 16 SC3
SC0 6 15 SD3
INT1 7 14 INT3
SD1 8 13 SC2
SC1 9 12 SD2
GND 10 11 INT2
No t to scale
Pin Functions
PIN
DESCRIPTION
NO. NAME
1 A0 Address input 0. Connect directly to VCC or ground.
2 A1 Address input 1. Connect directly to VCC or ground.
Active-low reset input. Connect to VCC or VDPUM (1) through a pull-up resistor if not
3 RESET
used.
4 INT0 Active-low interrupt input 0. Connect to VDPU0 (1) through a pull-up resistor.
(1)
5 SD0 Serial data 0. Connect to VDPU0 through a pul-up resistor.
6 SC0 Serial clock 0. Connect to VDPU0 (1)
through a pull-up resistor.
7 INT1 Active-low interrupt input 1. Connect to VDPU1 (1) through a pull-up resistor.
8 SD1 Serial data 1. Connect to VDPU1 (1) through a pull-up resistor.
9 SC1 Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor.
10 GND Ground
11 INT2 Active-low interrupt input 2. Connect to VDPU2 (1) through a pull-up resistor.
12 SD2 Serial data 2. Connect to VDPU2 (1) through a pull-up resistor.
13 SC2 Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor.
14 INT3 Active-low interrupt input 3. Connect to VDPU3 (1) through a pull-up resistor.
15 SD3 Serial data 3. Connect to VDPU3 (1) through a pull-up resistor.
16 SC3 Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor.
17 INT Active-low interrupt output. Connect to VDPUM (1) through a pull-up resistor.
18 SCL Serial clock line. Connect to VDPUM (1) through a pull-up resistor.
19 SDA Serial data line. Connect to VDPUM (1) through a pull-up resistor.
20 VCC Supply power
(1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C master reference voltage and VDPU0–VDPU3
are the slave channel reference voltages.
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
VI Input voltage range –0.5 7 V
II Input current ±20 mA
IO Output current ±25 mA
Continuous current through VCC ±100 mA
Continuous current through GND ±100 mA
Ptot Total power dissipation 400 mW
TA Operating free-air temperature range –40 85 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into
the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process. Terminals listed as 250 V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Terminals listed as 250 V may actually have higher performance.
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) All typical values are at nominal supply voltage (VCC = 1.8 V, 2.5 V, 3.3 V, or 5 V), TA = 25°C.
(2) RESET = VCC (held high) when all other input voltages, VI = GND
(3) The power-on reset circuit resets the I2C bus logic with VCC < VPORF.
Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TCA9545A
TCA9545A
SCPS204D – JANUARY 2014 – REVISED NOVEMBER 2019 www.ti.com
(4)
SCL, SDA VI = VCC or 15 19
Cio(OFF) Switch OFF 1.65 V to 5.5 V pF
SC3–SC0, SD3–SD0 GND (2) 6 8
4.5 V to 5.5 V 4 10 16
VO = 0.4 V IO = 15 mA
3 V to 3.6 V 5 13 20
RON Switch on-state resistance Ω
2.3 V to 2.7 V 7 16 45
VO = 0.4 V IO = 10 mA
1.65 V to 1.95 V 10 25 70
(4) Cio(ON) depends on the device capacitance and load that is downstream from the device.
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)
(1)
RON = 20 Ω, CL = 15 pF 0.3
tpd Propagation delay time SDA or SCL SDn or SCn ns
RON = 20 Ω, CL = 50 pF 1
tiv Interrupt valid time (2) INTn INT 4 μs
(2)
tir Interrupt reset delay time INTn INT 2 μs
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 7)
(1) trst is the propagation delay measured from the time the RESET terminal is first asserted low to the time the SDA terminal is asserted
high, signaling a stop condition. It must be a minimum of tWL.
800 1.8
VCC = 5.5V
700 VCC = 3.3V 1.6
VCC = 1.65V
500 1.2
VOL (mV)
400 1
300 0.8
200 0.6
25ºC (Room Temperature)
100 0.4 85ºC
-40ºC
0 0.2
0 2 4 6 8 10 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5
IOL (mA) D003
VCC (V) D004
Figure 1. SDA Output Low Voltage (VOL) vs Load Current Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
(IOL) at Three VCC Levels Three Temperature Points
6 30
25ºC (Room Temperature)
5.8 85ºC
-40º 25
5.6
5.4
20
CIO(OFF) (pF)
RON (Ohm)
5.2
5 15
4.8
10
4.6
4.4 25ºC (Room Temperature)
5
4.2 85ºC
-40ºC
4 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V) D006
VCC (V) D001
Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs. Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at
Supply Voltage (VCC) at Three Temperature Points Three Temperatures
RL = 1 kΩ
SDn, SCn
DUT
CL = 50 pF
(See Note A)
BYTE DESCRIPTION
1 I2C address + R/W
tscl tsch
0.7 × VCC
SCL
0.3 × VCC
tvd(ACK)
ticr tsts
or tvdL
tbuf ticf
tsp tvdH
0.7 × VCC
SDA
0.3 × VCC
ticf ticr tsdh tsps
tsth tsds Repeat
Start Stop
Start or Repeat
Condition Condition
Start Condition
VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf = 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
SDA
30%
trst
RESET 50%
tREC
tWL
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(See Note A)
INTn
INTn
0.5 × VCC (input) 0.5 × VCC
(input)
tir
tiv
INT INT
0.5 × VCC 0.5 × VCC
(output) (output)
8 Detailed Description
8.1 Overview
The TCA9545A is a 4-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to
four channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well
as any combination of the four channels. The TCA9545A also supports interrupt signals in order for the master to
detect an interrupt on the INT output terminal that can result from any of the slave devices connected to the
INT3-INT0 input terminals.
The device offers an active-low RESET input which resets the state machine and allows the TCA9545A to
recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can
also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function
and a POR will cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 terminals), a single 8-bit control register is written to or read from to determine the
selected channels and state of the interrupts.
The TCA9545A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
TCA9545A
6
SC0
9
SC1
13
SC2
16
SC3
SD0 5
SD1 8
SD2 12
SD3 15
20
VCC
3 Power-on Reset
RESET
SCL 18 1
A0
Input Filter I2C Bus Control
19 2
SDA A1
4
INT0
INT1 7 Output 17
Interrupt Logic INT
INT2 11 Filter
INT3 14
8.5 Programming
8.5.1 I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 8).
SDA
SCL
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 9).
Programming (continued)
SDA
SCL S P
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master, and the devices that are controlled by the master are the slaves (see
Figure 10).
SDA
SCL
Slave
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 11). Setup and hold times must be taken
into account.
Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master 1 2 8 9
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the TCA9545A control register using the write mode shown in Figure 12.
Slave Address Control Register
SDA S 1 1 1 0 0 A1 A0 0 A X X X X B3 B2 B1 B0 A P
Start Condition R/W ACK From Slave ACK From Slave Stop Condition
Data is read from the TCA9545A control register using the read mode shown in Figure 13.
Slave Address Control Register
Start Condition R/W ACK From Slave NACK From Master Stop Condition
1 1 1 0 0 A1 A0 R/W
Fixed Hardware
Selectable
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
7 6 5 4 3 2 1 0
Channel 0
Channel 1
Channel 2
Channel 3
INT0
INT1
INT2
INT3
(1) Several channels can be enabled at the same time. For example, B3 = 0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are
disabled, and channels 1 are 2 and enabled. Care should be taken not to exceed the maximum bus capacity.
(1) Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt
on channels 0 and 3, and there is interrupt on channels 1 and 2.
SD1 8
9 Channel 1
SC1
7
INT1
VDPU2 = 1.65 V to 5.5 V
TCA9545A
12
SD2
13 Channel 2
SC2
11
INT2
VDPU3 = 1.65 V to 5.5 V
2 A1
1 15
A0 SD3
10 16 Channel 3
GND SC3
14
INT3
5 25
25ºC (Room Temperature) Standard-mode
85ºC Fast-mode
4 -40ºC 20
Rp(max) (kOhm)
3 15
Vpass (V)
2 10
1 5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 50 100 150 200 250 300 350 400 450
VCC (V) D007
Cb (pF) D008
Space Space Standard-mode Fast-mode
spacespace spacespace (fSCL= 100 kHz, tr = 1 µs) (fSCL= 400 kHz, tr= 300 ns)
Figure 17. Pass-Gate Voltage (Vpass) vs Supply Voltage Figure 18. Maximum Pull-Up resistance (Rp(max)) vs Bus
(VCC) at Three Temperature Points Capacitance (Cb)
1.8
1.6
1.4
1.2
Rp(min) (kOhm)
0.8
0.6
0.4
Figure 19. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX)
Ramp-Down Ramp-Up
VCC_TRR
Time
Time to Re-Ramp
VCC_FT VCC_RT
Figure 20. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 3 specifies the performance of the power-on reset feature for TCA9545A for both types of power-on reset.
(1) All supply sequencing and ramp rate values are measured at TA = 25°C
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 21 and Table 3 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 22 and Table 3 provide more details on this specification.
VCC
VPORR
VPORF
Time
POR
Time
11 Layout
By-pass/De-coupling
capacitors VDPUM
GND VCC
VDPU0
To Slave Channel 0
A0 VCC
VDPU3
A1 SDA
RESET SCL
To Slave Channel 3
TCA9545A
INT0 INT
SD0 SC3
SC0 SD3
INT1 INT3
SD1 SC2
To Slave Channel 1
SC1 SD2
GND
VDPU1
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TCA9545APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PW545A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
6.6 5.85
6.4
NOTE 3
10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE 0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
18X (0.65)
10 11
(5.8)
4220206/A 02/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
18X (0.65)
10 11
(5.8)
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPORTANT NOTICE AND DISCLAIMER
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