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STI - FSM - Solutions

Setup time is the minimum time the data signal must be stable before the clock edge so that it can be reliably sampled by the clock. Hold time is the minimum time the data signal must be stable after the clock edge so that it can be reliably sampled. In the circuit, there is no hold time violation as the data path delay is less than the clock path delay, giving a positive hold slack. However, there is a setup time violation as the clock path delay is less than the data path delay, giving a negative setup slack. The maximum operating frequency is 45.5MHz.

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66 views6 pages

STI - FSM - Solutions

Setup time is the minimum time the data signal must be stable before the clock edge so that it can be reliably sampled by the clock. Hold time is the minimum time the data signal must be stable after the clock edge so that it can be reliably sampled. In the circuit, there is no hold time violation as the data path delay is less than the clock path delay, giving a positive hold slack. However, there is a setup time violation as the clock path delay is less than the data path delay, giving a negative setup slack. The maximum operating frequency is 45.5MHz.

Uploaded by

Aishwarya Gajendrula
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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A1: Define Setup and Hold time?

[2]
Setup Time:

 Setup time is the minimum amount of time the data signal should be held steady before
the clock event so that the data are reliably sampled by the clock. This applies to
synchronous circuits such as the flip-flop.
 Or In short I can say that the amount of time the Synchronous input (D) must be stable
before the active edge of the Clock.
 The Time when input data is available and stable before the clock pulse is applied is
called Setup time.

Hold time:

 Hold time is the minimum amount of time the data signal should be held steady after
the clock event so that the data are reliably sampled. This applies to synchronous
circuits such as the flip-flop.
 Or in short I can say that the amount of time the synchronous input (D) must be stable
after the active edge of clock.
 The Time after clock pulse where data input is held stable is called hold time.

A2: In the following Circuit, Find out whether there is any Setup Or Hold Violation?

[5]
Solution:
Hold Analysis:
When a hold check is performed, we have to consider two things-

 Minimum Delay along the data path.


 Maximum Delay along the clock path.

If the difference between the data path and the clock path is negative, then a timing violation
has occurred. ( Note: there are few Exceptions for this)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path


= min(wire delay to the clock input of FF1) + min(Clk-to-Q delay of FF1) +min(cell delay of
inverter) + min(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 1+9+6+(1+1)=18ns

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay


= max(wire delay from CLK to Buffer input) + max(cell delay of Buffer) + max(wire delay from
Buffer output to FF2/CLK pin) + (hold time of FF2)
=Tclk = 3+9+3+2 = 17 ns

Hold Slack = Td - Tclk = 18ns -17ns = 1ns


Since Hold Slack is positive-> No hold Violation.

Setup Analysis:
When a setup check is performed, we have to consider two things-

 Maximum Delay along the data path.


 Minimum Delay along the clock path.

If the difference between the clock path and the data path is negative, then a timing violation
has occurred. ( Note: there are few Exceptions for this)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path


= max(wire delay to the clock input of FF1) + max(Clk-to-Q delay of FF1) +max(cell delay of
inverter) + max(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 2+11+9+(2+2) = 26ns

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay


= (Clock period) + min(wire delay from CLK to Buffer input) + min(cell delay of Buffer) +
min(wire delay from Buffer output to FF2/CLK pin) - (Setup time of FF2)
=Tclk = 15+2+5+2-4=20ns
Setup Slack = Tclk - Td = 20ns - 26ns = -6ns.
Since Setup Slack is negative -> Setup violation

A3: In order to work correctly, what should be the Setup and Hold time at Input A in the
following Circuit. Also find out the maximum operating frequency for this circuit. (Note:
Ignore Wire delay). Where Tsu- Setup time; Thd-Hold Time; Tc2q- Clock-to-Q delay

[5]
Solution:
Step1: Find out the maximum Register to register Delay.

Max Register to Register Delay


= (clk-to-Q delay of U2) + (cell delay of U3) + (all wire delay) + (setup time of U1)
= 5 + 8 + 3 = 16 ns.
Note:

 There are 2 register to register paths


o U2 -> U3 ->U1 (Delay=5+8+3=16ns)
o U1 -> U4 -> U2 ( Delay=5+7+3=15ns)
 We have to pick maximum one.

Step2: Find Out Setup Time:


A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)
= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)
= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
= 3 + (1+8 ) - 2 = 10 ns
Note:
Here we are not using the Clock period. Because we are not suppose to calculate the Setup
violation. We are calculating Setup time.

 All the wire dealy is neglected. If Wire delay present, we have to consider those one.
 There are 2 Data path
o A -> U7 -> U4 -> D of U2 (Data path Delay = 1+7 =8ns )
o A -> U7 -> U3 -> D of U1 ( Data path Delay = 1+8 =9ns )
 Since for Setup calculation we need maximum Data path delay, we have choosen 2nd for
our calculation.

Step3: Find Out Hold Time:


A hold time = Hold time of Flipflop + max(Clock path Delay) - min( Data path delay)
=( Hold time of Flipflop + Clk path max delay) - (A2D max delay)
= Thd + Tpd U8 - (Tpd U7 + Tpd U4+wire delay)
= 4 + 2 - (1+7 ) = -2 ns

Step4: Find out Clock to Out Time:

Clock to Out
= Cell delay of U8 + Clk-to-Q delay of FlipFlop+ Cell delay of U5+ Cell delay of U6+ (all wire
delay)
= Tpd U8+ U2 Tc2q + U5 Tpd + U6 Tpd
= 2 + 5 + 9 + 6 = 22 ns

Note:

 There are 2 Clock to Out path- one from Flip flop U1 and other from U2.
 Since in this case the Clk-to-Q path for both Flipflop is same, we can consider any path.
But in some other Circuit where the delay is different for both the paths, we
should consider Max delay path.

Step5: Find Pin to Pine Combinational Delay (A to Y delay)

Pin to Pin Combinational Delay (A to Y)


= U7 Tpd + U5 Tpd + U6 Tpd
= 1 + 9 + 6 = 16 ns

Step5: Find Out Max Clock Frequency:


Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)
= 1/ Max (16, 22, 16)
= 45.5 Mhz

So summery is:

Parameter Description Min Max Units


Tclk Clock Period 22 Ns
Fclk Clock Frequency 45.5 Mhz
Atsu A setup time 10 Ns
Athd A hold time -2 Ns
A2Y A to Y Tpd 16 Ns
Ck2Y Clock to Y tpd 22 Ns

A4: How to solve setup & Hold violations in the design


To solve setup violation
1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx]
3. Tweak launch-flop to have better slew at the clock pin, this
will make CK->Q of launch flop to be fast there by helping fixing
setup violations
4. Play with skew [ tweak clock network delay, slow-down clock to
capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews)
To solve Hold Violations
1. Adding delay/buffer[as buffer offers lesser delay, we go for spl
Delay cells whose functionality Y=A, but with more delay]
2. Making the launch flop clock reaching delayed
3. Also, one can add lockup-latches [in cases where the hold time
requirement is very huge, basically to avoid data slip]

A5: The D ip-ops below have setup time ts = 18 ns and hold time th = 4 ns..

a.Suppose the clock is delayed by exactly 10 ns. (See the left device in the figure above.) What
are the setup and hold times for this modified flip-flop?
Sol:
When the clock is delayed, the data may be delayed by the same amount without violating
the setup time. But the hold time is increased because the clock does not arrive until later.
Setup time: ts = 18 - 10 = 8 ns Hold time: th = 4 + 10 = 14 ns

b. Suppose the data input is delayed by exactly 10 ns. (See the right device in the figure
above.) What are the setup and hold times for this modified flip-flop?

Setup time: ts = 18 + 10 = 28 ns Hold time: th = 4 - 10 = -6 ns

A6: What is the work of synchronizer?

IT is used to avoid metastability, which occurs during transfer of data from one clock domain to
another asynchronous clock domain. It resolves setup time & Hold time violation.

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