Verilog code for all gates:

module gate_d(a, b, y_not, y_and, y_or, y_nand, y_nor, y_xor, y_xnor);

input a,b;
output y_not, y_and, y_or, y_nand, y_nor, y_xor, y_xnor;
assign y_not = ~a;
assign y_and = a&b;
assign y_or = a|b;
assign y_nand = ~(a&b);
assign y_nor = ~(a|b);
assign y_xor = a^b;
assign y_xnor = ~(a^b);
endmodule

Testbench:

module gate_tb();
reg a,b;
wire y_not, y_and, y_or, y_nand, y_nor, y_xor, y_xnor;
gate_d uut(a,b, y_not, y_and, y_or, y_nand, y_nor, y_xor, y_xnor);
initial begin
a = 0; b = 0;
#10
b = 1;
#10
a = 1; b = 0;
#10
b = 1;
#10
$finish();
end
endmodule
1) RTL code for detecting whether the given 4-bit number is positive or negative:
module pos_neg_4bit(a_in,y_out);
input [3:0]a_in;
output y_out;
assign y_out = (a_in[3]!=0)?1'b1:1'b0;
endmodule

Testbench:
module pos_neg_4bit_tb();
reg [3:0]a_in;
wire y_out;
integer i;
pos_neg_4bit dut(a_in, y_out);
initial
begin
for(i=0; i<16; i=i+1)
begin
{a_in} = i;
#10;
end
$finish;
end
endmodule

Output waveforms:
2) RTL code:
Not gate:
module not_gate(output reg Y, input A);
always @ (A) begin
if (A == 1'b0) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule

And gate:
module and_gate(output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b1 & B == 1'b1) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule

Or gate:
module or_gate(output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b0 & B == 1'b0) begin
Y = 1'b0;
end
else
Y = 1'b1;
end
endmodule
Nand gate:
module nand_gate(output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b1 & B == 1'b1) begin
Y = 1'b0;
end
else
Y = 1'b1;
end
endmodule

Nor gate:
module nor_gate(output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b0 & B == 1'b0) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule

Xor gate:
module xor_gate(output reg Y, input A, B);
always @ (A or B)
begin
if (A == 1'b0 & B == 1'b0) begin
Y = 1'b0;
end
else if (A == 1'b1 & B == 1'b1) begin
Y = 1'b0;
 end
else
Y = 1'b1;
end
endmodule

Xnor gate:
module xnor_gate(output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b0 & B == 1'b0) begin
Y = 1'b1;
end
else if (A == 1'b1 & B == 1'b1) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule

Testbench:
module logic_gates_tb;
reg A, B;
wire Y_not,Y_and, Y_or, Y_nand, Y_nor, Y_xor, Y_xnor;
integer i;
not_gate dut(Y_not, A);
and_gate dut1(Y_and, A, B);
or_gate dut2(Y_or, A, B);
nand_gate dut3(Y_nand, A, B);
nor_gate dut4(Y_nor, A, B);
xor_gate dut5(Y_xor, A, B);
xnor_gate dut6(Y_xnor, A, B);

initial
begin
for(i=0; i<4; i=i+1)
begin
 {A,B} = i;
#10;
end
$finish;
end
endmodule

/*module logic_gates_tb;
reg A, B;
wire Y_and, Y_or, Y_nand, Y_nor, Y_xor, Y_xnor;
and_gate dut(Y_and, A, B);
or_gate dut1(Y_or, A, B);
nand_gate dut2(Y_nand, A, B);
nor_gate dut3(Y_nor, A, B);
xor_gate dut4(Y_xor, A, B);
xnor_gate dut5(Y_xnor, A, B);

initial begin
A = 0; B = 0;
#10 A = 0; B = 1;
#10 A = 1; B = 0;
#10 A = 1; B = 1;
#10;
end
endmodule*/

Output waveforms:

3) RTL code of logic gates using 2*1mux:

module logicgates_21mux(a,b,Y_not, Y_and, Y_or, Y_nand, Y_nor, Y_xor, Y_xnor);
input a,b;
output Y_not, Y_and, Y_or, Y_nand, Y_nor, Y_xor, Y_xnor;
assign Y_not = a?1'b0:1'b1;
assign Y_and = a?b:1'b0;
assign Y_or = a?1'b1:b;
 assign Y_nand = a?~b:1'b1;
assign Y_nor = a?1'b0:~b;
assign Y_xor = a?~b:b;
assign Y_xnor = a?b:~b;
endmodule

Testbench:
module logicgates_21mux_tb();
reg A,B;
wire Y_not, Y_and, Y_or, Y_nand, Y_nor, Y_xor, Y_xnor;
integer i;
logicgates_21mux dut(A,B, Y_not, Y_and, Y_or, Y_nand, Y_nor, Y_xor, Y_xnor);
initial
begin
for(i=0; i<4; i=i+1)
begin
{A,B} = i;
#10;
end
$finish;
end
initial
$monitor("A=%b, B=%b",A,B);
endmodule

Output waveforms:

Synthesis:
4) RTL code for combinational logic:
module combinational_logic(a, b,c,d,e,f,g,h,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10);
input a,b,c,d,e,f,g,h;
output y1,y2,y3,y4,y5,y6,y7,y8,y9,y10;
//output y7;
//assign y1 = (~(((a&b)|c)&d))^d;
//assign y2 = ~((a|b)&c);
//assign y3 = ((~((~(~(~(((a^b)&c)|d))^e)&f)|g))^h);
//assign y4 = ~(((~(~(~(((a^b)&c)|d))^e)&f)|g)^h);
//assign y5 = ~(((~(~(~((~(a|b)&c)^d))&e)|f)^g)|h);
//assign y6 = ~((~((~((((~a)&b)|c)&d))|e)^f)|g);
//assign y7 = (~((~((((~(a^b)|c)^d)&e)|f))&g))^h;
//assign y8 = (((~((~((a|(~b))^c))&d))|e)^f)^g;
//assign y9 = (~(((a|b)^c)&d))^e;
assign y10 = (((~((((~a)&(~b))|c)&d))|e)^(~f));
endmodule

assign y = (a|b)&c;
assign y = (~(((a&b)|c)&d))^d;

assign y7 = (~((~((((~(a^b)|c)^d)&e)|f))&g))^h;

assign y8 = (((~((~((a|(~b))^c))&d))|e)^f)^g;
assign y9 = (~(((a|b)^c)&d))^e;

assign y10 = (((~((((~a)&(~b))|c)&d))|e)^(~f));

module mux_logicgates(x,a,b,c,d,s0,s1,s2,s3,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9,Y10);
input x,a,b,c,d,s0,s1,s2,s3;
output Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9,Y10;
assign Y1 = (s0?b:a)&c;
assign Y2 = (s0?b:a)^b;
assign Y3 = (s1?c:(s0?((~a)^(~b)):(a&b)))^c;
assign Y4 = (s0?a:(s1?b:(s2?c:(s3?d:x))));
assign Y5 = s1?((s0?b:a)|a):b;
assign Y6 = (s0?c:(~(a^b)))&c;
endmodule

assign Y1 = (s0?b:a)&c;

assign Y2 = (s0?b:a)^b;

assign Y3 = (s1?c:(s0?((~a)^(~b)):(a&b)))^c;

a
c b
d

assign Y4 = (s0?a:(s1?b:(s2?c:(s3?d:x))));

assign Y5 = s1?((s0?b:a)|a):b;
 assign Y6 = (s0?c:(~(a^b)))&c;

RTL code for 3bit ALU:

module alu_3bit1(a_mag,a_sign,b_mag,b_sign,out_mag,out_sign);
input [2:0]a_mag;
input a_sign,b_sign;
input [2:0]b_mag;
wire [2:0]a;
wire [2:0]b;
output [2:0]out_mag;
wire [2:0]out;
output out_sign;

assign a= a_sign?((~a_mag)+1'b1):a_mag;
assign b= b_sign?((~b_mag)+1'b1):b_mag;

assign out=a+b;
assign out_sign=out[2];
assign out_mag=out[2]?((~out)+1'b1):out;

endmodule

Testbench:
module alu_3bit_tb();
reg [2:0]a_mag;
reg [2:0]b_mag;
reg a_sign,b_sign;
wire [2:0]out_mag;
wire out_sign;
integer i;
alu_3bit1 dut(a_mag,a_sign,b_mag,b_sign,out_mag,out_sign);
initial
begin
for(i=0; i<256; i=i+1)
begin
{a_mag,b_mag,a_sign,b_sign} = i;
#10;
end
$finish;
end
endmodule
RTL code for 8bit ALU generating 2scompliment:
module alu_2comp(input [7:0]a, output [7:0]y_2comp);
wire [7:0]a_mag;
wire [7:0]b;
assign a_mag={1'b0,a[6:0]};
assign y_2comp = a[7]?((~a_mag)+1'b1):a_mag;
endmodule

Testbench:
module alu_2comp_tb();
reg [7:0]a;
wire [7:0]y_2comp;
integer i;
alu_2comp dut(a,y_2comp);
initial
begin
for(i=0; i<256; i=i+1)
begin
a = i;
#10;
end
$finish;
end
initial
$display("y_2comp=%b",y_2comp);
Endmodule
Verilog Code for Half adder:
module half_adder(input a,b, output sum,carry);
assign {carry,sum} = a+b;
endmodule

Halfadder Testbench:
module half_adder_tb();
reg a,b;
wire sum,carry;
integer i;
half_adder DUT(a,b,sum,carry);
initial
begin
for(i=0;i<4;i=i+1)
begin
{a,b}=i;
#10;
end
$finish;
end
initial
$monitor("Input a=%b, b=%b, Output sum =%b, carry=%b",a,b,sum,carry);
Endmodule

Output:

Verilog Code for Full adder:

module full_adder(input a_in,b_in,c_in,
output sum_out,carry_out);
assign {carry_out,sum_out} = a_in+b_in+c_in;
endmodule

Full adder Testbench:

module full_adder_tb();
reg a,b,cin;
wire sum,carry;
integer i;
full_adder DUT(a,b,cin,sum,carry);
initial
begin
for(i=0;i<8;i=i+1)
begin
 {a,b,cin}=i;
#10;
end
$finish;
end
initial
$monitor("Input a=%b, b=%b, c=%b, Output sum =%b, carry=%b",a,b,cin,sum,carry);
endmodule

Output:

Verilog Code for Half subtractor:

module half_subtractor(input a,b, output diff,borrow);
assign {borrow,diff} = a-b;
endmodule

Half subtractor Testbench:

module half_subtractor_tb();
reg A,B;
wire Diff,Borrow;
integer i;
half_subtractor DUT(.a(A),.b(B),.diff(Diff),.borrow(Borrow));
initial
begin
for(i=0;i<4;i=i+1)
begin
{A,B}=i;
#10;
end
$finish;
end
initial
$monitor("Input: A=%b, B=%b, Output: Diff =%b, Borrow=%b",A,B,Diff,Borrow);
endmodule

Output:
Verilog Code for Full subtractor:
module full_subtractor(input a_in,b_in,c_in,
output diff_out,borrow_out);
assign {borrow_out,diff_out} = a_in - b_in - c_in;
endmodule

Full subtractor Testbench:

module full_subtractor_tb();
reg A,B,C;
wire Diff,Borrow;
integer i;
full_subtractor DUT(.a_in(A),.b_in(B),.c_in(C),.diff_out(Diff),.borrow_out(Borrow));
initial
begin
for(i=0;i<8;i=i+1)
begin
{A,B,C}=i;
#10;
end
$finish;
end
initial
$monitor("Input: A=%b, B=%b, C=%b, Output: Diff =%b,
Borrow=%b",A,B,C,Diff,Borrow);
endmodule

Output:

RTL code for 2*1 mux using assign statement:

module mux21(a,s,Y);
input [1:0]a;
input s;
output Y;
assign Y = s?a[1]:a[0];
endmodule
Hardware:
RTL code for 2*1 mux using ifelse statement:
module mux21_ifelse(in,s,y);
input [1:0]in;
input s; Hardware:
output reg y;
always @(*)
begin
if(s==1'b0) y=in[0];
else y=in[1];
end
endmodule

RTL code for 2*1 mux using case statement:

module mux21_case(a,sel,out);
input [1:0]a;
input sel;
output reg out; Hardware:
always @(*)
case(sel)
1'b0:out=a[0];
1'b1:out=a[1];
endcase
endmodule
sel

Testbench:
module mux21_tb();
reg [1:0]A; reg S;
wire Y_21assign,Y_21ifelse,Y_21case;
integer i;
mux21 dut(.a(A),.s(S),.Y(Y_21assign));
mux21_ifelse dut1(.in(A),.s(S),.y(Y_21ifelse));
mux21_case dut2(.a(A),.sel(S),.out(Y_21case));
initial
begin
for(i=0; i<8; i=i+1)
begin
{S,A} = i;
#10; end
$finish; end
endmodule

Output:
RTL code for 4*1 mux using assign statement:
module mux41(a,s,Y);
input [3:0]a;
input [1:0]s;
output Y;
assign Y = ({s[1],s[0]} ==2'b00) ? a[0]:
( ({s[1],s[0]} ==2'b01) ? a[1]:
( ({s[1],s[0]} ==2'b10) ? a[2]:a[3]) );
endmodule
Hardware:

RTL code for 4*1 mux using ifelse statement:

module mux41_ifelse(in,s,y);
input [3:0]in;
input [1:0]s; Hardware:
output reg y;
always @(*)
begin
if(s==2'b00) y=in[0];
else if(s==2'b01) y=in[1];
else if(s==2'b10) y=in[2];
else y=in[3];
end
endmodule

RTL code for 4*1 mux using case statement:

module mux41_case(a,sel,out);
input [3:0]a;
input [1:0]sel; Hardware:
output reg out;
always @(*)
case(sel)
2'd0:out=a[0];
2'd1:out=a[1];
2'd2:out=a[2];
2'd3:out=a[3];
endcase
endmodule
Testbench:
module mux41_tb();
reg [3:0]A;
reg [1:0]S;
wire Y_41assign,Y_41ifelse,Y_41case;
integer i;
mux41 dut(.a(A),.s(S),.Y(Y_41assign));
mux41_ifelse dut1(.in(A),.s(S),.y(Y_41ifelse));
mux41_case dut2(.a(A),.sel(S),.out(Y_41case));
initial
begin
for(i=0; i<64; i=i+1)
begin
{S,A} = i;
#10;
end
$finish;
end
endmodule

Output:
RTL code for 8*1 mux using assign statement:
module mux81(a,s,Y);
input [7:0]a;
input [2:0]s;
output Y;
assign Y = ({s[2],s[1],s[0]} ==3'b000) ? a[0]:
( ({s[2],s[1],s[0]} ==3'b001) ? a[1]:
( ({s[2],s[1],s[0]} ==3'b010) ? a[2]:
( ({s[2],s[1],s[0]} ==3'b011) ? a[3]:
( ({s[2],s[1],s[0]} ==3'b100) ? a[4]:
( ({s[2],s[1],s[0]} ==3'b101) ? a[5]:
( ({s[2],s[1],s[0]} ==3'b110) ? a[6]:a[7] ))))));
endmodule
Hardware:

RTL code for 8*1 mux using ifelse statement:

module mux81_ifelse(in,s,y);
input [7:0]in;
input [2:0]s;
output reg y;
always @(*) Hardware:
begin
if(s==3'b000) y=in[0];
else if(s==3'b001) y=in[1];
else if(s==3'b010) y=in[2];
 else if(s==3'b011) y=in[3];
else if(s==3'b100) y=in[4];
else if(s==3'b101) y=in[5];
else if(s==3'b110) y=in[6];
else y=in[7];
end
endmodule

RTL code for 8*1 mux using case statement:

module mux81_case(a,sel,out);
input [7:0]a;
input [2:0]sel; Hardware:
output reg out;
always @(*)
case(sel)
3'd0:out=a[0];
3'd1:out=a[1];
3'd2:out=a[2];
3'd3:out=a[3];
3'd4:out=a[4];
3'd5:out=a[5];
3'd6:out=a[6];
3'd7:out=a[7];
endcase
endmodule

Testbench:
module mux81_tb();
reg [7:0]A;
reg [2:0]S;
wire Y_81,Y_81ifelse,Y_81case;
integer i;
mux81 dut(.a(A),.s(S),.Y(Y_81));
mux81_ifelse dut1(.in(A),.s(S),.y(Y_81ifelse));
mux81_case dut2(.a(A),.sel(S),.out(Y_81case));
initial
begin
for(i=0; i<2048; i=i+1)
begin
{S,A} = i;
#10;
end
$finish;
end
endmodule

Output:
RTL code for parameterized and gate:
`define and_num 5
module and_gate(output [(`and_num):0]Y, input [(`and_num):0]A, input [(`and_num):0]B);
genvar gen_i;
generate for(gen_i = 0; gen_i < (`and_num) ; gen_i = gen_i + 1)
begin:and_n
assign Y[gen_i] = A[gen_i] & B[gen_i]; end
endgenerate
endmodule

when we get x,z 5-10codes, blocking non blockings, default with example, if we miss one
variable in sensitivity list.
What is netlist
module half_subtractor(input a,b, output diff,borrow);
assign {borrow,sum} = a-b;
endmodule

module examp_tb;
reg [3:0] a,b,c;
reg [3:0]Y;
initial
begin
a=4'b1000;
b=4'b0101;
#10 Y=a+b;
#10; end
endmodule

4*1mux:
module mux41_assign(a,s,Y);
input [3:0]a;
input [1:0]s;
output Y;
endmodule
Testbench:
module mux41_tb();
reg [3:0]A;
reg [1:0]S;
wire Y_41assign,Y_41ifelse,Y_41case;
integer i;
mux41_assign dut(.a(A),.s(S),.Y(Y_41assign));
mux41_ifelse dut1(.s(S),.y(Y_41ifelse)); //result 2
mux41_case dut2(.a(A),.sel(S),.out(Y_41case));
initial
begin
for(i=0; i<64; i=i+1)
begin
A = i; #10; //result 1 // {S,A} = i; #10; //result 2
end
$finish; end
endmodule

Example of 2*1mux:
module mux21(a,s,Y);
 input [1:0]a;
input x;
output reg Y;
assign Y = s?a[1]:a[0]
endmodule

Syntax errors:
• Syntax errors occurs when written code does not follow the set of rules defined for the
syntax of the language.
• These are mistakes in the source code, such as spelling and punctuation errors.

Complilation errors:

Example :
module mux_case(a,sel,out);
input a,b;
input sel;
output reg out;
always @(*)
begin
case(sel)
1’b0: begin
out1=a;
out2=b; end
1’b1: out1=a;
endcase
end
endmodule
Full subtractor:
module full_subtractor(input a_in,b_in,c_in,
output diff_out,borrow_out);
assign {borrow_out,diff_out} = a_in - b_in - c_in;
endmodule

Full adder:
module full_adder(a_in,b_in,c_in,sum_out,carry_out);
input a_in,b_in,c_in;
output sum_out,carry_out;
wire b1,d1;
full_subtractor
FS1(.a_in(a_in),.b_in(b_in),.c_in(c_in),.diff_out(sum_out),.borrow_out(b1));

full_subtractor
FS2(.a_in(~a_in),.b_in(b_in),.c_in(c_in),.diff_out(d1),.borrow_out(carry_out));
endmodule

Full adder TB:

module full_adder_tb();
reg a,b,cin;
wire sum,carry;
integer i;
full_adder DUT(a,b,cin,sum,carry);
initial
begin
for(i=0;i<8;i=i+1)
begin
{a,b,cin}=i;
#10;
end
$finish;
end
initial
$monitor("Input a=%b, b=%b, c=%b, Output sum =%b, carry=%b",a,b,cin,sum,carry);
endmodule
Blocking assignment:
Module blocking(D,clock, Q);
Input D,clock;
Output reg Q;
Reg Q1;
always@(posedge clock)
begin
Q1=D;
Q2=Q1;
End
Endmodule

Non-Blocking assignment:
Module blocking(D,clock, Q);’
Input D,clock;
Output reg Q;
Reg Q1;
always@(posedge clock)
begin
Q1<=D;
Q2<=Q1;
End
endmodule
AND Gate netlist:
module and_netlist(input A,B, output Y_and);
and_gate1 dut(.a(A), .b(B),.y(Y_and));
endmodule

1)RTL code for logic gates:

module logic_gates(input a,
input b,
output y_not,
output y_and,
output y_or,
output y_nand,
output y_nor,
output y_xor,
output y_xnor);

assign y_not = ~a;

assign y_and = (a==0 | b==0)?1'b0:1'b1;
assign y_nand = (a==0 | b==0)?1'b1:1'b0;
assign y_or = (a==1 | b==1)?1'b1:1'b0;
assign y_nor = (a==1 | b==1)?1'b0:1'b1;
assign y_xor = ({a,b}==2'b00 | {a,b}==2'b11)?1'b0:1'b1;
assign y_xnor = ({a,b}==2'b00 | {a,b}==2'b11)?1'b1:1'b0;
endmodule

Netlist for logic gates:

module logic_gates_netlist(input a,
input b,
output y_not,
output y_and,
output y_or,
output y_nand,
output y_nor,
output y_xor,
output y_xnor);
 buf_1Y g1(.IN1(a), .OUT(y_buf));
not_1Y g2(.IN1(a), .OUT(y_not));
and_2Y g3(.IN1(a), .IN2(b), .OUT(y_and));
nand_2Y g4(.IN1(a), .IN2(b), .OUT(y_nand));
or_2Y g5(.IN1(a), .IN2(b), .OUT(y_or));
nor_2Y g6(.IN1(a), .IN2(b), .OUT(y_nor));
xor_2Y g7(.IN1(a), .IN2(b), .OUT(y_xor));
xnor_2Y g8(.IN1(a), .IN2(b), .OUT(y_xnor));
endmodule

2)RTL code for 3input AND gate using 2 AND gates:

module and_3input(input a,
input b,
input c,
output y_and);
wire y;
assign y=a&b&c;
//assign w1 = (a==0 | b==0)?1'b0:1'b1; //assign y_and = (w1==0 | c==0)?1'b0:1'b1;
endmodule

Netlist:
module and_3input_netlist(input a,
input b,
input c,
output y_and);
wire w1;
and_2input1 g1(.IN1(a), .IN2(b), .OUT(w1));
and_2input1 g2(.IN1(w1), .IN2(c), .OUT(y_and));
endmodule

Testbench:
module and_3input_tb;
reg A, B,C;
wire Y_and;
integer i;
and_3input dut( A, B, C, Y_and);
initial
begin
for(i=0; i<8; i=i+1)
begin
{A,B,C} = i;
#10;
end
$finish;
end
endmodule
3) RTL code for OR gate using NOR,NOT gates:
module or_gate_nornot(input a, b, output y_or);
wire y_nor;
assign y_nor = (a==1 | b==1)?1'b0:1'b1;
assign y_or = ~y_nor;
endmodule

Netlist:
module or_gate_nornot_netlist(input a,b, output y_or);
wire y_nor;
nor_gate_nornot11 dut(.IN1(a), .in2(b), .OUT(y_nor));
or_gate_nornot11 dut1(.IN1(y_nor), .OUT(y_or));
endmodule

3) RTL code for OR gate using NOT,AND gates:

module or_gate_notand(input a, b, output y_or);
wire y_no1,y_not2;
assign y_not1 = ~a;
assign y_not2 = ~b;

assign y_or = y_not1 & y_not2;

endmodule

Netlist:
module or_gate_nornot_netlist(input a,b, output y_or);
wire y_not;
not_gate_not11 g1(.IN1(a), .OUT(y_not1));
not_gate_not11 g2(.IN1(b), .OUT(y_not2));
or_gate_nornot11 g3(.IN1(y_not1), .IN2(y_not1), .OUT(y_or));
endmodule

1)RTL code for 2*1mux:

module mux21_netlist(input [1:0]a,
input s,
output Y);
wire sbar,w1,w2;
assign Y = ((~s)&a[0]) | (s&a[1]);
endmodule
Netlist:
module mux21_netlist(input [1:0]a,
input s,
output Y);
wire sbar,w1,w2;
not_1in g1(.IN1(s), .OUT(sbar));
and_2in g2(.IN1(a[0]), .IN2(sbar), .OUT(w1));
and_2in g3(.IN1(a[1]), .IN2(s), .OUT(w2));
or_2in g4(.IN1(w1), .IN2(w2), .OUT(Y));
endmodule

2)RTL code for 4*1mux:

module mux41_case(input [3:0]a,
input [1:0]s,
output reg out);
always @(*)
case(s)
2'd0:out=a[0];
2'd1:out=a[1];
2'd2:out=a[2];
2'd3:out=a[3];
endcase
endmodule

Netlist:
module mux41_netlist(input [3:0]a,
input [1:0]s,
output Y);
wire s1bar,s0bar,w1,w2,w3,w4;
not_1in g1(.IN1(s[0]), .OUT(s0bar));
not_1in g2(.IN1(s[1]), .OUT(s1bar));
and_2in g3(.IN1(a[0]),. IN2(s1bar),. IN3(s0bar),.OUT(w1));
and_2in g4(.IN1(a[1]),. IN2(s1bar),. IN3(s[0]),.OUT(w2));
and_2in g5(.IN1(a[2]),. IN2(s[1]),. IN3(s0bar),.OUT(w3));
and_2in g6(.IN1(a[3]),. IN2(s[1]),. IN3(s[0]),.OUT(w4));
or_2in g7(.IN1(w1),. IN2(w2),. IN3(w3),.IN4(w4),.OUT(Y));
endmodule

3)RTL code for Halfadder:

module half_adder(input a,b, output sum,carry);
assign {carry,sum} = a+b;
endmodule

Netlist:
module halfadder_netlist(input a,b, output sum,carry);
xor_2in g1(.IN1(a),.IN2(b),.OUT(sum));
and_2in g2(.IN1(a),.IN2(b),.OUT(carry));
endmodule
1)
Verilog code of 2*1mux:
module mux21(input a0,
input a1, input sel,
output out);
assign out = sel?a1:a0;
endmodule

Verilog code of Fulladder using 2*1mux:

module fulladder_21mux(input a,
input b,
input c,
output sum,
output carry);
wire axorb, c_axorb, aandb;
mux21 MUX1(.a0(a),.a1(~a),.sel(b), .out(axorb));
mux21 MUX2(.a0(c),.a1(~c),.sel(axorb), .out(sum));
mux21 MUX3(.a0(1'b0),.a1(axorb),.sel(c), .out(c_axorb));
mux21 MUX4(.a0(1'b0),.a1(a),.sel(b), .out(aandb));
mux21 MUX5(.a0(c_axorb),.a1(aandb),.sel(aandb), .out(carry));
endmodule

Netlist of Fulladder using 2*1mux:

module fulladder_21mux_netlist(input a,
input b,
input c,
output sum,
output carry);
wire axorb, c_axorb, aandb;
xor_2in g1(.IN1(a),.IN2(b),.OUT(axorb));
xor_2in g2(.IN1(axorb),.IN2(c),.OUT(sum));
and_2in g3(.IN1(a),.IN2(b),.OUT(aandb));
and_2in g4(.IN1(axorb),.IN2(c),.OUT(c_axorb));
or_2in g5(.IN1(c_axorb),.IN2(aandbb),.OUT(carry));
endmodule
2)RTL code for Half adder using case statement:
module halfadder_case(
input a,
input b,
output reg sum,
output reg carry);
always @(*)
begin
case ({a,b})
2'b00: begin sum = 0; carry = 0; end
2'b01: begin sum = 1; carry = 0; end
2'b10: begin sum = 1; carry = 0; end
2'b11: begin sum = 0; carry = 1; end
// default : begin sum = 0; carry = 0; end
endcase
end
endmodule

3)RTL code for Full adder using case statement:

module fulladder_case(
input a,
input b,
input c,
output reg sum,
output reg carry);
always @(*)
begin
case ({a,b,c})
3'b000: begin sum = 0; carry = 0; end
3'b001: begin sum = 1; carry = 0; end
3'b010: begin sum = 1; carry = 0; end
3'b011: begin sum = 0; carry = 1; end
3'b100: begin sum = 1; carry = 0; end
3'b101: begin sum = 0; carry = 1; end
3'b110: begin sum = 0; carry = 1; end
3'b111: begin sum = 1; carry = 1; end
default : begin sum = 0; carry = 0; end
endcase
end
endmodule

Which of the following is a valid syntax for accessing a single element within an array?
@array [0] @array $array[index] $array None of the above