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Tutorial Sheet

This document contains tutorial questions and solutions related to implementing logic circuits using Programmable Logic Devices (PLDs) such as PROMs and PLAs. It includes questions about determining the size of PROMs needed for different logic circuits, showing logic arrangements to implement a full adder using PROM and PLA, and designing a PLA for a magnitude comparator and converter by deriving Boolean equations and minimizing them using Karnaugh maps. The solutions analyze the circuit requirements and provide simplified logic expressions and PLD implementations.

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أمير نصيف محسن
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© © All Rights Reserved
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39 views

Tutorial Sheet

This document contains tutorial questions and solutions related to implementing logic circuits using Programmable Logic Devices (PLDs) such as PROMs and PLAs. It includes questions about determining the size of PROMs needed for different logic circuits, showing logic arrangements to implement a full adder using PROM and PLA, and designing a PLA for a magnitude comparator and converter by deriving Boolean equations and minimizing them using Karnaugh maps. The solutions analyze the circuit requirements and provide simplified logic expressions and PLD implementations.

Uploaded by

أمير نصيف محسن
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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University College of Madenat El-Elem Types of FPLD

Computer Eng.Tech. Dept. Tutorial Sheet


Advance Digital Electronics Lecturer: Fatima H.Fakhri
Q.1\ Implementation the Boolean function using 8x2 PROM

Solution:

One would need a 2n × m PROM, where n is the number of inputs and m is the
number of outputs

Q.2\ Determine the size of the PROM required for implementing the following
logic circuits:
(a) a binary multiplier that multiplies two four-bit numbers;
(b) a dual 8-to-1 multiplexer with common selection inputs;

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University College of Madenat El-Elem Types of FPLD
Computer Eng.Tech. Dept. Tutorial Sheet
Advance Digital Electronics Lecturer: Fatima H.Fakhri
(c) a single-digit BCD adder/subtractor with a control input for selection of
operation

Solution:
(a) The number of inputs required here would be eight. The result of multiplication
would be in eight bits. Therefore, the size of the PROM=28×8=256×8.
(b) The number of inputs =8+8+3=19 (the number of selection inputs=3). The
number of outputs = 2. Therefore, the size of the PROM = 219 ×2 = 512K×2.
(c) The number of inputs=4 (augend bits) +4 (addend bits)+1 (carry-in)+1 (control
input)=10. The number of outputs=4 (sum or subtraction output bits)+1 (carry or
borrow bit)=5. The size of the PROM= 210 ×5 =1024×5 =1K×5.

Q.3\Show the logic arrangement of both a PROM and a PLA required to


implement a binary full adder.
Solution:
The Boolean expressions for sum S and carry-out Co can be written as follows:

If we simplify the Boolean expressions for the sum and carry outputs, we will find
that the expression for the sum output cannot be simplified any further, and also
that the expression for carry-out can be simplified to three product terms with
fewer literals. If we examine even the existing expressions, we find that we would
need seven AND gates in the PLA implementation. And if we use the simplified
expressions, even then we would require the same number of AND gates.
Therefore, the simplification here would not help as far as its implementation with

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University College of Madenat El-Elem Types of FPLD
Computer Eng.Tech. Dept. Tutorial Sheet
Advance Digital Electronics Lecturer: Fatima H.Fakhri
a PLA is concerned. Figure B shows the implementation of a full adder with a PLA
device.
A) Using 8x2 PROM to implement the full adder

B) Using PLA

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University College of Madenat El-Elem Types of FPLD
Computer Eng.Tech. Dept. Tutorial Sheet
Advance Digital Electronics Lecturer: Fatima H.Fakhri
Q.4\ We have two two-bit binary numbers A 1A0 and B1B0. Design a PLA device to
implement a magnitude comparator to produce outputs for A 1A0 being ‘equal to’,
‘not equal to’, ‘less than’ and ‘greater than’ B1B0.
Solution
Table below shows the function table with inputs and desired outputs. The Boolean
expressions for the desired outputs are given in the following equations:

4
University College of Madenat El-Elem Types of FPLD
Computer Eng.Tech. Dept. Tutorial Sheet
Advance Digital Electronics Lecturer: Fatima H.Fakhri
After simplification using K-map the equations will be:

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University College of Madenat El-Elem Types of FPLD
Computer Eng.Tech. Dept. Tutorial Sheet
Advance Digital Electronics Lecturer: Fatima H.Fakhri
Q.4\ Table below shows the function table of a converter. Starting with the
Boolean expressions for the four outputs (P, Q, R, S), minimize them using
Karnaugh maps and then hardware-implement this converter with a suitable PLD
with PAL architecture.

Solution:
From the given function table, we can write the Boolean expressions for the four
outputs as follows:

6
University College of Madenat El-Elem Types of FPLD
Computer Eng.Tech. Dept. Tutorial Sheet
Advance Digital Electronics Lecturer: Fatima H.Fakhri

7
University College of Madenat El-Elem Types of FPLD
Computer Eng.Tech. Dept. Tutorial Sheet
Advance Digital Electronics Lecturer: Fatima H.Fakhri
Using K-map to simplify the equations:

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