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Cmsc132part1 3rdexam

This document contains 8 questions about computer architecture concepts like caches, memory hierarchy, and addressing. It asks the reader to analyze cache performance, explain cache design tradeoffs, derive address mapping schemes for different cache configurations, and recommend an upgrade to improve system performance based on given cache hit/miss rates and memory speeds.

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warlic978
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284 views2 pages

Cmsc132part1 3rdexam

This document contains 8 questions about computer architecture concepts like caches, memory hierarchy, and addressing. It asks the reader to analyze cache performance, explain cache design tradeoffs, derive address mapping schemes for different cache configurations, and recommend an upgrade to improve system performance based on given cache hit/miss rates and memory speeds.

Uploaded by

warlic978
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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CMSC 132 3rd Exam (Part 1) 1.

Suppose you had a computer that, on average, exhibited the following properties on the programs that you run: Instruction miss rate: 1.5% Data miss rate: 4.0% Percentage of memory instructions: 30% Miss penalty: 70 cycles There is no penalty for a cache hit (i.e. the cache can supply the data as fast as the processor can consume it). Assume also that a cache-block is one word. You want to upgrade the computer, and your budget will allow one of the following: Get a new processor that is twice as fast as your current computer. The new processors cache is twice as fast too, so it can keep up with the processor. Get a new memory that is twice as fast. Which is a better choice? Explain fully, showing a quantitative comparison between the two choices. 2. Explain why a DRAM cell has to be re-written after a read operation. Why does it also have to be refreshed periodically, even if it is not read? 3. Modern processors have 3 levels of caches inside. For example, Core i7 has 32KB L1, 256KB L2, and 8MB L3 caches. Explain why they have multiple levels of caches instead of one big monolithic cache? 4. A data cache has the following configuration: Cache structure is directed-mapped Cache policy is write-back and write-allocate Cache size is 256B Cache line size is 16 bytes and a word is 32-bit Cache is indexed with physical address and the size of physical address is 32-bit Draw the detailed cache structure. Specify which parts of the physical address are used for tag, index, block offset, and byte offset to select a word. 5. A processor runs at 2 GHz and has a CPI of 1.2 without including the stall cycles due to cache misses. Load and store instructions count 30% of all instructions. The processor has an I-cache and a D-cache. The hit time is 1 clock cycle. The I-cache has a 2% miss rate. The D-cache has a 5% miss rate on load and store instructions. The miss penalty is 50 ns, which is the time to access and transfer a cache block betweenmain memory and the processor. a) What is the average memory access time for instruction access in clock cycles? b) What is the average memory access time for data access in clock cycles? c) What is the number of stall cycles per instruction and the overall CPI? d) You are considering replacing the 2 GHz CPU with one that runs at 4 GHz, but is otherwise identical. How much faster does the new processor run? Assume that hit time in the I-cache and the D-

cache is 1 clock cycle in the new processor, and the time to access and transfer a cache block between main memory and the processor is still 50 ns. 6) Consider a direct-mapped cache with 128 blocks. The block size is 32 bytes. a) Find the number of tag bits, index bits, and offset bits in a 32-bit address. b) Find the number of bits required to store all the valid and tag bits in the cache. c) (BONUS) Given the following sequence of address references in decimal: 20000, 20004, 20008, 20016, 24108, 24112, 24116, 24120 Starting with an empty cache, show the index and tag for each address and indicate whether a hit or a miss. 7) Suppose you own a computer that exhibits the following properties on the programs that you run: the pipeline can accept a new instruction every cycle the cache can provide data every cycle (i.e. no penalty for cache hits) the instruction cache miss rate is 2.5% the data cache miss rate is 3.5% 30% of instructions are memory instructions the cache miss penalty is 80 cycles. Suppose, also, that you have decided to purchase a new computer. For the budget allocated, you can either purchase a machine with a processor and cache that is twice as fast as your current one (memory speed is the same as the old machine, though), or purchase a machine with a processor and cache that is the same speed as your old machine but in which the cache is twice as large. Assume, for the purposes of this problem, that the cache miss rate for the programs you run will drop by 40% with this larger cache (although this is generally not true in the real world). Which computer are you best off purchasing? Explain in detail, showing the relative performance of each choice. 8) Suppose physical addresses are 32 bits wide. Suppose there is a cache containing 256K words of data (not including tag bits), and each cache block contains 4 words. For each of the following cache configurations, a. direct mapped b. 2-way set associative c. 4-way set associative d. fully associative specify how the 32-bit address would be partitioned. For example, for a direct mapped cache, you would need to specify which bits are used to select the cache entry and which bits are used to compare against the tag stored in the cache entry.

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