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16×4 Ram

The document discusses the operation of a 4x4 RAM using VHDL, including the theory of static RAM memories which retain their state using latches and inverters, and a behavioral VHDL code that models the reading and writing of data to the RAM. The procedure describes opening a new VHDL source file, writing the code to model the 4x4 RAM, simulating it, and verifying the output matches the input data. The result confirms the operation of a 4x4 RAM was successfully studied using the VHDL hardware description language.

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giridhar chikka
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19 views5 pages

16×4 Ram

The document discusses the operation of a 4x4 RAM using VHDL, including the theory of static RAM memories which retain their state using latches and inverters, and a behavioral VHDL code that models the reading and writing of data to the RAM. The procedure describes opening a new VHDL source file, writing the code to model the 4x4 RAM, simulating it, and verifying the output matches the input data. The result confirms the operation of a 4x4 RAM was successfully studied using the VHDL hardware description language.

Uploaded by

giridhar chikka
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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X
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Date:3o -9-16
IG x4 RAM USING TCAI87
opealien o>
of RAN (t6x4) usfng
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ArrARATUS
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hardwae: Spatan
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Memeries that ehe
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3 RAtMI Consists of two tansates
a latch and
invereYs
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ohich act as
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capaeftor. dyna mt RAM
a chage
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lhen column (sense) end row (eonto) lines
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heet o

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use 3EEE. td.togiett
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dotain, horlo );
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end rom;
oTchitectuore behavtdal of 1am u
dd logc-vet) (e couonto b);
subtype obype i
ype mem.type
Ainal menoy mem.type;
sd.togi.vectoi (o dounto ))
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Moniable venult irntegen;
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for f in x aam loop

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ond looP
return result
end tonv-inteqo;
beg?n
proces (v0,en.l,datain , ada)
beqin
{University College of Engineering JNTUK
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9 0 0

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Sheet No. y
f (en.lslo') then
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conv.integet adda)e dala in):
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ta cut "zzzz":
els it (rw)then
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dota out e not
end ifs
end proces;
poo ces;
end behavioal;
PRoCEDURF:
ic8n of
of ibink 8-(i
6.(:
1) Open TSE a new souYCe
3, Open new project n -fle and open
vIDL eole progiam în module
3) U0te
be
ßs d.d.208DrS.
4) Save the pi0gham and check
-found.
5) CoyTect the erOY
ony
foy test bench o aveform
6) Opon onothen sowce interest.
and set output as per

RESULT
Hence, -the epeat on ofR (6x4) sing
HDL language is-tudied

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