UNIT V

VHDL and HDL

Introduction to VHDL and HDL:
In the mid-1980’s the U.S. Department of Defense and the IEEE
sponsored the development of a hardware description language with
the goal to develop very high-speed integrated circuit.
ie VHDL -VHSIC (Very High Speed Integrated Circuits) Hardware
Description Language.
The other powerful widely used hardware description language is
Verilog.
A third HDL language is ABEL (Advanced Boolean Equation
Language) which was specifically designed for Programmable Logic
Devices (PLD). ABEL is less powerful than the other two languages
and is less popular in industry
VHDL versus conventional programming
languages
(1) A hardware description language is
inherently parallel, i.e. commands, which
correspond to logic gates, are executed
(computed) in parallel, as soon as a new input
arrives.
(2) A HDL program mimics the behavior of a
physical, usually digital, system.
(3) It also allows incorporation of timing
specifications (gate delays) as well as to
describe a system as an interconnection of
different components.
Levels of representation and abstraction

The highest level of

abstraction is the behavioral
level that describes a system
in terms of what it does (or
how it behaves)
Example: A simple circuit that warns car passengers
when the door is open or the seatbelt is not used
whenever the car key is inserted in the ignition lock

At the behavioral level this could be expressed as,

Warning = Ignition_on AND ( Door_open OR
Seatbelt_off)

The structural level, describes a system as a

collection of gates and components that are
interconnected to perform a desired function

Structural representation
of a “buzzer” circuit
The behavioral level can be further divided into two kinds of
styles: Data flow and Sequential.
The dataflow representation describes how data moves through
the system. This is typically done in terms of data flow between
registers (Register Transfer level). The data flow model makes use
of concurrent statements that are executed in parallel as soon as
data arrives at the input.
sequential statements are executed in the sequence that they are
specified.
VHDL allows both concurrent and sequential signal assignments
that will determine the manner in which they are executed.
Mixed level design consists both behavioral and structural
design in one block diagram.
Basic Structure of a VHDL file

(a) Entity
Each entity is modeled by an entity declaration and an
architecture body.
The entity declaration as the interface to the outside
world that defines the input and output signals.

The architecture body contains the description of

the entity and is composed of interconnected
entities, processes and components, all operating
concurrently,
 a. Entity Declaration
The entity declaration defines the NAME of the
entity and lists the input and output
ports. The general form is as follows,
entity
NAME_OF_ENTITY is [generic
generic_declarations);]
port
(signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end
[NAME_OF_ENTITY] ;
An entity declaration always ends with the keyword end, optionally []
followed by the name of the entity
Example 1:
entity FULLADDER is
-- (After a double minus sign (-) the rest of the
-- line is treated as a comment)
-- Interface description of FULLADDER
port ( x, y, Ci: in bit;
S, CO: out bit);
end FULLADDER;
 mode: is one of the reserved words to indicate the signal direction:

in – indicates that the signal is an input

out – indicates that the signal is an output of the entity whose value can
only be read by other entities that use it.
buffer – indicates that the signal is an output of the entity whose value can
be read inside the entity’s architecture
inout – the signal can be an input or an output.
type: a built-in or user-defined signal type. Examples of types are bit,
bit_vector, Boolean, character, std_logic, and stc_ulogic.
bit – can have the value 0 and 1
bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7) std_logic,
std_ulogic, std_logic_vector, std_ulogic_vector: can have 9
values to indicate the value and strength of a signal. Std_ulogic and
std_logic are preferred over the bit or bit_vector types.
o boolean – can have the value TRUE and FALSE
o integer – can have a range of integer values
o real – can have a range of real values
o character – any printing character
o time – to indicate time
generic: generic declarations are optional

entity AND3 is
port (in1, in2, in3:in std_logic;
out1:out std_logic);
end AND3;

a digital system accurately including the binary values 0 and 1,

as well as the unknown value X, the uninitialized value U, “-”
for don’t care, Z for high impedance, and several symbols to
indicate the signal strength (e.g. L for weak 0, H for weak 1, W
for weak unknown).
entity mux4_to_1 is
port(I0,I1,I2,I3:in std_logic;
S: in std_logic_vector(1downto 0);
y: out std_logic);
end mux4_to_1;

entity dff_sr is
port (D,CLK,S,R:in std_logic;
Q,Qb: out std_logic);
end dff_sr;
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
:
end architecture_name;
The types of Architecture are:
(a) The behavioral Model
(b) Structure Model
(c) Mixed Model
Architecture behavioral of BUZZER is
begin
WARNING <= (not DOOR and IGNITION)or (not SBELT and IGNITION);
end behavioral;

The “<=” symbol represents an assignment operator and assigns the value of the
expression on the right to the signal on the left.

The behavioral description of a 3 input AND gate is shown below.

entity AND3 is
port (in1, in2, in3: in std_logic;
out1: out std_logic);
end AND3;
architecture behavioral_2 of AND3 is
begin
out1 <= in1 and in2 and in3;
end behavioral_2;
entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;
architecture behavioral_xnor of XNOR2 is
-- signal declaration (of internal signals X, Y)
signal X, Y: std_logic;
begin
X <= A and B;
Y <= (not A) and (not B);
Z <= X or Y;
End behavioral_xnor;
The behavioral description of a 3 input AND gate
is shown below.
entity AND3 is
port (in1, in2, in3: in std_logic;
out1: out std_logic);
end AND3;
architecture behavioral_2 of AND3 is
begin
out1 <= in1 and in2 and in3;
end behavioral_2;
Entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;
architecture behavioral_xnor of XNOR2 is
-- signal declaration of internal signals X, Y)
signal X, Y:std_logic;
begin
X <= A and B;
Y <= (not A) and (not B);
Z <= X or Y;
End behavioral_xnor;
 SR Flip Flop:
Entity SRFF is
Port (S, R: in std_logic;
Q, Qb: out std_logic);
end SRFF;
architecture behavioral_2 of SRFF
begin
Q <= NOT (S and Qb);
Qb <= NOT ( R and Q);
end behavioral_2;

Concurrency
The signal assignments in the above examples are concurrent
statements. This implies that the statements are executed when one or
more of the signals on the right hand side change their value (i.e. an
event occurs on one of the signals).
a change of the current value of a signal is called an event.
 Digital systems are basically data-driven and an event
which occurs on one signal will lead to an event on another
signal, etc. Hence, the execution of the statements is
determined by the flow of signal values. As a result, the
order in which these statements are given does not matter

architecture CONCURRENT of FULLADDER is

begin
S <= x xor y xor Ci after 5 ns;
CO <= (x and y) or (y and Ci) or (x and Ci) after 3 ns;
end CONCURRENT;

Event Scheduling:
The mechanism of delaying the new value is called scheduling an event. In the above
example, assignment to signals S and CO does not happen instantly. The after
(keyword) clause delays the assignment of the new value to S and CO by 3 ns.
end behv2;
The statement WHEN…..ELSE conditions are executed one at a time in sequential
order until the conditions of a statement are met. The first statement that matches the
conditions required assigns the value to the target signal. The target signal for this
example is the local signal Q. Depending on the values of signals S and R, the values
Q,1,0 and Z are assigned to Q.
If more than one statements conditions match, the first statement that matches
does the assign, and the other matching state.
In with …select statement all the alternatives are checked simultaneously to find a
matching pattern. Therefore the with … select must cover all possible values of the
selector
 Structural Descriptions
component_label:component_name port map(signal_mapping);

If one of the ports has

no signal connected
to it (this happens, for
example, when there
are unused outputs), a
reserved word open
may be used.
Example 2:Four Bit Adder – Illustrating a structural model: VHDL
VHDL Operators
The operand is on the left of the operator and the number (integer) of shifts is on the
right side of the operator. As an example,
variable NUM1 :bit_vector := “10010110”; NUM1 srl 2;
will result in the number “00100101”.
When a negative integer is given, the opposite action occurs, i.e. a shift to the left
will be a shift to the right. As an example
NUM1 srl –2 would be equivalent to NUM1 sll 2 and give the result “01011000”.
Other examples of shift operations are for the bit_vector A = “101001”
variable A: bit_vector :=”101001”;
The remainder (rem) and modulus (mod) are defined as follows:
A rem B = A –(A/B)*B (in which A/B in an integer)
A mod B = A – B * N (in which N is an integer)

The result of the rem operator has the sign of its first operand while the result of the mod
operators has the sign of the second operand.

Some examples of these operators are given

below.
11 rem 4 results in 3
(-11) rem 4 results in -3
9 mod 4 results in 1
7 mod (-4) results in –1 (7 – 4*2 = -1).
All of the values of an enumerated type are user defined.
Structure of Verilog module:
module module_name(signal_names)
Signal_type signal_names;
Signal_type signal_names;
Assign statements
Assign statements
Endmodule_name
Verilog Ports:
◼ Input: The port is only an input port. In any assignment statement, the port should
appear only on the right hand side of the statement
◼ Output: The port is an output port. The port can appear on either side of the
assignment statement.
◼ Inout: The port can be used as both an input & output. The inout represents a
bidirectional bus.
Verilog Value Set:
◼ 0 represents low logic level or false condition
◼ 1 represents high logic level or true condition
◼ x represents unknown logic level
◼ z represents high impedance logic level