An

Industrial Training Report

on

VLSI Foundation
At

PinE Training Academy

Report submitted in partial fulfillment of the requirement for award of

Bachelor of Technology
by

Osheen Gorakh

Roll No.-300702820025

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

ENGINEERING

GOVERNMENT ENGINEERING COLLEGE, BILASPUR

Approved by AICTE Affiliated to CSVTU, Bhilai Newai
Koni, Bilaspur, Chhattisgarh 495009

I
 DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION
ENGINEERING

GOVERNMENT ENGINEERING COLLEGE BILASPUR

CERTIFICATE
This is to certify that the “Internship report” submitted by Osheen Gorakh (300702820025) is
work done by her and submitted during 2023 – 2024 academic year, in partial

Fulfillment of the requirements for the award of the degree of BACHELOR OF TECHNOLOGY
in OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, at PinE Training Academy.

Department Internship Coordinator

Assistant Prof. Deepika Bairagi

Head of the Department

Dr. Seema Chauhan

II
INDUSTRIAL TRAINING CERTIFICATE

III
 ACKNOWLEDGEMENT

First I would like to thank Mr. VAIBHAV MISHRA, HR, Head, of PINE ACADEMY, Noida for giving
me the opportunity to do an internship within the organization.

I would also like to thank all the people that worked along with me at PINE ACADEMY, Noida
with their patience and openness they created an enjoyable working environment.

It is indeed with a great sense of pleasure and immense sense of gratitude that I acknowledge
the help of these individuals.

I am highly indebted to Principal Dr. BS. CHAWLA, for the facilities provided to accomplish this
internship.

I would like to thank my Head of the Department DR. SEEMA CHAUHAN for her constructive
criticism throughout my internship.

I would like to thank Prof. Deepika Bairagi, College internship coordinator Department of
ET&T for her support and advices to get and complete internship in above said organization.

I am extremely great full to my department staff members and friends who helped me in
successful completion of this internship.

Osheen Gorakh

300702820025

IV
 DECLARATION

I, hereby declare that work, which is being presented in this report “ VLSI FOUNDATION
COURSE’’ in partial fulfillment of the requirement for the award of bachelor of technology in
Electronics and telecommunication Engineering and submitted to the Department of
Electronic and telecommunication , Government Engineering college Koni, Bilaspur, is an
authentic record of work carried within the premises of “PinE Training Academy’’, under the
supervision of “Vaibhav Mishra’’ Director of PinE Training Academy.

The contents of this report , in full or in parts, have not been submitted to any other Institute
or University for the award of any degree and are free from plagiarism

Signature of the student

Osheen Gorakh

300702820025

V
 ABSTRACT

Since we have keen interest in knowing new things especially related to the area of VLSI. We
selected a topic to the area of this field

As we want to enhance our career from the VLSI design which is also our subject, the research
made by us to complete this project will very helpful.

The main objective of our project on the topic “ VLSI FOUNDATION COURSE’’ is to study the
depth knowledge about the behavior and designing of different digital circuits, With the use
of XILINX software and ARTIX-7 FPGA board hardware, designing of practical electronic
devices has become much easier than before and easy to implement.

So, we would like to clearly mention that, our project purely involves the basic concepts of
RTL design and Verilog programming language using XILINX software.

VI
 INDEX

S No. Contents Page No.

1 Introduction 1–3

2 Analysis 4–6

3 Software Requirement
7–8
Specification

4 Technology 9 – 11

5 Coding 12 – 17

6 Screenshots 18 – 20

7 Conclusion 21

8 Bibliography 22

VII
 Learning Objectives/Internship Objectives

➢ Internships are generally thought of to be reserved for college students looking to gain
experience in a particular field. However, a wide array of people can benefit from
Training Internships in order to receive real world experience and develop their skills.

➢ An objective for this position should emphasize the skills you already possess in the
area and your interest in learning more

➢ Internships are utilized in a number of different career fields, including architecture,

engineering, healthcare, economics, advertising and many more.

➢ Some internship is used to allow individuals to perform scientific research while others
are specifically designed to allow people to gain first-hand experience working.

➢ Utilizing internships is a great way to build your resume and develop skills that can be
emphasized in your resume for future jobs. When you are applying for a Training
Internship, make sure to highlight any special skills or talents that can make you stand
apart from the rest of the applicants so that you have an improved chance of landing
the position.

VIII
 WEEKLY OVERVIEW OF INTERNSHIP ACTIVITIES
Date Day Name Of The Topic/Module Completed

13/7/23 Thursday Making all logic gate using Nand gate

1st Week

14/7/23 Friday Half,Full,4-bit adders/ substractor normal and using

Nand gate

17/7/23 Monday Half,Full,4-bit adders/ substractor schematic circuit

18/7/23 Tuesday Multiplexer, Making all gate and full adder using mux

19/7/23 Wednesday Introduction Verilog, Gate level modeling, half/full

adder and substractor ,mux coding

Date Day Name Of The Topic/Module Completed

20/7/23 Thursday Dataflow modeling,

Operators(Logical,Bitwise,reduction,etc)
2nd Week

21/7/23 Friday Operators (Concatenation, relational, arithmetic, etc.)

22/7/23 Saturday Basic introduction of design hardware to perform sign

calculator

24/7/23 Monday Sequential circuit schematic(SR,SR bug)

25/7/23 Tuesday SR bug free, JK master slave, DFF, TFF

26/7/23 Wednesday Counter(up,down,even,odd,ring,Johnson)

IX
 Date Day Name Of The Topic/Module Completed

27/7/23 Thursday Shift registers(SISO,SIPO,PIPO,PISO)

3rd Week

28/7/23 Friday Practice session

29/7/23 Saturday Behavioral modeling

31/7/23 Monday Combinational circuit coding

1/8/23 Tuesday Sequential circuit coding

2/8/23 Wednesday One second led blinking implementation in FPGA

board(Coding/hardware)

Date Day Name Of The Topic/Module Completed

3/8/23 Thursday One seven segment display (coding/hardware)

4th Week

4/8/23 Friday Two seven segment display (coding/hardware)

5/8/23 Saturday Loops (for,while,repeat,forever)

7/8/23 Monday Project 1(Single SSD Logics and Code)

8/8/23 Tuesday Project 1(Single SSD Implementation on FPGA)

9/8/23 Wednesday Project 1 (Working Demo and Submission)

X
 Date Day Name Of The Topic/Module Completed
5th Week

10/8/23 Thursday Project 2(Two SSD Logics and Code)

11/8/23 Friday Project 2(Two SSD Implementation on FPGA)

12/8/23 Saturday Project 2 (Working Demo and Submission)

XI
 1. INTRODUCTION

Our summer training immersed us in the intricate world of Very Large Scale Integration (VLSI),
offering a comprehensive exploration of its foundational principles. The heart of our module
lay in the meticulous study of hardware design, where we dissected various combinational
and sequential circuits. From the essential building blocks like adders, substractor, and
multiplexers to more complex elements such as encoders, decoders, flip-flops, latches,
timers, counters, and registers, we navigated the intricate landscape of logical circuits.

Our journey into Verilog, a powerful hardware description language, took us through three
distinct levels of modelling: Gate Level, Data Flow, and Behavioural. This multi-faceted
approach not only broadened our understanding but also empowered us to articulate and
implement designs with precision.

The hands-on aspect of our training was accentuated through our engagement with Xilinx
tools, providing us with practical insights into FPGA and CPLD architectures. The exploration
reached its pinnacle with an introduction to the Nexus A7, Artix 7 FPGA board—a
sophisticated platform that became the canvas for our practical applications.

A significant culmination of our efforts was manifested in a captivating project: the

programming of a seven-segment display. This project served as a testament to our ability to
translate theoretical knowledge into tangible applications. It encapsulated the essence of our
learning journey—bridging the gap between theory and practice, and honing our skills in real-
world problem-solving.

As a testament to our newfound knowledge, we undertook a captivating project involving the

programming of a seven-segment display. This project not only showcased our acquired skills
but also provided a tangible application of the theoretical concepts we absorbed throughout
the training.

Methodology

The methodology for the project involving the implementation of a two 7-Segment Display
using the Artix-7 FPGA initiates with the commencement of the FPGA design process. In the
initial phase, the Hardware Description Language (HDL) code is developed or loaded,
specifying the desired functionality for the two 7-segment displays. Subsequently, rigorous
testing is conducted through simulation to ensure the correctness and optimal performance
of the code. The planning phase follows, utilizing tools such as Xilinx Plan Ahead to
strategically allocate hardware resources on the Artix-7 FPGA, thereby optimizing utilization.

1
With the hardware plan established, the next step involves loading the code onto the FPGA
to evaluate its compatibility with the planned hardware resources. This critical testing phase
ensures alignment between the code logic and the FPGA architecture. The subsequent
connection with the Artix-7 FPGA board is established, enabling effective communication
between the development environment and the hardware.

Verification of the Artix-7 FPGA status becomes paramount in the following step, where
synthesis and implementation tools are employed to scrutinize the available resources and
confirm proper configuration. Following this verification, the current code instance is
terminated in preparation for the subsequent phase. The code is then re-loaded onto the
FPGA, and a meticulous verification process is conducted to ensure the correct operation of
the two 7-Segment Display in the real hardware environment.

The culmination of the project involves concluding the FPGA design process, signifying the
successful implementation and validation of the Two 7-Segment Display using the Artix-7
FPGA. This comprehensive methodology ensures a systematic approach to designing and
testing the display, guaranteeing its functionality and performance in real-world applications.

2
Flowchart START

INPUT THE VERILOG CODE

IN XILINX

VERIFY THE CODE

OPEN THE Plan Ahead

CONSTRAINTING ALL THE PINS

CONNECTING THE XILINX

WITH THE PlanAhead

CONNECTING THE PlanAhead

WITH FPGA BOARD

CHECKING THE STATUS

OF THE ARTIX-7

LOADING THE CODE IN ARTIX-7

PROCESSOR

VERIFICATION OF THE CODE ON

END
THE BOARD

3
 2. SYSTEM ANALYSIS

2.1 Requirement Analysis

Xilinx Software

Xilinx is a technology company that develops programmable logic devices (PLDs), including
field-programmable gate arrays (FPGAs), programmable logic controllers (PLCs), and software
development tools. Xilinx products are used in a wide range of applications, including
aerospace and defense, automotive, consumer electronics, industrial, and communications.

Xilinx System Requirements: The specific system requirements for Xilinx tools and devices
vary depending on the specific tool or device being used. However, there are some general
system requirements that apply to all Xilinx tools and devices. These requirements include:

Operating System: Xilinx tools and devices are supported on a variety of operating systems,
including Windows, Linux, and MacOS.

Processor: The processor speed and type will depend on the specific tool or device being
used. However, a general recommendation is to use a processor with a speed of 2.2 GHz or
higher.

Memory: The amount of memory required will depend on the specific tool or device being
used. However, a general recommendation is to have at least 2 GB of RAM.

Storage: The amount of storage space required will depend on the specific tool or device
being used. However, a general recommendation is to have at least 10 GB of free space.

Display: The display resolution should be 1024x768 or higher.

Xilinx System Analysis

Xilinx tools and devices are powerful tools that can be used to develop complex designs.
However, they can be complex to use and require a significant amount of time and effort to
learn. It is important to carefully consider the system requirements before purchasing Xilinx
tools or devices.

In addition to the general system requirements listed above, there are also specific system
requirements that must be met for certain Xilinx tools and devices. For example, some Xilinx
tools require a specific type of graphics card. It is important to consult the documentation for
the specific tool or device to determine the exact system requirements.

Xilinx tools and devices can be used to develop a wide range of applications. However, they
are not suitable for all applications. For example, Xilinx tools are not suitable for developing
applications that require high performance or low latency.

4
Overall, Xilinx tools and devices are powerful tools that can be used to develop complex
designs. However, they can be complex to use and require a significant amount of time and
effort to learn. It is important to carefully consider the system requirements before
purchasing Xilinx tools or devices.

PlanAhead Software

PlanAhead is a comprehensive FPGA design suite that provides a wide range of features for
Verilog analysis, synthesis, and implementation. It is developed by Xilinx, a leading FPGA
vendor, and is specifically designed for Xilinx FPGA devices.

Verilog Analysis

PlanAhead provides a number of features for analyzing Verilog designs, including:

Syntax checking: PlanAhead can check your Verilog code for syntax errors and ensure that it
adheres to the Verilog language standard.

Static timing analysis: PlanAhead can perform static timing analysis to identify potential
timing violations in your design. This can help you to ensure that your design meets the timing
requirements of your target FPGA device.

Design rule checking: PlanAhead can check your design for violations of Xilinx design rules.
This can help you to avoid problems during the synthesis and implementation stages of the
design flow.

Power analysis: PlanAhead can estimate the power consumption of your design. This can help
you to make informed decisions about the trade-offs between performance and power
consumption.

Verilog Synthesis

PlanAhead also provides a number of features for synthesizing Verilog designs, including:

Logic synthesis: PlanAhead can synthesize your Verilog code into a netlist of logic gates. This
netlist can then be used to implement your design on an FPGA device.

Technology mapping: PlanAhead can map your netlist to the specific logic gates and flip-flops
available on your target FPGA device.

Floorplanning: PlanAhead can generate a floorplan for your design that places the logic gates
and flip-flops on the FPGA device.

Routing: PlanAhead can route the connections between the logic gates and flip-flops on your
design.

5
Verilog Implementation

PlanAhead also provides a number of features for implementing Verilog designs, including:

Bitstream generation: PlanAhead can generate the bitstream that is used to program your
FPGA device.

Timing analysis: PlanAhead can perform post-synthesis timing analysis to ensure that your
design meets the timing requirements of your target FPGA device.

JTAG debugging: PlanAhead can be used to debug your design using the JTAG (Joint Test
Action Group) interface.

Overall, PlanAhead is a powerful tool that can be used to analyze, synthesize, and implement
Verilog designs for Xilinx FPGA devices. It is a comprehensive suite of tools that can be used
to create high-quality FPGA designs that meet your performance, power, and timing
requirements.

6
3. SOFTWARE REQUIREMENT AND SPECIFICATION

3.1 System configurations

The software requirement specification can produce at the culmination of the analysis task.
The function and performance allocated to software as part of system engineering are refined
by established a complete information description, a detailed functional description, a
representation of system behaviour, and indication of performance and design constrain,
appropriate validate criteria, and other information pertinent to requirements.
Software Requirements:
• Xilinx ISE :Developer(s) Xilinx

• Operating system: RHEL, SLED, FreeBSD, Microsoft Windows

• Size: 23.43 Gigabytes

• Type: EDA

• Website: xilinx.com/products/design-tools/ise-design-suite.html

Hardware Requirement:
• Hard Disk: 1TB.

• Ram: 4GB.

Xilinx ISE (Integrated Synthesis Environment) is a discontinued software tool from Xilinx for
synthesis and analysis of HDL designs, which primarily targets development of embedded
firmware for Xilinx FPGA and CPLD integrated circuit (IC) product families. It was succeeded
by Xilinx Vivado. Use of the last released edition from October 2013 continues for in-system
programming of legacy hardware designs containing older FPGAs and CPLDs otherwise
orphaned by the replacement design tool, Vivado Design Suite.

ISE enables the developer to synthesize ("compile") their designs, perform timing analysis,
examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the
target device with the programmer. Other components shipped with the Xilinx ISE include the
Embedded Development Kit (EDK), a Software Development Kit (SDK) and ChipScope Pro. The
Xilinx ISE is primarily used for circuit synthesis and design, while ISIM or the ModelSim logic
simulator is used for system-level testing.

As commonly practiced in the commercial electronic design automation sector, Xilinx ISE is
tightly-coupled to the architecture of Xilinx's own chips (the internals of which are highly
proprietary) and cannot be used with FPGA products from other vendors. Given the highly
proprietary nature of the Xilinx hardware product lines, it is rarely possible to use open source

7
alternatives to tooling provided directly from Xilinx, although as of 2020, some exploratory
attempts are being made.

Xilinx's patented algorithms for synthesis allow designs to run up to 30% faster than
competing programs, and allows greater logic density which reduces project time and costs.
Also, due to the increasing complexity of FPGA fabric, including memory blocks and I/O blocks,
more complex synthesis algorithms were developed that separate unrelated modules into
slices, reducing post-placement errors. IP Cores are offered by Xilinx and other third-party
vendors, to implement system-level functions such as digital signal processing (DSP), bus
interfaces, networking protocols, image processing, embedded processors, and peripherals.
Xilinx has been instrumental in shifting designs from ASIC-based implementation to FPGA-
based implementation.

8
 4. TECHNOLOGY

4.1 Verilog: - Verilog is a hardware description language (HDL) used in digital circuit design
and verification. It's widely used in the semiconductor and electronic design automation
industries to model electronic systems. Engineers use Verilog to describe the behavior and
structure of digital systems, including circuits, chips, and electronic systems.

Verilog in VLSI: - Verilog plays a critical role in VLSI (Very Large Scale Integration) design. It's
used for designing and verifying complex digital circuits that are integral to integrated circuits
(ICs) and electronic systems. In VLSI design, Verilog helps engineers describe the behavior and
structure of these circuits, facilitating tasks such as:

1. Behavioral Modeling: Describing the functionality and behavior of digital systems at higher
levels of abstraction.

2. RTL (Register Transfer Level) Design: Defining the transfer of data between registers and
the logic operations performed in a digital system.

3. Simulation: Verifying and testing the functionality of designs before actual fabrication,
which helps catch errors and optimize designs.

4. Synthesis: Converting the Verilog code into a netlist of logical gates, which can then be
further processed for physical implementation.

Overall, Verilog is a cornerstone in VLSI design, enabling engineers to conceptualize, simulate,

and implement intricate digital systems efficiently.

4.2. Xilinx: - Xilinx is a prominent company specializing in the development of programmable

logic devices (PLDs), particularly field-programmable gate arrays (FPGAs). In VLSI (Very Large
Scale Integration), Xilinx holds a significant position due to its FPGA technology and associated
tools.

Here's how Xilinx relates to VLSI:

1. FPGA Technology: Xilinx produces FPGAs, which are semiconductor devices that can be
programmed and configured after manufacturing. These FPGAs consist of configurable logic
blocks interconnected via programmable routing channels. They play a vital role in VLSI by
offering flexibility in designing and prototyping complex digital circuits.

2. Tools and Software: Xilinx provides a suite of software tools, including development
environments and synthesis tools like Vivado and ISE. These tools are crucial in the VLSI design
flow, aiding engineers in designing, verifying, synthesizing, and implementing their designs
onto Xilinx FPGAs.

9
3. Applications in VLSI: Engineers and designers use Xilinx FPGAs in various VLSI applications
such as prototyping, rapid development, hardware acceleration, and emulation. They allow
for faster time-to-market and the implementation of innovative designs due to their
reconfigurable nature.

In essence, Xilinx's FPGA technology and associated tools are integral to the VLSI design
process, offering flexibility, rapid prototyping capabilities, and a platform for implementing
complex digital systems.

4.3. FPGA (Artix 7):- The Artix-7 FPGA, part of Xilinx's FPGA family, is employed in various
aspects of VLSI (Very Large Scale Integration) design:

1. Prototyping and Validation: Artix-7 FPGAs are often used in the initial stages of VLSI design
for rapid prototyping and validation. Engineers can implement and test their designs on these
FPGAs before moving to more expensive and time-consuming fabrication processes.

2. Custom Logic Implementation: In VLSI, Artix-7 FPGAs offer the ability to implement custom
logic efficiently. Designers can create and optimize specific logic functions, enabling flexibility
and customization in the design process.

3. Accelerating Algorithms: These FPGAs are utilized for accelerating algorithms and
computationally intensive tasks. They offer parallel processing capabilities, making them
suitable for applications requiring high-speed processing, such as image and signal processing.

4. Verification and Testing: Artix-7 FPGAs are also utilized for verification and testing
purposes. Engineers can simulate and validate their designs in real-time on these FPGAs,
allowing for thorough testing before committing to silicon fabrication.

5. Embedded Systems: They are employed in embedded systems due to their re -

configurability, enabling them to adapt to changing requirements and implement multiple
functions on a single device.

Overall, Artix-7 FPGAs serve as versatile tools in VLSI design, enabling rapid prototyping,
customization, accelerated processing, thorough verification, and implementation in various
embedded systems.

4.4. PlanAhead: - PlanAhead was a tool provided by Xilinx as part of their software suite for
FPGA design, especially in the context of VLSI.

1. Design Planning and Analysis: PlanAhead offered capabilities for visualizing, planning, and
analyzing FPGA designs. Designers could explore and optimize their designs using floor-
planning, resource utilization, and timing analysis tools.

2. Hierarchical Design: It supported hierarchical design methodologies, enabling engineers to

manage complex designs by breaking them into manageable modules, facilitating easier
design and integration.
10
3. Timing Closure: PlanAhead helped in achieving timing closure, crucial in FPGA designs. It
allowed designers to analyze and address timing constraints to ensure that the design
operates correctly within the specified timing requirements.

4. Debugging and Optimization: The tool provided debugging features and optimization
suggestions, allowing designers to identify and rectify potential issues or bottlenecks in their
designs.

5. Integration with Other Tools: PlanAhead integrated with other Xilinx design tools like
Vivado, allowing a seamless flow from design exploration and planning to implementation
and verification stages.

However, as of my last update in January 2022, Xilinx has transitioned its tool chain, and
Vivado has become the primary tool for FPGA design, incorporating functionalities that were
previously offered by PlanAhead along with additional features.

11
 5. CODING
Two SSD Verilog Code

module TwoSSD1(AN,CA,clk,rst);

output reg [7:0]AN;

output reg [6:0]CA;

input clk,rst;

reg [26:0]countt;

reg clk_in=0;

reg [6:0]CA_1;

reg [6:0]CA_2;

reg [7:0]AN_1;

reg [7:0]AN_2;

reg [17:0]count;

reg clk_int=0;

reg [3:0] counter_1;

reg [3:0] counter_2;

//1 sec clock//

always@(posedge clk or posedge rst)

begin

if(rst)

countt<=27'd0;

else if(countt==50000000)

begin

clk_in<=~clk_in;

12
countt<=0;

end

else

countt<=countt+1'b1;

end

//counter_1//

always @(posedge clk_in or posedge rst)

begin

if(rst)

counter_1<=4'b0000;

else if(counter_1==4'b1001)

counter_1<=4'b0000;

else

counter_1<=counter_1+1;

end

//counter_2//

always @(posedge clk_in or posedge rst)

begin

if(rst==1 || (counter_1==9 & counter_2==9))

counter_2<=4'b0000;

else if(counter_1==4'b1001)

counter_2<=counter_2+1;

end

//SSD 1///////////////////////////////////////////////////

always @(posedge clk )

begin

AN_1<=8'b11111110;

13
if(counter_1 == 4'b0000)

CA_1 <=7'b0000001;

else if(counter_1 == 4'b0001)

CA_1 <=7'b1001111;

else if(counter_1 == 4'b0010)

CA_1 <=7'b0010010;

else if(counter_1 == 4'b0011)

CA_1 <=7'b0000110;

else if(counter_1 == 4'b0100)

CA_1 <=7'b1001100;

else if(counter_1 == 4'b0101)

CA_1 <=7'b0100100;

else if(counter_1 == 4'b0110)

CA_1 <=7'b0100000;

else if(counter_1 == 4'b0111)

CA_1 <=7'b0001111;

else if(counter_1 == 4'b1000)

CA_1 <=7'b0000000;

else if(counter_1 == 4'b1001)

CA_1 <=7'b0000100;

end

//SSD 2///////////////////////////////////////////////////

always @(posedge clk )

begin

AN_2<=8'b11111101;

if(counter_2 == 4'b0000)

CA_2 <=7'b0000001;

14
else if(counter_2 == 4'b0001)

CA_2 <=7'b1001111;

else if(counter_2 == 4'b0010)

CA_2 <=7'b0010010;

else if(counter_2 == 4'b0011)

CA_2 <=7'b0000110;

else if(counter_2 == 4'b0100)

CA_2 <=7'b1001100;

else if(counter_2 == 4'b0101)

CA_2 <=7'b0100100;

else if(counter_2 == 4'b0110)

CA_2 <=7'b0100000;

else if(counter_2 == 4'b0111)

CA_2 <=7'b0001111;

else if(counter_2 == 4'b1000)

CA_2 <=7'b0000000;

else if(counter_2 == 4'b1001)

CA_2 <=7'b0000100;

end

// 200 Hz Wala clock hai ye isse ssd referesh hoga 5 ms mai...

always @(posedge clk or posedge rst)

begin

if(rst)

count<=18'b0;

else if(count==250000)

begin

clk_int<=~clk_int;

15
count<=0;

end

else

count <=count +1'b1;

end

/////////Mux_Code///

//always@(posedge clk_int or negedge clk_int)

always @(clk_int or AN_1 or AN_2 or CA_1 or CA_2 )

begin

if(clk_int)

begin

AN<=AN_1;

CA<=CA_1;

end

else

begin

AN<=AN_2;

CA<=CA_2;

end

end

endmodule

//////////////////////////////////////////////////////////////////////

# PlanAhead Generated physical constraints

NET "AN[7]" LOC = U13;

NET "AN[6]" LOC = K2;
NET "AN[5]" LOC = T14;
NET "AN[4]" LOC = P14;
NET "AN[3]" LOC = J14;
NET "AN[2]" LOC = T9;
NET "AN[1]" LOC = J18;
NET "AN[0]" LOC = J17;

16
# PlanAhead Generated IO constraints

NET "AN[7]" IOSTANDARD = LVCMOS33;

NET "AN[6]" IOSTANDARD = LVCMOS33;
NET "AN[5]" IOSTANDARD = LVCMOS33;
NET "AN[4]" IOSTANDARD = LVCMOS33;
NET "AN[3]" IOSTANDARD = LVCMOS33;
NET "AN[2]" IOSTANDARD = LVCMOS33;
NET "AN[1]" IOSTANDARD = LVCMOS33;

NET "AN[0]" IOSTANDARD = LVCMOS33;

# PlanAhead Generated physical constraints

NET "CA[6]" LOC = L18;

NET "CA[5]" LOC = T11;
NET "CA[4]" LOC = P15;
NET "CA[3]" LOC = K13;
NET "CA[2]" LOC = K16;
NET "CA[1]" LOC = R10;
NET "CA[0]" LOC = T10;

# PlanAhead Generated IO constraints

NET "CA[6]" IOSTANDARD = LVCMOS33;

NET "CA[5]" IOSTANDARD = LVCMOS33;
NET "CA[4]" IOSTANDARD = LVCMOS33;
NET "CA[3]" IOSTANDARD = LVCMOS33;
NET "CA[2]" IOSTANDARD = LVCMOS33;

NET "CA[1]" IOSTANDARD = LVCMOS33;

NET "CA[0]" IOSTANDARD = LVCMOS33;

# PlanAhead Generated physical constraints

NET "clk" LOC = E3;

NET "rst" LOC = T8;

# PlanAhead Generated IO constraints

NET "clk" IOSTANDARD = LVCMOS33;

NET "rst" IOSTANDARD = LVCMOS33;

17
 6. SCREENSHOTS

TWO SSDs with ARTIX7:

18
19
20
 7. CONCLUSION
VLSI, which stands for Very Large Scale Integration, is a process used in the design and
fabrication of integrated circuits (ICs), which are electronic circuits that are made up of a large
number of transistors and other components that are integrated into a single chip. The
technology allows for the creation of highly complex and compact ICs that can be used in a
wide range of applications, from consumer electronics and computers to communication
systems and medical devices.

VLSI technology is ubiquitous. In the telecommunications industry, VLSI engineers are

responsible for designing and developing advanced chips that power smartphones and enable
seamless communication. In the automotive sector, VLSI engineers contribute to the creation
of innovative solutions for autonomous driving, which improve safety and efficiency on the
roads. Moreover, VLSI engineers play a critical role in the development of consumer
electronics, ensuring that devices are smaller, faster, and more energy-efficient. With VLSI
engineering at the forefront of technological advancements, it is shaping the world we live in.

One of the key advantages of this technology is its ability to pack a large number of transistors
and other components onto a single chip, which allows for the creation of highly complex and
powerful ICs. This makes it possible to create ICs that can perform a wide range of functions,
from simple logical operations to complex algorithms. It also allows for the creation of ICs
with high levels of performance, power efficiency, and reliability, which are essential for many
applications.

The future of VLSI technology looks promising, with new innovations such as artificial
intelligence (AI) and the Internet of Things (IoT) driving the demand for more powerful and
energy-efficient chips. The development of 5G technology is also expected to drive the
demand for VLSI technology in the coming years. Scope of design and verification: The design
and verification of VLSI chips are critical processes that ensure that the chip meets the desired
specifications and functions correctly. The scope of design and verification includes various
stages, such as design entry, simulation, synthesis, physical design, and verification. As the
complexity of VLSI chips continues to increase, the demand for skilled engineers with
expertise in VLSI design and verification is expected to grow in the future.

VLSI is a critical technology that is used in the design and fabrication of modern ICs. This
technology allows for the integration of a large number of transistors and other components
onto a single chip, which allows for the creation of highly complex and powerful ICs. It also
requires coding in order to create the detailed designs that are needed for modern ICs, and
VLSI designers use a wide range of programming languages and tools to create and verify their
designs.

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 8. BIBLIOGRAPHY

The following websites are referred during the analysis and execution phase of
the project

1. https://resources.pcb.cadence.com/blog/2020-vlsi-technology-its-history-
and-uses-in-modern-technology. – Importance and meaning of VLSI.

2. https://skill-lync.com/blogs/circuit-simulation-and-analysis-in-vlsi-design. –
Tools and their requirements for the VLSI Testing.

3. https://archive.nptel.ac.in/courses/106/105/106105165/. – Introduction
Verilog modules and coding Environment.

4. https://www.xilinx.com/support/download.html. – Xilinx Understanding to

use and about its environment.

5. https://www.xilinx.com/products/design-tools/planahead.html. –PlanAhead
details with requirements and about its usage.

6. https://xilinx-planahead.software.informer.com/. – PlanAhead Download

and installing in our System.

7. https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet. –Artix7 FPGA

Board datasheets to study about Artix 7.

8. https://www.scribd.com/document/348384590/Plan-Ahead-User-Guide. –
PlanAhead Setup with Artix7 and configuration needed to establish
communication PlanAhead and Artix7.

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