Pre-Assembly Testing of Interconnects in Embedded

Multi-Die Interconnect Bridge (EMIB) Dies

Sudipta Mondal and Krishnendu Chakrabarty
Department of Electrical and Computer Engineering
Duke University, Durham, NC 27708, USA
Abstract—The embedded multi-die interconnect bridge applying test patterns and observing test responses. In this
(EMIB) is an advanced packaging technology for 2.5D integra- way, direct probing is not required and test cost is reduced.
tion. This paper presents a bridge test architecture based on the In an EMIB chip reported in the literature [6], one side of
proposed IEEE Std. P1838. The proposed test method enables
access to interconnects at a pre-assembly stage by pairing the the EMIB die is connected to a transceiver die and other side is
interconnects using metal shorts and probing on coarse-pitch C4 connected to an FPGA. If testing is performed with both sides
bumps. It can efficiently detect resistive-open and resistive-short of bridge attached to functional dies, then in case of a faulty
defects in the bridge interconnects and micro-bumps. Simulation bridge, we will need to discard both the dies. As the processing
results are presented to evaluate the range of defects that can be cost of an FPGA is higher than that of a transceiver die [6], it
detected by the proposed method.
is more economical to perform the test with the transceiver die
I. I NTRODUCTION and attach the FPGA later. On the other hand, direct probing
of the bridge die with no functional die is difficult due to
Three-dimensional (3D) ICs use through-silicon-vias the localized high density of interconnects. Thus, this paper is
(TSVs) to stack multiple dies [1]. Even though 3D integration aimed at testing of the EMIB with one functional die attached
overcomes the problems of large footprint and long global to it. This testing step can ensure the screening of defective
interconnects, challenges related to cost, yield, and testing are EMIB dies, whereby good functional dies do not have to be
yet to be adequately addressed. These problems have paved discarded after assembly due to a defective EMIB. While pre-
the way for the adoption of interposer-based 2.5-D ICs [2]. assembly EMIB testing without any functional die and post-
However, interposers also introduce design and test chal- assembly testing where functional dies are connected to both
lenges. An interposer must be large in size to accommodate sides of the EMIB are also desirable, we leave this problem
the dies on it. In addition, the large number of TSVs in 2.5D for future work.
ICs may result in reduced yield, degraded signal integrity, and The IEEE 1149.1 test-access port (TAP) has been used
IR drop in power-delivery nets [3]. to test interposer interconnects [7], [8]. In these methods,
Embedded multi-die interconnect bridge ICs (EMIB ICs) of- two dies are used to launch tests and capture responses,
fer several advantages over interposers, e.g., higher bandwidth, respectively. We have to, however, implement a new test
flexibility of die placement, and increased scalability [3]. In architecture in which the same functional die is used to apply
this technology, the interposer is replaced by a thin silicon test patterns and capture test responses. The key difference
chip (also called a bridge), with multiple routing layers that between interposers and EMIBs is that interposers use vertical
eliminate the need for TSVs [4]. Intel recently announced and horizontal interconnects for inter-die communication [8].
the 8th-generation Core H-Series chip with integrated AMD The vertical interconnects are connected to C4 bumps by
Radeon graphics [5]. This H-Series CPU uses EMIB technol- TSVs. Hence, these interconnects can be utilized to apply
ogy to interconnect the various Intel and AMD components, test patterns and observe test responses. EMIB-based 2.5D
as well as high-bandwidth on-chip memory. Resistive opens ICs do not have TSVs that can be leveraged for testing and
and shorts can, however, occur in the bridge interconnect this imposes a new challenge in EMIB interconnect testing.
due to incomplete metal fill, misalignment of micro-bumps, The IEEE 1149.1 boundary scan architecture is not suitable
and deformation. These defects lead to excessive interconnect for this purpose as it provides only one test data input pin
delay and anomalous electrical characteristics. In [4], a test (TDI) and one test data output pin (TDO). Hence, the TDO
vehicle was proposed to evaluate the signal integrity of EMIB pin of another functional die must be used to shift out the
interconnects. RF probing was performed to measure the S- test responses from interconnect test. On the other hand, the
parameters of the interconnects. However, direct RF probing proposed IEEE Std. P1838 [9] facilitates TAPs, (primary and
of micro-bumps is expensive using standard test equipment secondary) on a functional die, which can be concatenated to
in high-volume manufacturing. Moreover, the test-application form a single test path. Thus, we present a test technique that
time for RF probing can be prohibitively high and it is difficult is compatible with P1838.
to evaluate test quality for shorts and opens. Since EMIB-based 2.5D IC prototypes have been reported
We propose a new test method for detecting opens and in industry [4], [6], [3], it is likely that test methods have also
shorts in EMIB interconnects. We perform testing after a logic been developed for these prototypes. However, these methods
die is attached to the bridge. This die is utilized for both are proprietary and not fully disclosed in the literature. This

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c EDAA 373
 Secondary
Interface 2
Interface 2
Interface 1
paper describes a test solution based on open standards that

Secondary
Secondary
Interface 1

Interface
Interface
Primary
Primary
Primary
can be leveraged and extended, and can facilitate collaborative
advances for the next generation of EMIB-based 2.5D ICs.
The rest of the paper is organized as follows. Section II Fine-pitch
presents an overview of EMIB technology. The proposed test micro-bumps
Coarse-pitch
method and test architecture are presented in Section III. micro-bumps
Section IV presents simulation results. Finally, Section VI
C4 bumps
concludes the paper. (a) (b)
II. OVERVIEW OF EMIB TECHNOLOGY Fig. 1: P1838-compliant test interfaces for: (a) Interposer-based IC;
The bridge substrate is composed of glass, ceramic, or (b) EMIB die.
Secondary TAP
semiconductor material. Electrical routing features (through-
TRST_S
hole-vias, traces, and pads) through the substrate are first TCK_S TMS_S TDI_S
created. A sacrificial layer is added on the surface of the TD0_S
m2
1
substrate. Openings are formed in the sacrificial layer to m1

facilitate the connections between interconnects and micro- 2 3

bumps. After the formation of interconnect pads and traces,

Internal Scan Chains
the sacrificial layer is etched away [10]. The organic package
substrate is formed with a cavity to attach the bridge fabricated Die Wrapper Register

in the previous step. After the bridge is attached to the package Bypass Register
FPP Config Register
cavity, the final dielectric layers are formed, and coarse-pitch TAP Config Register
and fine-pitch vias are etched for power-delivery nets and inter- Instruction Register
die interconnects, respectively. The bridge is then embedded TAP Controller 1
TDI_P 3 2
into the cavity using an adhesive [4].
TRSTN TMS TCK
There are two types of micro-bumps in an EMIB: 1) fine- TDO_P
pitch micro-bumps; 2) coarse-pitch micro-bumps. Fine-pitch Primary TAP
micro-bumps are used to connect dies to the interconnects. Fig. 2: Primary and secondary TAPs.
They enable localized interconnects and high density. Coarse-
input ports and one output port. The ports at the primary
pitch micro-bumps provide power and ground connections to
interface are labeled as TDI P (Test Data Input), TCK P
functional dies. One end of a coarse-pitch micro-bump is
(Test Clock), TMS P (Test Mode Select), TRSTN P (Test
connected to a functional die, and the other end is connected
Reset Not), and TDO P (Test Data Output). The ports at the
to the back of the package substrate through a C4 bump. In-
secondary interface are denoted as TDI S (Test Data Input),
terconnects are formed between coarse-pitch micro-bumps and
TCK S (Test Clock), TMS S (Test Mode Select), TRSTN S
the C4 bumps to provide power and ground connections [10].
(Test Reset Not) and TDO S (Test Data Output). The 16-state
III. P ROPOSED T EST A RCHITECTURE finite-state machine of 1149.1 is utilized in the primary TAP
controller. It includes:
The proposed test-architecture design adds controllability
and observability to the bridge interconnects through the 1) Instruction Register: This register selects the test mode for
package C4 bumps. A new die-wrapper cell is added to the the die. It also selects the test data register (TDR) that is
inputs and outputs of the functional die. This design is based connected to the serial path of the scan chain.
on minimal changes to P1838. 2) Configuration Register: It selects the secondary interface
to be included in the serial scan path of the die. Multiple
A. Overview of P1838 secondary interfaces can be activated simultaneously.
P1838 envisions a primary and a secondary test interface 3) Bypass Register: It is used to bypass the serial scan path.
inserted on the bottom side of each functional die. These 4) Die Wrapper Register (DWR): This register is used dur-
interfaces are placed in such a way that the secondary interface ing EXTEST (testing of interconnect between dies) and
of a die is connected to the primary interface of another die INTEST (testing of die-internal logic) modes.
as shown in Fig. 1(a).
In the pre-assembly stage, there is only one functional die on B. Details of the Proposed Test Method
the EMIB. Hence, one primary and one secondary interface are In order to overcome the difficulty of direct probing of
necessary for testing. The primary interface can be placed on micro-bumps, dummy metal interconnects were placed in [11]
the bottom side of the die where the coarse-pitch micro-bumps to create test loops between pairs of micro-bumps. We simi-
are located. The secondary interface can be placed at the larly propose the use of dummy metal to create interconnect
location of the fine-pitch micro-bumps, as shown in Fig. 1(b). pairs. After the bridge substrate is embedded in the package
Both the primary and secondary interfaces are equipped substrate, a logic die is connected to one side of the EMIB
with test access ports (TAPs); these are referred to as primary and dummy metal wires are placed on the interconnect traces
and secondary TAPs, respectively (Fig. 2). Each TAP has four that are located on the other side of the EMIB. The dummy

374 Design, Automation And Test in Europe (DATE 2018)

 Receiver Transmitter CT0
DWR Cell DWR Cell
1
CFI
Dummy metal CFO
1 0

CTI 0 SC
Interconnect traces Update
Mode Control
Shift Enable
Fig. 4: A dedicated DWR cell [9].
T
Test data flow CT0
Test response output CFI 1

TEST_ENABLE_S1
CFO
1 0
Test pattern input CTI 0 SC
Update
Fig. 3: Test architecture for bridge interconnects.
FP 1

metal can be subsequently removed using specific processing Shift DR 0

steps as in [12]. Fig. 5: Design of the proposed transmitter DWR cell.

Suppose there are N interconnects in the bridge denoted CT0

by 1, 2,...., N . First, we assume that N is even. We divide CFI

the interconnects into two groups. The first group includes

TEST_ENABLE_S2
1
interconnects 1 to N /2 and the second group includes N /2+1 0 1
CFO
and the interconnects up to N . The group of interconnects TP
1 0
0
CTI SC Update
that are closer to the coarse-pitch micro-bumps are called
TP
receiver interconnects, and the interconnects that are on the FP
1

other side of the bridge are called transmitter interconnects; Shift DR 0

see Fig. 3. The micro-bumps attached to the transmitter and Fig. 6: Design of the proposed receiver DWR cell.
receiver interconnects are called the transmitter and receiver FP signal is used to shift in the test patterns. In the receiver
micro-bumps, respectively. DWR cell, we add two multiplexers and a NAND gate. One
Next, we short (using dummy metal) one transmitter and of the multiplexers is added to the feedback path from CFO
one receiver interconnect to make a pair. The pairing of the to CTI. This feedback path is important in the proposed test
interconnects is done in the following manner. Interconnect 1 method to ensure that receiver cells can receive test data from
is paired with interconnect N /2+1, interconnect 2 with inter- transmitter cells. As the boundary scan cells used in IEEE
connect N /2+2, and so on. The last pair is made by shorting 1149.1 do not have a feedback connection from the parallel
interconnect N /2 with interconnect N . On the other hand, if N output pin (CFO) to the serial input pin (CTI), they are not
is odd, the first group includes interconnects 1 to (N -1)/2 and suitable for the proposed method.
the second group includes (N +1)/2+1 and the interconnects We insert one primary test interface and two secondary test
up to N . In this case, the first pair consists of interconnect interfaces on the bottom-side of a die. The primary interface
1 and interconnect (N +1)/2+1, the second interconnect pair is connected to the bottom side of the die that has the coarse-
consists of interconnect 1 and interconnect (N +1)/2+2, and pitch micro-bumps. The test data pins of the primary interface
so on. The last pair is made by shorting interconnect (N -1)/2 are connected to two coarse-pitch micro-bumps.
with interconnect N . If N is odd, interconnect (N +1)/2 cannot The secondary interfaces are inserted on the side of the die
be included in any pair. After testing all of the remaining that has the transmitter and receiver fine-pitch micro-bumps.
interconnects, one of the dummy metal shorts can be removed The transmitter and receiver test interfaces are denoted as
and interconnect (N +1)/2 can be paired with the disconnected Secondary Interfaces SI 1 and SI 2, respectively. The test
interconnect of the second group. data input and output pins of the secondary interface at the
A dedicated DWR cell is shown in Fig. 4. DWR cells are transmitter side are TD1 S1 and TDO S1, respectively. The
attached to transmitter and receiver micro-bumps; these are test data input and output pins of the secondary interface
referred to as transmitter and receiver DWR cells, respectively. at the receiver side are TD1 S2 and TDO S2, respectively.
In the proposed method, we do not consider connecting a Instructions, configuration data and test data are fed to the
transmitter and receiver DWR cell at every interconnect be- primary TAP controller through TDI P. When the test mode
cause this solution is associated with increased area overheard. is initiated, the value in the configuration register selects
The transmitter DWR cells are used to shift in and apply test the secondary test interface (transmitter or receiver) to be
patterns. The receiver DWR cells capture and shift out test included in the serial scan path of the die. The TCK P pin
responses. The transmitter and receiver DWR cells (Fig. 5-6) is connected to TCK S1 and TCK S2. Similarly, TRSTN P
are different due to their difference in functionality. Several is connected to TRSTN S1 and TRSTN S2. The data at the
modifications are made to the P1838-complaint DWR cells in primary interface TMS P is fed in to TMS S1 and TMS S2
order to implement the transmitter and receiver DWR cells. through multiplexers. For instance, if TAP S1 is selected by
A multiplexer is added to the transmitter DWR cell. The the configuration register in the TDI P and TDO P path,
TEST ENABLE S1 signal determines whether the transmitter then TMS S1 will receive the values in TMS P. When it
DWR cell operates in functional mode or test mode, and the is deselected, TMS S1 receives a user-programmable value.

Design, Automation And Test in Europe (DATE 2018) 375

 Table I: Control signal values in the newly defined test modes.
Instruction SHIFTIN SHIFTOUT
Internal Scan Chains TP 1 0
TP FP 0 1
Die Wrapper
pp Register
g FP TEST ENABLE P 1 1

TDO_P
Bypass
yp Register
g
TEST_ENABLE_P 1
TAP Config Register V(CLK)
0.5
0
Update_DR

Shift_DR
0 10

Voltage (V)
TDI_P 5 15 20 25 30

Decoder 1
V(N_1)
0.5 5
TMS_P 0
TCK_P Update_IR 0 15 20 25
Instruction 5 10 30
TRSTN_P P1838 TAP Controller
Shift_IR Register
1
0.5 22 V(N_OUT)
0
0 5 10 15 20 25 30
Fig. 7: Design of the primary TAP controller. Time (ns)
Fig. 8: Results obtained by simulating a resistive-open defect.
Similarly, TEST ENABLE P is fed into TEST ENABLE S1
IV. S IMULATION R ESULTS
and TEST ENABLE S2 to select between the functional
mode and the test mode at the secondary TAPs. In this section, we present HSPICE and ModelSim simula-
tion results, and, DfT hardware overhead. In a representative
In order to implement the proposed test method two private
EMIB IC, the interconnects are 0.8 μm in diameter, with a
instructions (SHIFTIN and SHIFTOUT) need to be inserted, in
pitch of 0.8 μm and thickness of 0.6 μm [13]. Based on this
addition to the public instructions in IEEE P1838 (BYPASS,
data, we calculated the resistance and capacitance of the bridge
IDCODE, and EXTEST). In SHIFTIN, the configuration reg-
interconnect to be 3.5 Ω per 100 μm and 7.73 fF per 100 μm,
ister value is set to 1, and the secondary interface at the
respectively. The transistors were modeled using a low-power
transmitter side is included in the serial scan path of the
45 nm technology [14]. Transmission-gate transistor widths
die. The die-wrapper register in connected between TDI S1
were set to 360 nm (270 nm) for PMOS (NMOS). Inverters
and TDO S1, and test patterns are shifted into the transmitter
were composed of 270 nm (180 nm) wide NMOS (PMOS)
DWR cells. The test patterns are applied to the interconnects
devices. The supply voltage was set to 1 V.
and captured by the receiver DWR cells. When SHIFTOUT
is asserted, the configuration register value is set to 0, and the A. Open-defect detection
secondary interface at the receiver side is included in the TDI-
For the analysis of resistive-open defects, a 2000 μm-long
TDO path of the die. The die-wrapper register is connected
interconnect is used to connect a transmitter and a receiver
between TDI S1 and TDO S1, and test responses captured in
micro-bump. A high resistance (60 kΩ) is inserted in the
the receiver DWR cells are shifted out through TDO P.
interconnect to model a resistive-open defect. The test patterns
The primary TAP controller remains in the Run-Test/Idle for the detection of an open defect are shifted in at a frequency
controller state for the duration required for the completion of 200 MHz and six clock periods are shown in Fig. 8. During
of the execution of SHIFTIN. The scan chain between TDI S the first two clock cycles, test patterns are shifted into the
and TDO S is utilized to shift in a test pattern into the DWR transmitter DWR cells. Test responses are captured by the
cells. Similarly, when the SHIFTOUT mode is selected, the receiver DWR cells in the third clock cycle. The remaining
captured test response in the scan chain between TDI S and three clock cycles are used to shift out the test response from
TDO S is shifted out through TDO P. the receiver cells through TDO P. As shown in Fig. 8, a test
The block diagram of the primary TAP controller is shown sequence of 1010 is shifted into the transmitter cells (V(N 1)),
in Fig. 7. It has four inputs TCK P, TMS P, TRST P and but due to the delay introduced by the resistive-open defect,
TDI P. The signal TEST ENABLE P is internally generated the receiver cell cannot capture the correct value (V(N OUT)).
from the decoder, and set to 1 when the opcode output As a result, the incorrect value 0001 is shifted out.
of the instruction register matches SHIFTIN or SHIFTOUT. Next, we determine the smallest resistive-open defect that
Otherwise, it is set to 0. can be detected. Fig. 9(a) shows the smallest detectable
Several outputs are generated by the primary TAP con- resistance when the shift frequency is varied from 50 MHz
troller. The Shift IR and Update IR signals are fed into the to 200 MHz. As the frequency decreases, the value of the
instruction register during the IR cycle. The Shift DR and smallest detectable resistance increases. This happens because
Update DR signals are generated during the DR cycle and the capacitance of the interconnect has sufficient time to charge
fed to the DWR register and the bypass register. The modified and discharge as the shift frequency is decreased. At a shift
TAP controller generates the additional outputs TP, FP, and frequency of 50 MHz (200 MHz), the smallest detectable open
TEST ENABLE P to implement the proposed test method. resistance is 90 kΩ (16 kΩ).
These signals are used to select between the functional and In addition to the shift frequency, the location of the
the test mode of the TAP. The values of these output signals open defect also affects detectability. We modeled a long
during different modes of operation are listed in Table I. interconnect using 2, 5, 10, and 20 RC segments. It can be seen

376 Design, Automation And Test in Europe (DATE 2018)

 Table II: Distance between open defects affects detectability.
Minimum Detectable Open Resistance
120 60
Distance between R1 and R2 Smallest detectable value of R2
100 50
500 μm 85 kΩ
40
80
1000 μm 166 kΩ
60 30 1500 μm 8 MΩ
40 20
Table III: Largest detectable short resistance for different combina-
20 10 tions of inputs.
0 0
0 500 1000 1500 2000
Interconnect 1 Interconnect 2 Interconnect 3 Rshort
(kȍ)

0 50 100 150 200 250

Shift Frequency of Test Input (MHz) Defect Location (*m
0 0 1 5 kΩ
(a) (b) 0 1 0 7 kΩ
0 1 1 450 Ω
Fig. 9: Detectability of open defect: (a) Minimum detectable resis-
1 0 0 4.5 kΩ
tance versus shift frequency of the test input; (b) Minimum detectable
1 0 1 1 kΩ
resistance versus the defect location.
1 1 0 450 Ω
R1 R2 R3 R1 Ropen R2 R3 R1 R2 Ropen R3

R1, the smallest detectable value of R2 increases rapidly. For

(a) (b) (c) a distance of 1500 μm, the smallest detectable value of R2 is
Fig. 10: Elmore delay model for an EMIB interconnect: (a) A high as 8 MΩ. This happens because when R2 is moved further
fault-free interconnect with three RC segments; (b) A resistive-open away from the transmitting end, the capacitance associated
between Segment 1 and Segment 2; (c) A resistive-open defect with it decrease.
between Segment 2 and Segment 3.
B. Detection of short defects
from Fig. 9(b) that the smallest detectable resistance increases
as the open is moved closer to the end of the interconnect. Fig. 12 shows simulation results for the detection of bridge
This is because the capacitance associated with the open is defects. Two interconnects are shorted by a resistance of 1 Ω.
reduced when the defect is closer to the end. The signal values applied to the interconnects are opposite to
This simulation results can be explained using the Elmore each other. Hence, the fault-free logic values of V(O1) and
delay model. Let us assume that the interconnect under con- V(O2) are opposite to each other. However, due to the short,
sideration is modeled using three RC segments as shown in the logic values on the interconnects are incorrect.
Fig. 10. According to the Elmore delay model, the RC delay Next, we analyze the largest detectable short resistance. As
is R1 (C1 +C2 +C3 )+R2 (C2 +C3 )+R3 C3 . Now, we insert a the value of the largest detectable short resistance decreases,
resistive-open defect (Ropen ) between Segment 1 and Segment the effectiveness of the detection method increases. We use a
2. In this case, the delay of the interconnect is calculated to be lumped model for analyzing shorts. Fig. 12 shows the results
R1 (C1 +C2 +C3 )+R2 (C2 +C3 )+Ropen (C2 +C3 )+R3 C3 , and for the detection of shorts. The voltage level of V(O1) at 9
the additional RC delay due to the defect is Ropen (C2 + C3 ). ns is analyzed when the short resistance is increased from 0
Next, we place the open-defect resistance between Segment 2 to 1.8 kΩ with a step size of 100 Ω. The voltage switches to
and Segment 3. In this case, the RC delay of the interconnect 1.1 V when the bridge resistance is 1.8 kΩ. Thus, the largest
is R1 (C1 + C2 + C3 ) + R2 (C2 + C3 ) + Ropen C3 + R3 C3 and detectable short resistance is 1.8 kΩ. As the shift frequency
the additional RC delay due to the defect is Ropen C3 . Hence, and the location of the short are varied, the largest detectable
it is evident that as the defect is shifted towards the end of the short resistance remains 1.8 kΩ. This is because the delay on
interconnect, the RC delay decreases because the capacitance the shorted path remains negligible even when different shift
in the “RC” product term decreases. frequencies and short locations are taken into account.
Next, we consider the occurrence of multiple open defects Next, we consider shorts that involve more than two inter-
at different locations of an interconnect. For instance, we insert connects. For instance, we consider three interconnects shorted
open defects in two different locations; the first at a distance of by two resistances. In order to determine the largest detectable
500 μm from the transmitting end and another 1500 μm away short defect, we consider all possible combinations of signals
from the transmitting end. Without loss of generality, we use a on the three interconnects. The signal combinations and the
shift frequency of 200 MHz for analysis. We fix the first open corresponding value of the largest detectable short resistance
defect at 500 μm (R1) with a magnitude of 10 kΩ and perform are listed in Table III. We use ‘1’ to denote a high signal level
HSPICE simulation to determine the smallest detectable open and ‘0’ to denote a low signal level. The largest detectable
defect at 1500 μm (R2). At a shift frequency of 200 MHz, R2 short resistance for each combination is indicated as Rshort
is 166 kΩ. As we decrease the shift frequency to 100 MHz, in Table III. We exclude the ‘111’ and ‘000’ combinations as
R2 increases from 166 kΩ to 200 kΩ. they do not lead to any observable error.
The smallest detectable value of R2 also depends on the Table III shows that the largest detectable short resistance
relative distance between R1 and R2. To analyze this relation- for input combinations (001, 010, and 100) is higher than that
ship, we fixed the location of R1 and the shift frequency to 200 for the input combinations (001, 101, 110). We next consider
MHz as before, and varied the location of R2. The smallest two interconnects as aggressors and the third interconnect as
detectable value of R2 with varying distance between R1 and the victim. When aggressors are low and victim interconnect is
R2 is given in Table II. As R2 is moved further away from high (001, 010, and 100), the largest detectable short resistance

Design, Automation And Test in Europe (DATE 2018) 377

 controller. The transmitter DWR cell and receiver DWR cell
overheads are 10.9% and 18.2%, respectively.
Table IV: (a) Synthesis results; (b) Area overhead.
Cell name Layout area Type of Overhead Overhead
Standard DWR cell 14.09 μm2 Transmitter DWR
Transmitter DWR cell 15.69 μm2 10.9%
cell overhead
2
Receiver DWR cell 16.85 μm Receiver DWR cell
18.2%
Standard primary overhead
490.34 μm2
TAP controller DWR cell (averaged) 14.55%
Proposed primary Proposed primary
497.02 μm2 1.4%
TAP controller TAP controller overhead
(a) (b)
V. C ONCLUSION
We have presented a DfT solution that enables pre-assembly
Fig. 12: Simulation results for short defects.
testing of interconnects in an EMIB die. The proposed solution
is larger. On the other hand, when aggressors are high and can detect open and short defects in the EMIB interconnects
the victim is low (001, 101, 110), the largest detectable short along with any defects that may occur in micro-bumps. We
resistance is small. have presented HSPICE and ModelSim simulation results to
demonstrate the effectiveness of the proposed approach.
C. DfT Architecture Simulation
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calculated with respect to the P1838-compliant primary TAP edu, 2002.

 
 
  

Configuration register ‘0000’
 
 
  



Instruction ‘0000’

Fig. 11: Results for DfT architecture simulation.

378 Design, Automation And Test in Europe (DATE 2018)