Problem 22

A report on
Design of a Two Stage Single-Ended Output

Opamp
Problem No.- 22
Krish Ambre 2017B4A80869P

Ashish 2017B5A30686P
Keshav Tawari 2017B3A30511P
Puney Chawla 2018A3PS0385P
Submitted in partial fulfillment of the course

EEE F313/ INSTR F313 – Analog & Digital VLSI Design
Problem Statement
Design a two-stage single-ended output OPAMP (Telescopic + gain stage) for the following specification
a) Analysis of all equations of your design, with a systematic derivation of all transistors’ W/L ratios and
spectre simulation of circuit for the following specifications.
i) Gain ≥ 80 dB
ii) Power dissipation ≤ .2mW
iii) Output swing ≥ 2V
b) Show a biasing circuitry to bias all the voltages in your design (except the input).
c) Use STB analysis to measure the closed loop gain and phase margin.
d) Calculate and plot the following parameters for your OPAMP: DC gain, bode plot for AC gain and
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power
consumption, and input and output offset voltage.
Required Specifications and Restrictions

Parameters Specifications
Technology TSMC 180nm technology
VDD 2.5V
CL ≤1 pF
Current mirror ratios ≤ 20
Reference Current Single ideal current source of arbitrary value, with the
positive node tied to VDD or negative node tied to ground
Power Dissipation ≤ .2mW
Output swing ≥ 2V
Gain ≥ 80 dB
Schematic Diagram
Transistor sizes
Transistor Length(µm) Width(µm)

M1, M2 0.35 24.89
M3, M4 0.35 5
M5 0.35 10.13
M6, M7 0.35 8.68
M8, M9 1.48 18.99
M10, M11 0.35 8
M12, M13 0.35 13
M14, M15 1.48 96.1
M16, M17 0.35 1.92
Biasing Circuit
Results
From the bode plot we get the following results
Gain ~ 87dB
Phase Margin~75°
3dB frequency~5kHz
CMRR~100dB
Output Swing
By performing transient analysis, we can get output swing
Output swing = 2.051V
ICMR
By performing DC sweep on input voltage from 0 to Vdd, we can get the ICMR
ICMR = 0.4 to 2.2

Slew Rate
Slew rate is defined as the maximum rate of change of an op amp's output voltage and is given units of
volts per microsecond. Slew rate is measured by applying a large signal step, such as 1V, to the input of
the op amp, and measuring the rate of change from 10% to 90% of the output signal's amplitude.
𝑑𝑉𝑜𝑢𝑡
Slew Rate = ( 𝑑𝑡
)
𝑚𝑎𝑥
Slew Rate is calculated as an average of positive and negative slew rates.
17.44+16.97
=17.21V/µs
2
PSRR
PSRR provides a measure of how well a circuit rejects ripple, of various frequencies, injected at its input.
To calculate PSRR, connect opamp in unity gain configuration, provide analog ground at input, provide
AC analysis on VDD . This gives negative plot of PSRR.
𝑉
PSRR = 20log ( 𝑉𝑜𝑢𝑡)
𝑖𝑛
From the plot, we can infer PSRR~126dB
Power consumption
Can be calculated using .op directive and checking the current flowing through VDD
Power consumed = Vdd ×I(Vdd) = 2.5 × (5.052 × 10-5 ) = 0.1263mW

Offset voltage
The input offset voltage is defined as the DC voltage that must be applied between the two input terminals
of the op amp to obtain zero volts at the output. The dc voltage between two output terminals (or
the output terminal and ground for circuits with one output) when the input terminals are grounded.
Input offset voltage = 0.043V
Output offset voltage = 0.0054V

Conclusion
Gain 87dB
Phase Margin 75°
3dB frequency 5kHz
CMRR 100dB
Output swing 2.051V
ICMR 0.4 to 2.2
Slew Rate 17.21V/µs
PSRR 126dB
Power Consumed 0.1263mW
Input offset voltage 0.043V
Output offset voltage 0.0054V
Problems and Innovations
When we calculated the required parameters on paper, we used K n =150µ and Kp =60µ and Vtn and Vtp
were approximately considered to be 0.5V and 0.4V respectively. But during actual simulation, values
turned out to be slightly different than expected.
To resolve this error, .step param directive was used on LT Spice and correct desirable values were
achieved.
To increase the voltage swing we increased the load capacitance value, but it could not be increased after
a certain value. So instead we increased other capacitances but it decreased the slew rate as a trade-off.

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A report on

Design of a Two Stage Single-Ended Output

Krish Ambre 2017B4A80869P

Submitted in partial fulfillment of the course

Required Specifications and Restrictions

Transistor Length(µm) Width(µm)

By performing transient analysis, we can get output swing

Output swing = 2.051V

ICMR = 0.4 to 2.2

Slew Rate is calculated as an average of positive and negative slew rates.

From the plot, we can infer PSRR~126dB

Power consumed = Vdd ×I(Vdd) = 2.5 × (5.052 × 10-5 ) = 0.1263mW

Input offset voltage = 0.043V

Output offset voltage = 0.0054V

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