SEQUENTIAL LOGIC

Unit-IV

SACHIN DHARIWAL
Assistant Professor
Subject Code: EC-302 ECE Department, DTU
 Objective
▪ Introduction

▪ Timing matrix for sequential circuits

▪ Classification of memory elements

▪ Static Latches and registers

▪ The Bi-stability principle

▪ Static latches and Registers

 Introduction
Combinational Logic Circuits Sequential Logic Circuits

▪ Output is function of current input values. ▪ Output is function of current input values and also
▪ Do not remember past history. preceding input values.
▪ Remembers past history of the system.

Note:
▪ Unlike combinational in sequential circuits timing issues are very critical.
▪ Output has to be held till the time next input is actually coming to the combinational logic block.
▪ It wait till output reaches the combinational block.
 Timing Metrics for Sequential Circuits
Setup Time (tsu): The time that the date input must be valid (stable) before the clock transition. (i.e. 0→ 1
transition for a positive edge-triggered register.)

Hold Time (thold): The data input must remain valid (stable) after the clock edge.

Clock Period (T): The time at which the sequential circuits operates, must accomodate the longest delay of
any stage in the network.

tplogic: The worst propagation delay of combinational circuit.

tcd: Minimum delay at which we get the output, is also called contamination delay.
 Classification of Memory Elements
Foreground Versus Background Memory:

▪ Memory that is embedded into logic is foreground memory is often organized as individual registers
or register banks. Ex: Shift register
▪ Large amounts of centralized memory core are referred to as background memory. Ex: 6T SRAM Cell

Static Versus Dynamic Memory:

▪ Static memories preserve the state as long as the power is turned on.
▪ They are build by using positive feedback or regeneration.
▪ Dynamic memories store data for short period of time, perhaps milliseconds.
 Cont…
Latches Versus Registers:
▪ A latch is a level sensitive circuit that passes the input to the output when clock signal is high.
This latch is said to be in transparent mode.
▪ Contrary to level-sensitive latches, edge-triggered registers only sample the input on a clock transition
i.e. 0→ 1 for a positive edge triggered register and 1 →0 for negative edge triggered register.
 Static Latches and Registers
The Bi-Stability Principle:
▪ Static memories use positive feedback to create bi-stable circuit.
▪ Bi-stable circuit has two stable states that represents 0 and 1.
▪ Positive feedback loop helps to store data for longer period of time.

▪ It can be operated at A,B and C nodes.

▪ At C points acts as an amplifier, it is an unstable point.
▪ A and B are stable point.
 Static Latches and Registers
The Bi-Stability Principle:
▪ When the gain of the inverter in the transient region is larger than 1, A and B are the only stable points
and C is a meta-stable operation point.

A bi-stable circuit also known as flip-flop is useful only if there exist a means to bring it from one state to the other one.
In general two different approaches may be used.
1. Cutting the feedback loop: Once the feedback loop is open, a new value can easily be written into output. Such a
latch is called multiplexer based.
2. By applying a trigger signal at the input of the flip-flop a new value is forced into the cell by overpowering the stored
value. A careful sizing of the transistors in the feedback loop is necessary.
 Static Latches and Registers
Multiplexer based latches:
▪ The most robust and common technique to build a latch involver the use of transmission-gate multiplexers.

MUX based Positive latch using transmission gate MUX based latch using nMOS pass transistor

▪ CLK=1, Q=D, latch takes samples of the input. ▪ CLK=1, Latch sample the D input
▪ CLK=0, Q=Q, latch holds the previous output. ▪ CLK=0, Latch is on hold mode
▪ transistor logic passes the degraded high voltage VDD-Vtn
▪ Noise margin and switching performance is impacted here.
 Static Latches and Registers
Multiplexer based latches:
▪ The most robust and common technique to build a latch involver the use of transmission-gate multiplexers.

MUX based Positive latch using transmission gate MUX based latch using nMOS pass transistor

▪ CLK=1, Q=D, latch takes samples of the input. ▪ CLK=1, Latch sample the D input
▪ CLK=0, Q=Q, latch holds the previous output. ▪ CLK=0, Latch is on hold mode
▪ transistor logic passes the degraded high voltage VDD-Vtn
▪ Noise margin and switching performance is impacted here.
 Static Latches and Registers
Master Slave edge triggered Register:
▪ The most common approach for constructing an edge-triggered register is to use master slave configuration.
▪ The register consist of cascading a negative latch (master stage) with a positive one (slave stage).

Positive edge-triggered based on master-slave configuration

▪ The value of Q is the value of D right before the rising edge of the clock, achieving positive-edge triggered effect.
 Objective
▪ Master Slave edge triggered register using MUX

▪ Non-Ideal Clock Signals

▪ Low Voltage Static Latches

 Static Latches and Registers
Master Slave edge triggered Register:
▪ The most common approach for constructing an edge-triggered register is to use master slave configuration.
▪ The register consist of cascading a negative latch (master stage) with a positive one (slave stage).

Positive edge-triggered based on master-slave configuration

▪ The value of Q is the value of D right before the rising edge of the clock, achieving positive-edge triggered effect.
 Static Latches and Registers
Master Slave edge triggered Register using MUX:

Master-slave positive edge-triggered register using multiplexers

CLK=0, T1 →ON, T2 →OFF

T3 →OFF, T4 →ON
Slave will not sample any data.
Slave feedback loop is valid, it holds the previous output.
CLK=1, T1 →OFF, T2 →ON
T3 →ON, T4 →OFF
T3 will store the data at its output.
 Static Latches and Registers
Master Slave edge triggered Register using MUX:

Master-slave positive edge-triggered register using multiplexers

Important Points:
▪ At no point of time input and output is transparent.
▪ Clock load is very high, driving 8 transistor.
▪ Capacitance loading is very high.
▪ The drawback of the transmission gate register is the high capacitive load presented to the clock signal.
▪ One approach to reduce the clock load at the cost of robustness is to make the circuit ratioed.
 Static Latches and Registers
Master Slave edge triggered Register using MUX:

Reduced load clock load static master-slave register

CLK=0
𝐶𝐿𝐾 = 1, T1 →ON, T2 →OFF
CLK=1
𝐶𝐿𝐾 = 0, T1 →OFF, T2 →ON
▪ Forward inverters can be made stronger than reverse one, otherwise I2 and I4 will drag all the data.
▪ Clock load is reduced by half.
 Static Latches and Registers
Master Slave edge triggered Register using MUX:
▪ The penalty paid for the reduced in clock load is an increase design complexity. The sizing of the transmission gate is
a crucial parameter.
▪ Another problem with this scheme is reverse conduction.

Reverse conduction possible in the transmission gate.

▪ When the slave is ON, T2 and I4 combination can influence the data stored in I1-I2 latch, if I4 is not made weaker
compare to I3.
 Static Latches and Registers
Non-Ideal Clock Signals:
▪ Due to delay the CLK starts shifting to right side, and it may overlap with 𝐶𝐿𝐾. (1-1 overlap)

▪ When CLK=1 slave should stop sampling the master output and go into hold mode.
▪ When CLK=1 and 𝐶𝐿𝐾=1 (overlap period) both sampling transistor conducts and direct path between Q and D.
▪ The output can change at rising edge for negative edge triggered register.
▪ This problem is known as RACE problem.
 Static Latches and Registers
Non-Ideal Clock Signals:
▪ Race problem can be avoided by using two non-overlapping clocks PH1 and PH2 and keeping non-overlap time large.

▪ If PHI1=1, PHI2=0, data is sampled, input loop and slave is disconnected.

▪ If PHI1=0, PHI2=1, data is not sampled by master.
▪ Last value of the data available at the input of slave is sampled and slave feedback is disconnected.

▪ Pass transistor logic is used which have a signal integrity issue.

▪ Slave might have a problem of signal degradation due to pass transistor.
 Static Latches and Registers
Low Voltage Static Latches:
▪ The scaling of the supply voltage is critical for low-voltage operation.
▪ Scaling to low supply voltages thus requires the use of reduced threshold devices.
▪ One approach to solve this problem is multiple threshold devices at critical path.
▪ Critical path→Use Low threshold devices
▪ Non-critical path → Use high threshold devices.

▪ Sleep=0, 𝑆𝑙𝑒𝑒𝑝=1, Inverter is ON.

▪ CLK=0, TG becomes transparent. Output of TG= 𝐷 ഥ, Q = D
▪ CLK=1, Vertical Tg is ON, Latch is in hold mode.
▪ Sleep Transistor is high Vt transistor. They do not come in critical path, allows inverter to switch On and OFF.
 Summary
▪ The sequential logic circuit has a memory in which the output depends on the current input as well as preceding
inputs.

▪ A latch is a level sensitive device while a register is an edge triggered device.

▪ Static memories use positive feedback to create a bi-stable circuit, this is having two stable states and one meta-stable
state.

▪ To avoid the problem of non-ideal clocks, we prefer two non-overlapping clocks.

▪ For low-voltage devices and scaling of the supply voltage, we prefer multiple threshold devices.
 Dynamic Latches and Registers
▪ When the registers use in computational structures that are constantly clocked, the requirement that the memory
should hold state for extended periods of time, can be significantly relaxed.
▪ The temporary charge storage on the parasitic capacitor is used to represent the logic signal.
▪ The absence of charge represents 0 while the presence of the charge represents 1.
▪ To preserve the signal integrity, a periodic refresh of the value is necessary, hence the name dynamic storage.

Dynamic Transmission Gate Edge Triggered Registers:

▪ CLK=0, T1 is ON and T2 is OFF., Capacitor charges to input value.

▪ CLK=1, T1 is OFF and T2 is ON, Q=D
▪ The setup time for this circuit is simply the delay of the transmission gate.
▪ The hold time is approximately zero, since the transmission gate is turned off on the clock edge and further change in
input is ignored.
▪ The propagation delay is the delay of two inverters plus the delay of transmission gate.
 Dynamic Latches and Registers
Dynamic Transmission Gate Edge Triggered Registers:

▪ Clock overlap is an important concern for this register.

▪ During 0-0 overlap NMOS of T1 and PMOS of T2 are simultaneously ON and creates a direct path for data to flow from
▪ D input of the register to Q output.
▪ In 1-1 overlap the path exists through PMOS of T1 and NMOS of T2.
 Objective
▪ Dynamic Transmission Gate edge-triggered Registers

▪ C2MOS Registers

▪ Dual edge-triggered Register

▪ True single phase clocked Register

 Dynamic Latches and Registers
▪ When the registers use in computational structures that are constantly clocked, the requirement that the memory
should hold state for extended periods of time, can be significantly relaxed.
▪ The temporary charge storage on the parasitic capacitor is used to represent the logic signal.
▪ The absence of charge represents 0 while the presence of the charge represents 1.
▪ To preserve the signal integrity, a periodic refresh of the value is necessary, hence the name dynamic storage.

Dynamic Transmission Gate Edge Triggered Registers:

𝑡𝑠𝑒𝑡𝑢𝑝 = 𝑡𝑇1

𝑡𝐻𝑜𝑙𝑑 = 0

𝑡𝑐−𝑞 = 𝑡𝐼1 + 𝑡𝑇2 + 𝑡𝐼3

Positive edge triggered register

▪ CLK=0, T1 is ON and T2 is OFF., Capacitor charges to input value.

▪ CLK=1, T1 is OFF and T2 is ON, Q=D
▪ The setup time for this circuit is simply the delay of the transmission gate.
▪ The hold time is approximately zero, since the transmission gate is turned off on the clock edge and further change in
input is ignored.
▪ The propagation delay is the delay of two inverters plus the delay of transmission gate.
 Dynamic Latches and Registers
Dynamic Transmission Gate Edge Triggered Registers:

▪ Clock overlap is an important concern for this register.

▪ During 0-0 overlap NMOS of T1 and PMOS of T2 are simultaneously ON and creates a direct path for data to flow from
▪ D input of the register to Q output.
▪ Any change in D, reflects at the output Q.
▪ In 1-1 overlap the path exists through PMOS of T1 and NMOS of T2.

Solution:
▪ Do not let overlap happen
▪ For 0-0 overlap
▪ For 1-1 overlap

▪ Maintain a phase difference between two clock such that simultaneously 0-0 and 1-1 overlap do not occur.
 Dynamic Latches and Registers
𝑪𝟐 𝑴𝑶𝑺 (𝑪𝒍𝒐𝒄𝒌𝒆𝒅 𝑪𝑴𝑶𝑺) 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓:
▪ In C2MOS register with CLK-𝐶𝐿𝐾 clocking is insensitive to overlap, as long as the rise and fall times of the clock edges
are sufficiently small.
▪ For CLK=0, the master is in evaluation mode and slave is in hold mode. (X = 𝐷) ഥ
▪ For CLK=1, the master is in hold mode and slave is in evaluation mode. (Q = 𝑋ത = 𝐷)
 Dynamic Latches and Registers
𝑪𝟐 𝑴𝑶𝑺 (𝑪𝒍𝒐𝒄𝒌𝒆𝒅 𝑪𝑴𝑶𝑺) 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓:

▪ C2MOS latch is insensitive to clock overlaps because those overlaps activate either the pull-up or pull-down networks
of the latches but never both of them simultaneously.
▪ In 0-0 overlap, M3 and M7 are off,
▪ If D=0, M2 and M4 are ON, VX=VDD, M6→OFF, M5 →ON. Q holds the previous state.
▪ In 1-1 overlap, M4 and M8 are off.
▪ If D=1, M3 and M1 are ON, VX=0, M6→ ON. Q holds the previous state.
▪ D and Q are not transparent in case of 0-0 and 1-1 overlap.
Issue: In 1-1 overlap, If VX=VDD, Q=0 (If 𝑡𝑀7 + 𝑡𝑀5 < 𝑡𝑀1 + 𝑡𝑀3 )
To avoid this problem keep, 𝑡𝑀7 + 𝑡𝑀5 > 𝑡𝑀1 + 𝑡𝑀3
 Dynamic Latches and Registers
𝑫𝒖𝒂𝒍 𝒆𝒅𝒈𝒆 𝒕𝒓𝒊𝒈𝒈𝒆𝒓𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓:
▪ Two parallel Master-Slave edge-triggered registers are used.
▪ It is possible to design a sequential circuit which samples the data
on both the edges of clock.
▪ The advantage of this scheme is that a lower frequency clock is
distributed for the same functional throughput, resulting in power saving.
▪ It consist of two parallel master-slave edge-triggered registers, whose
outputs are multiplexed by using tri-state drivers.

Working:
▪ If CLK=1, M2 and M3 are ON. X = 𝐷,ഥ
▪ And M6 and M7 are OFF. On falling edge, Q holds the previous state from
bottom network.
▪ If CLK=0, M9, M10 are ON. Y = 𝐷 ഥ
▪ And M11, M13 are off, on rising edge, Q=D (D is transparent to Q)
 Dynamic Latches and Registers
𝑻𝒓𝒖𝒆 𝑺𝒊𝒏𝒈𝒍𝒆 𝑷𝒉𝒂𝒔𝒆 𝑪𝒍𝒐𝒄𝒌𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓 (𝑻𝑺𝑷𝑪𝑹):
▪ It is possible to design a register that only use a single phase clock.
▪ For positive latch, when CLK is high then the latch is in transparent mode and corresponds to two cascaded inverters,
the latch is non-inverting and propagates the input to the output.
▪ A register can be constructed by cascading positive and negative latches.

▪ Driving a nMOS logic is relatively easier compare to driving a pMOS logic because of low mobility of holes.
▪ Switching time is small in positive latch.
▪ Clock rise time and fall time should be very low.
▪ If you allow clock to rise for large duration of time then you are allowing data to be sampled even at the rising edge
▪ Of the clock, violating the setup time.
▪ Clock must have 5times more speed compare to input data. (Industry standard)
 Dynamic Latches and Registers
𝑻𝒓𝒖𝒆 𝑺𝒊𝒏𝒈𝒍𝒆 𝑷𝒉𝒂𝒔𝒆 𝑪𝒍𝒐𝒄𝒌𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓 (𝑻𝑺𝑷𝑪𝑹):
▪ TSPC offers an additional advantage of embedding logic functionality into the latches.

▪ Similarly other logic gates can be realized using TSPCR.

 Dynamic Latches and Registers
𝑻𝒓𝒖𝒆 𝑺𝒊𝒏𝒈𝒍𝒆 𝑷𝒉𝒂𝒔𝒆 𝑪𝒍𝒐𝒄𝒌𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓 (𝑻𝑺𝑷𝑪𝑹):
▪ TSPC can further be designed with less complexity as only the first inverter is controlled by the clock.
▪ This reduce the clock load but having a disadvantage the all node voltages will not experience the full logic swing.
 Alternative Register Styles
𝑷𝒖𝒍𝒔𝒆 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓
▪ The idea is to construct a short pulse around the rising
or falling edge of the clock. So the data sampling takes
place over the short window.
▪ The combination of glitch-generation circuitry and
the latch results in a positive edge triggered register.

▪ If CLK=0, CLKG=0, Mn is off and Mp is ON, X=VDD

▪ When CLK goes from 0→ 1, both clock might overlap.
 Objective
▪ Pulse Register

▪ Sense Amplifier Based Register

▪ Pipelining

▪ Latches Vs Register Based Pipelining

▪ NORA-CMOS Pipelined Structure

 Alternative Register Styles
𝑷𝒖𝒍𝒔𝒆 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓
▪ Pulse register is constructed using pulse signals.
▪ A short pulse CLKG is generated around rising or falling
edge of clock pulse.
▪ CLKG acts as clock input to the latch, sampling the
input D for a short window.
▪ Pulse Register = Pulse generation circuitry + Register

▪ Initially CLKG is low.

▪ When CLK is low, node X=VDD, MN offand CLKG is low
▪ During rising edge of CLK, CLKG= High for short time
▪ When CLKG is High, MN is ON, thereby pulling node X=0 V, CLKG= 0 V
▪ This cycle repeats for next rising edge of the CLK.
▪ The CLKG pulse duration depends on the delay of the AND gate and
delay of two inverters.
 Alternative Register Styles
𝑷𝒖𝒍𝒔𝒆 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓

▪ The CLKG acts as clock input to the register.

▪ The data D is sampled during the pulse period.
▪ When CLKG=HIGH, Register is active, M2 and M5 ON
▪ If D=HIGH, M1-ON, M3-OFF, M4-OFF, M6-ON, pulling Q=HIGH
▪ If D=LOW, M1-OFF, M3-ON, M4-ON,M6-OFF, pulling Q=LOW
 Alternative Register Styles
𝑷𝒖𝒍𝒔𝒆 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓
▪ Another version of pulsed register is shown below. Contd…

CLK →Clock
𝐶𝐿𝐾𝐷 →Delay inverted Version of CLK

▪ When CLK=0, M3 and M6→OFF,

▪ P1 → ON, x=VDD, P3→ OFF, Q holds previous state
▪ On rising edge of CLK, M3, M6 → ON
▪ 𝐶𝐿𝐾𝐷 → Stays high for short period
▪ M1, M4→ stays ON for short period (ON time decided by the delay of 3 inverter)
▪ During this time circuit is transparent and Date is sampled by latch.
▪ When 𝐶𝐿𝐾𝐷 → goes low, x is decoupled from D, x held to VDD depends upon P2.
▪ On falling edge of CLK, x=VDD, Q holds pervious state.
 Alternative Register Styles
𝑺𝒆𝒏𝒔𝒆 𝑨𝒎𝒑𝒍𝒊𝒇𝒊𝒆𝒓 𝑩𝒂𝒔𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓𝒔
▪ Earlier registers that had been discussed utilized Master Slave concept and glitch technique.

▪ The technique utilizes sense amplifier to realize edge triggered registers.

▪ Sense amplifier circuits accept small input signals and amplify them to generate rail to rail swings.

▪ Sense amplifier circuits are used extensively in memory cores.

NAND CROSS COUPLED SR FLIP FLOP:
Outputs of front end amplifier are given to the inputs of NAND FF
That holds data. It also ensure that differential outputs switch only
Once per clock cycle.

▪ FRONT END AMPLIFIER:

▪ Initially pre-charged.
▪ Samples the differential signal on the rising edge of the clock.
▪ Difference of input signals amplified and available at L1 and L2
▪ based upon the value of CLK.
 Alternative Register Styles
𝑺𝒆𝒏𝒔𝒆 𝑨𝒎𝒑𝒍𝒊𝒇𝒊𝒆𝒓 𝑩𝒂𝒔𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓𝒔
▪ When CLK=0, L1 and L2 both are pre-charged to VDD
▪ If CLK=1, Depending upon the value of differential inputs IN and 𝐼𝑁, L1 and L2 passed on to SR Ff and produces the
output.
▪ Initially frontend amplifier is pre-charged and when clock is high it samples the differential signal at rising edge of
the clock.
 Alternative Register Styles
𝑺𝒆𝒏𝒔𝒆 𝑨𝒎𝒑𝒍𝒊𝒇𝒊𝒆𝒓 𝑩𝒂𝒔𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓𝒔
M5 to M8 : Cross coupled Inverter L1 & L2 : Outputs of cross
coupled Inverter ▪ M1: Evaluation Transistor
▪ M4: Shorting Transistor

▪ During CLK=LOW, M1- OFF, M9 and M10- ON. Hence L1

Precharge
and L2 are Precharged to VDD. Hence M7 and M8- OFF.
NAND SR FF Holds previous state.
M1- ON, ensuring that differential signals (IN and 𝐼𝑁)
don’t affect output during low phase of CLK.

▪ During CLK=HIGH, M1- ON. Based on differential signals

Evaluation
IN and 𝐼𝑁, M2 and M3- enabled. So that difference
between signals is amplified and obtained at L1 and L2.
Cross coupled inverter output is in one of its stable states
based on differential signal inputs.
▪ For e.g, IN=HIGH and 𝐼𝑁 =LOW, M2-ON, M3-OFF, L3-’0’
and L4-’1’ Precharged previous value of L1 and L2=HIGH
makes M5 and M6- ON.
Hence, L1=‘0’ & L2=‘1’, OUT=‘0’ & 𝑂𝑈𝑇 =‘1’
 Alternative Register Styles
𝑺𝒆𝒏𝒔𝒆 𝑨𝒎𝒑𝒍𝒊𝒇𝒊𝒆𝒓 𝑩𝒂𝒔𝒆𝒅 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓𝒔
Need for shorting transistor M4:

▪ The shorting transistor, M4 is used to provide DC leakage path from either node L3, or L4 to ground.
▪ Without the leakage path the node would be susceptible to charging by leakage currents.
▪ The latch could then actually change state prior to the next rising edge of CLK, which is not desirable.
 Summary

▪ The sequential logic circuit with an idea of temporary storage of charge on parasitic capacitors comes into the
category of dynamic logic.

▪ Dynamic Transmission Gate Edge Triggered Registers is suffered from the clock overlapping while C2MOS is
insensitive to overlap.

▪ Dual Edge Registers can reduce the clock frequency by half of the original rate.

▪ The disadvantage of TSPCR is slight increase in the transistor count in the circuit.
 Pipelining: An approach to optimized Sequential Circuit
𝑵𝒐𝒏 − 𝑷𝒊𝒑𝒆𝒍𝒊𝒏𝒆𝒅 𝑽𝒆𝒓𝒔𝒊𝒐𝒏
 Pipelining: An approach to optimized Sequential Circuit
𝑷𝒊𝒑𝒆𝒍𝒊𝒏𝒊𝒏𝒈
▪ Pipelining is a popular design technique often used to accelerate the operation of data-paths in digital
processors.
▪ Let’s take an example to calculate log of ‘a’ and ‘b’ where ‘a’ and ‘b’ are stream of numbers

Clock (a+b) 𝒂+𝒃 𝒍𝒐𝒈 𝒂 + 𝒃

Cycle

1 𝒂𝟏 + 𝒃𝟏 − −

2 𝒂𝟐 + 𝒃𝟐 𝒂𝟏 + 𝒃𝟏 −

3 𝒂𝟑 + 𝒃𝟑 𝒂𝟐 + 𝒃𝟐 𝒍𝒐𝒈 𝒂𝟏 + 𝒃𝟏

4 𝒂𝟒 + 𝒃𝟒 𝒂𝟑 + 𝒃𝟑 𝒍𝒐𝒈 𝒂𝟐 + 𝒃𝟐

5 𝒂𝟓 + 𝒃𝟓 𝒂𝟒 + 𝒃𝟒 𝒍𝒐𝒈 𝒂𝟑 + 𝒃𝟑
 Pipelining: An approach to optimized Sequential Circuit
𝑷𝒊𝒑𝒆𝒍𝒊𝒏𝒊𝒏𝒈
 Objective
▪ Pipelining

▪ Latches Vs Register Based Pipelining

▪ NORA-CMOS Pipelined Structure

 Pipelining: An approach to optimized Sequential Circuit
𝑳𝒂𝒕𝒄𝒉𝒆𝒔 𝒗𝒔 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓 𝑩𝒂𝒔𝒆𝒅 𝑷𝒊𝒑𝒆𝒍𝒊𝒏𝒆𝒔
▪ Pipelined circuits can be conducted by using level-sensitive latches instead of edge-triggered registered.
▪ When CLK and 𝐶𝐿𝐾 are non-overlapping, correct pipelining operation is obtained.

▪ When CLK=1, Input pass transistor is ON, input data is sampled on C1 at the negative edge of the CLK.
▪ When CLK=0, Computation of F starts and result is stored on c2 at falling edge of the 𝐶𝐿𝐾, and computation of G
block starts.
▪ Suffers from the problem of racing because of overlapping CLK and 𝐶𝐿𝐾.
 Pipelining: An approach to optimized Sequential Circuit
𝑵𝑶𝑹𝑨 − 𝑪𝑴𝑶𝑺 − 𝑨 𝒍𝒐𝒈𝒊𝒄 𝒔𝒕𝒚𝒍𝒆 𝒇𝒐𝒓 𝒑𝒊𝒑𝒆𝒍𝒊𝒏𝒆𝒅 𝒔𝒕𝒓𝒖𝒄𝒕𝒖𝒓𝒆𝒔
▪ A C2MOS based pipelined circuit is a race free as long as all the logic function F (implementing by using
static logic) between the latches are non-inverting.

▪ Potential race condition during (0-0) overlap in C2MOS based

design.
▪ Similar problem exist for (1-1) overlap in C2MOS based design.
 Pipelining: An approach to optimized Sequential Circuit
𝑵𝑶𝑹𝑨 − 𝑪𝑴𝑶𝑺 − 𝑨 𝒍𝒐𝒈𝒊𝒄 𝒔𝒕𝒚𝒍𝒆 𝒇𝒐𝒓 𝒑𝒊𝒑𝒆𝒍𝒊𝒏𝒆𝒅 𝒔𝒕𝒓𝒖𝒄𝒕𝒖𝒓𝒆𝒔
▪ Examples of NORA-CMOS modules.

▪ Consist of C2MOS pipeline register and NORA dynamic logic function.

▪ Each module consist of combination logic followed by C2MOS latch.
▪ Two modules: CLK module (Evaluate at CLK=1)
▪ 𝐶𝐿𝐾 module (Evaluate at CLK=0)
▪ NORA datapath consist of chain of alternating CLK and 𝐶𝐿𝐾 modules.
▪ Data is passed in pipelined fashion from module to module.
 Objective
▪ SR Latch Circuit

▪ Based on NOR Gate

▪ Based on NAND Gate

▪ Clocked SR Latch
 SR Latch
𝑵𝑶𝑹 𝒈𝒂𝒕𝒆 𝒃𝒂𝒔𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉 𝑪𝒊𝒓𝒄𝒖𝒊𝒕
▪ The bistable element consisting of two cross-coupled inverters has two stable operating modes, or states.
▪ The circuit can perform a simple memory function of holding its state.
▪ Simple two-inverter circuit has no provision for allowing its state to be changed.
▪ To allow such a change of state, we must add simple switches to the bistable element.

Bistable Cross Coupled Invertes CMOS NOR SR Latch

▪ The simple CMOS SR latch, has two such triggering inputs, S (set) and R (reset).
▪ SR latch is also called an SR flip-flop, since two stable states can be switched back and forth.
 SR Latch
𝑵𝑶𝑹 𝒈𝒂𝒕𝒆 𝒃𝒂𝒔𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉 𝑪𝒊𝒓𝒄𝒖𝒊𝒕
▪ Two CMOS NOR gates are used to construct SR latch.
▪ One NOR gate is cross-coupled to the output of another NOR gate, second input enables triggering of the circuit.

CMOS NOR SR Latch Gate level schematic and block diagram Truth Table of NOR SR Latch

▪ The simple CMOS SR latch, has two such triggering inputs, S (set) and R (reset).
▪ SR latch is also called an SR flip-flop, since two stable states can be switched back and forth.
 SR Latch
𝑵𝑶𝑹 𝒈𝒂𝒕𝒆 𝒃𝒂𝒔𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉 𝑪𝒊𝒓𝒄𝒖𝒊𝒕
▪ Two CMOS NOR gates are used to construct SR latch.
▪ One NOR gate is cross-coupled to the output of another NOR gate, second input enables triggering of the circuit.

CMOS NOR SR Latch Operating Modes of transistors Truth Table of NOR SR Latch
 SR Latch
𝑵𝑶𝑹 𝒈𝒂𝒕𝒆 𝒃𝒂𝒔𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉 𝑪𝒊𝒓𝒄𝒖𝒊𝒕
▪ Two CMOS NOR gates are used to construct SR latch.
▪ One NOR gate is cross-coupled to the output of another NOR gate, second input enables triggering of the circuit.

CMOS NOR SR Latch Depletion load nMOS NOR based SR latch

Advantages of CMOS based NOR SR latch Vs Depletion load nMOS NOR SR latch
▪ Virtually no static power dissipation
▪ Output exhibit a full swing from 0 to VDD
▪ Better Noise Margin
 SR Latch
𝑵𝑨𝑵𝑫 𝒈𝒂𝒕𝒆 𝒃𝒂𝒔𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉 𝑪𝒊𝒓𝒄𝒖𝒊𝒕
▪ Two CMOS NAND gates are used to construct SR latch.
▪ One NAND gate is cross-coupled to the output of another NAND gate, second input enables triggering of the circuit.

CMOS NAND SR Latch Gate level schematic and block diagram Truth Table of NOR SR Latch
 SR Latch
𝑵𝑨𝑵𝑫 𝒈𝒂𝒕𝒆 𝒃𝒂𝒔𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉 𝑪𝒊𝒓𝒄𝒖𝒊𝒕
▪ Two CMOS NOR gates are used to construct SR latch.
▪ One NOR gate is cross-coupled to the output of another NOR gate, second input enables triggering of the circuit.

CMOS NAND SR Latch Depletion load nMOS NAND based SR latch

Advantages of CMOS based NAND SR latch Vs Depletion load nMOS NAND SR latch
▪ Virtually no static power dissipation
▪ Output exhibit a full swing from 0 to VDD
▪ Better Noise Margin
 Clocked SR Latch
𝑪𝒍𝒐𝒄𝒌𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉: NOR Based
▪ Asynchronous sequential circuit : SR latch discussed will response to change occurring in input at a circuit delay
dependent time.
▪ Synchronous Circuit: Clock should be added to the circuit so that output will respond to input only during active
period of clock pulse.

Gate level schematic of clocked NOR based SR latch clocked NOR based SR latch Clocked NOR based SR latch waveforms

▪ When CLK=0, latch is in hold mode, input signal has no influence upon the circuit response.
▪ When CLK=1, S,R inputs reaches latches and changes its states depending upon the inputs.
▪ Circuit is strictly level-sensitive during active clock phases.
▪ Even a narrow spike or glitch occurring during an active clock phase can set or reset the latch if the loop delay is
shorter than the pulse width.
 Clocked SR Latch
𝑪𝒍𝒐𝒄𝒌𝒆𝒅 𝑺𝑹 𝑳𝒂𝒕𝒄𝒉: NAND Based
▪ Active Low CK: When CK=1, changes in the input signal level will be ignored.
When CK=0, changes in the input signal levels can be seen.
▪ Active High CK: When CK=1, changes in the input signal levels can be seen.

Clocked NAND based SR latch (Active Low CLK) Clocked NAND based SR latch (Active High CLK) Clocked NOR based SR latch waveforms

▪ CK=0, S=0, R=1, Q=0 (Set) ▪ CK=1, S=1, R=, 0, Q=1 (Set)
THANK YOU

59
 VLSI DESIGN
METHODOLOGY
Unit-V
SACHIN DHARIWAL
Assistant Professor
Subject Code: EC-302 ECE Department, DTU
 Objective
▪ VLSI Design Methodology

▪ Design Time

▪ Types of Design

▪ Full Custom Design

▪ Semi Custom Design

▪ Performance Analysis Versus design time

▪ Technology Window
 VLSI Design Methodology
𝑫𝒆𝒔𝒊𝒈𝒏 𝑻𝒊𝒎𝒆 𝒐𝒇 𝒂𝒏 𝑰𝒏𝒕𝒆𝒈𝒓𝒂𝒕𝒆𝒅 𝑪𝒊𝒓𝒄𝒖𝒊𝒕
Design time of an IC depends on following parameters
▪ Design complexity:
▪ Lead to increase in design cycle time
▪ Performance level:
▪ Design time is more for higher performance level.
▪ Acceptable cost:
▪ Before going to the designing acceptable needs to be considered.
▪ Cost is defined based on the type of design.
𝑻𝒚𝒑𝒆𝒔 𝒐𝒇 𝑫𝒆𝒔𝒊𝒈𝒏
There are two types of design
1. Full Custom Design:
▪ Requires all the components to be designed and verified right from the transistor level.
▪ This methodology is used for mass production and to optimized area and speed and power.
▪ Full custom design has a higher cost.
2. Semi Custom Design:
▪ Used when there is less time for design and for less quantities.
▪ Most of the modules are prebuilt and pretested.
▪ Additional components can be integrated.
▪ This saves a design time but not that optimized and cost-efficient for mass production.
 VLSI Design Methodology
𝑷𝒆𝒓𝒇𝒐𝒓𝒎𝒂𝒏𝒄𝒆 𝑨𝒏𝒂𝒍𝒚𝒔𝒊𝒔 𝑽𝒔 𝑫𝒆𝒔𝒊𝒈𝒏 𝑻𝒊𝒎𝒆

Full-Custom Design: Longer design time

Semi-Custom Design: Shorter design time

 VLSI Design Methodology
𝑷𝒆𝒓𝒇𝒐𝒓𝒎𝒂𝒏𝒄𝒆 𝑨𝒏𝒂𝒍𝒚𝒔𝒊𝒔 𝑽𝒔 𝑫𝒆𝒔𝒊𝒈𝒏 𝑻𝒊𝒎𝒆

Full Custom Design Semi Custom Design

▪ Complete design, layout, geometry, orientation and ▪ Some commonly used design, layout, geometry and

▪ Placement of transistor is done by designer. ▪ Placement of transistor is interfaced with given demand.

▪ Entire design is made without use of any library. ▪ Design is completed with the use of multiple library.

▪ Development time for design before maturity is more. ▪ Development time for design before maturity is less.

▪ It has more opportunity for performance improvement. ▪ It has less opportunity for performance improvement.

▪ Less dependency on existing technology. ▪ Complete dependency on existing technology.

▪ High cost ▪ Low cost

 VLSI Design Methodology
𝑻𝒆𝒄𝒉𝒏𝒐𝒍𝒐𝒈𝒚 𝑾𝒊𝒏𝒅𝒐𝒘
 Objective
▪ VLSI Design Flow

▪ VLSI Design Flow Domains

▪ Y Chart of VLSI Design Flow

▪ Computer Added Design Technology

▪ Basics of CAD Tools in VLSI Design

▪ Important Feature of CAD Tools in VLSI

▪ Design Hierarchy

▪ Regularity

▪ Modularity

▪ Locality
 VLSI Design Flow
𝑽𝑳𝑺𝑰 𝑫𝒆𝒔𝒊𝒈𝒏 𝑭𝒍𝒐𝒘
▪ Specifications: The design flow start with a given set of specification or requirements.
▪ Designing: System should get design with respect to given specifications.
▪ At the end, when the desired specifications are not met, the design has to be modified and re-checked several
time until it meets the required specifications.

𝑭𝒍𝒐𝒘 𝒄𝒉𝒂𝒓𝒕 𝒐𝒇 𝑽𝑳𝑺𝑰 𝑫𝒆𝒔𝒊𝒈𝒏 𝑭𝒍𝒐𝒘

Design Specification HDL Coding

Architecture Design Simulation

Gate Level Design Verification (wrt timing)

No Yes
Circuit Level Design Meets Fabrication
 Domains of VLSI Design Flow
𝑽𝑳𝑺𝑰 𝑫𝒆𝒔𝒊𝒈𝒏 𝑭𝒍𝒐𝒘 𝑫𝒐𝒎𝒂𝒊𝒏𝒔
The design description for a VLSI circuit may be described in forms of three domains.
1. Behavioural Domain
2. Structural Domain
3. Physical Domain
 Y CHART OF VLSI DESIGN
Structural Domain Behavioral
Domain
Processor Algorithm
Register Finite State
ALU Machine
Leaf Cell Module
Description
Transistor Boolean
Equation

Mask
Cell
Placement
Module
Placement
Chip Floor
Plan
Physical Domain
 Computer Added Design Technology
𝑪𝒐𝒎𝒑𝒖𝒕𝒆𝒓 𝑨𝒅𝒅𝒆𝒅 𝑫𝒆𝒔𝒊𝒈𝒏 𝑻𝒆𝒄𝒉𝒏𝒐𝒍𝒐𝒈𝒚

▪ As per Moore’s Law, complexity of IC’s is increasing over the years.

▪ Designing of VLSI circuit with millions of transistor in single IC is beyond human brain.

▪ To design VLSI circuit, computer is required to check layout, circuit performance, process etc.

▪ Computer are used to aid in the design and optimization process.

▪ VLSI designers are normally given a set of design rules based on given technology.
 Computer Added Design Technology
𝑪𝒐𝒎𝒑𝒖𝒕𝒆𝒓 𝑨𝒅𝒅𝒆𝒅 𝑫𝒆𝒔𝒊𝒈𝒏 𝑻𝒆𝒄𝒉𝒏𝒐𝒍𝒐𝒈𝒚

Pattern File

Design Entry

Product Mask

Design
Verification, DRC, For each layer
Simulation etc. wafer processing,
deposit, expose,
develop etch etc.

Pattern Generator
Package

Test
 Computer Added Design Technology
𝑭𝒆𝒂𝒕𝒖𝒓𝒆𝒔 𝒐𝒇 𝑽𝑳𝑺𝑰 𝑪𝑨𝑫 𝑻𝒐𝒐𝒍𝒔
▪ VLSI CAD has following tools to meet design features.
1. Physical Design (Layout, Editor, Circuits Schematics)
2. Physical Verification (DRC (Design Rule Check), Circuit Extractor, Plot output, Visual Checking)
3. Behavioural Verification (Observed timing of the blocks)
 IC Design Complexity Reduction Techniques
𝑫𝒆𝒔𝒊𝒈𝒏 𝑯𝒊𝒆𝒓𝒂𝒓𝒄𝒉𝒚
▪ It involves dividing complex design into various modules and submodules.
▪ This division is done until the complexity of submodules becomes manageable.

▪ Divide and Conquer

▪ Composed system from simpler widgets
▪ Analogy with Software
▪ Break large program into small threads and subroutine
▪ Hierarchy can be there with all domain
▪ Behavioral, structural and physical
▪ Hierarchy in different domains may not work with each other.
 IC Design Complexity Reduction Techniques
𝑹𝒆𝒈𝒖𝒍𝒂𝒓𝒊𝒕𝒚
▪ The designer divides the hierarchy into sets of similar building blocks.
▪ Regularity is the design of array structures consisting of identical cells.
▪ Example: RAM composed of identical cells.
▪ Regularity can be there at many levels.
▪ At transistor level
▪ At Identical Gate level
▪ At micro block
▪ At macro block

Regularity improves following attributes of the system.

▪ Reuse of design
▪ Simplify Verification
▪ Correct by construction
 IC Design Complexity Reduction Techniques
𝑴𝒐𝒅𝒖𝒍𝒂𝒓𝒊𝒕𝒚
▪ Modularity means various functional blocks has well defined functions and interfaces, so that they can be
implemented and tested separately.
▪ All the blocks can be combined easily at the end of the design process to form large system.

𝑳𝒐𝒄𝒂𝒍𝒊𝒕𝒚
▪ Locality ensures that the connection between modules or blocks avoids long distance connection.
▪ Locality ensures that the internal connection of each module is not important for other modules.
▪ Locality ensures that the internals of modules are not visible to any exterior interface.
▪ This enables the outside world to treat each module as a black box with well defined inputs and outputs.
 VLSI Design Style
▪ There are mainly three type of design style.
▪ Each design style has its merits or shortcoming.
▪ Proper choice has to be made by designer to provide the specified functionality at low cost in timely manner.
1. Programmable Logic Devices
▪ Field Programmable Gate Array (FPGA)
▪ Gate Array
2. Standard Cell Design (Semi-Custom Design)
3. Full Custom Design

Which Design Style to Use?

▪ Basically a trade off among several design parameters.
‒ Hardware Cost
‒ Circuit Delay
‒ Time Required
▪ Optimizing on these parameters is often conflicting.
 VLSI Design Style
𝑭𝒊𝒆𝒍𝒅 𝑷𝒓𝒐𝒈𝒓𝒂𝒎𝒎𝒂𝒃𝒍𝒆 𝑮𝒂𝒕𝒆 𝑨𝒓𝒓𝒂𝒚
▪ User / Field programmability
▪ Array of logic cells connected via routing channels (programmable).
▪ Different types of cells
‒ Special I/O cells.
‒ Logic cells (mainly lookup table (LUT) with associated registers)
▪ Interconnection between cells
‒ Using SRAM based switches
‒ Using antifuse elements.

Availability
▪ FPGA chip are manufactured by a number of vendors.
▪ Xilinx, Altera, Actel etc
▪ Products vary widely in capability
▪ FPGA development boards and CAD software available from many sellers.
▪ Allow rapid prototyping in laboratory.
 VLSI Design Style
𝑭𝒊𝒆𝒍𝒅 𝑷𝒓𝒐𝒈𝒓𝒂𝒎𝒎𝒂𝒃𝒍𝒆 𝑮𝒂𝒕𝒆 𝑨𝒓𝒓𝒂𝒚

▪ I/O blocks along the boundary

▪ I/O pins are there along the boundary, for every pin there are I/O blocks which are programmable.
▪ Logic Cells are CLB, which can be modified in terms of their functionality.
▪ Interconnects are also programmable
 VLSI Design Style
𝑭𝒊𝒆𝒍𝒅 𝑷𝒓𝒐𝒈𝒓𝒂𝒎𝒎𝒂𝒃𝒍𝒆 𝑮𝒂𝒕𝒆 𝑨𝒓𝒓𝒂𝒚

2 Block implements: 4 variable logic

functions
2 Flipflops: CLB can be used as storage
cell
Other blocks are used for programming.

CLB Functionalities
XC4000E Configurable Logic Block
Two 4-input function generators
▪ Implemented using lookup table using 16x1 RAM
▪ Can also implement 16x1 memory.
Two 1-bit registers
▪ Each can be configured as flip-flop or latch.
▪ Independent clock polarity.
▪ Synchronous and asynchronous set/Reset
 VLSI Design Style
𝑭𝒊𝒆𝒍𝒅 𝑷𝒓𝒐𝒈𝒓𝒂𝒎𝒎𝒂𝒃𝒍𝒆 𝑮𝒂𝒕𝒆 𝑨𝒓𝒓𝒂𝒚
Look Up Tables (LUT)

LUT: 4x16 decoder followed by 16x1 RAM

 VLSI Design Style
𝑭𝒊𝒆𝒍𝒅 𝑷𝒓𝒐𝒈𝒓𝒂𝒎𝒎𝒂𝒃𝒍𝒆 𝑮𝒂𝒕𝒆 𝑨𝒓𝒓𝒂𝒚
Xilinx FPGA Routing

Switch Matrix: Programmable externally to connect CLB pins

Implemented Using:
SRAM: By loading some bits in memory connections can be switch ON/OFF
Antifuse : By passing high current line can be connected/disconnected
 VLSI Design Style
𝑭𝑷𝑮𝑨 𝑫𝒆𝒔𝒊𝒈𝒏 𝑭𝒍𝒐𝒘

▪ Design Entry
▪ In schematic, VHDL or Verilog
▪ Implementation
▪ Placement & Routing
▪ Bitstream generation
▪ Analyze timing, view layout, simulation etc
▪ Download
▪ Directly to Xilinx hardware devices with unlimited reconfigurations

Advantages
▪ Configurability
▪ Ease of use.
▪ Very short turn-around time
 VLSI Design Style
𝑮𝒂𝒕𝒆 𝑨𝒓𝒓𝒂𝒚

▪ In view of the speed of prototyping capability the gate array comes after FPGA.
▪ Design Implementation of
▪ FPGA chip is done with user programming.
▪ Gate array is done with metal mask design and processing.
▪ Gate array implementation requires a two step manufacturing process.
▪ The first phase which is based on generic mask, result in an array of uncommitted transistors on each GA chip.
▪ These uncommitted chips can be customized later, which is completed by deigning the metal interconnects
between the transistors of the array.
 VLSI Design Style
𝑮𝒂𝒕𝒆 𝑨𝒓𝒓𝒂𝒚

▪ The GA chip utilization factor is higher that that of FPGA.

▪ The used chip area divided by the total chip area.
▪ Chip speed is also higher.
▪ More customized design can be achieved with metal mask designs.
▪ Typical gate array chips can implement millions of logic gates.
 VLSI Design Style
𝑺𝒕𝒂𝒏𝒅𝒂𝒓𝒂 𝑪𝒆𝒍𝒍 𝑩𝒂𝒔𝒆𝒅 𝑫𝒆𝒔𝒊𝒈𝒏

▪ One of the most prevalent design styles.

▪ Also called semi-custom design style.
▪ Requires developing full custom mask set.
▪ Basic Idea
▪ Commonly used logic cells are developed and stored in a standard cell library.
▪ Typical library may contain a few hundred cells (Inverters, NAND gates, NOR gates, AOI gates, OAI gates, 2to 1
MUX, D-latches, flipflops etc.)

Characteristics of the Cells

▪ Each cell is designed with a fixed height.
▪ To enable automated placement of the cells, and routing of inter-cell connections.
▪ A number of cell can be abutted side by side to form rows.
▪ The power and ground rails typically run parallel to upper and lower boundaries of cell.
▪ Neighbouring cells share a common power and ground bus.
▪ The input and output pins are located on the upper and lower boundaries of the cell.
 VLSI Design Style
𝑺𝒕𝒂𝒏𝒅𝒂𝒓𝒂 𝑪𝒆𝒍𝒍 𝑩𝒂𝒔𝒆𝒅 𝑫𝒆𝒔𝒊𝒈𝒏
 VLSI Design Style
𝑺𝒕𝒂𝒏𝒅𝒂𝒓𝒂 𝑪𝒆𝒍𝒍 𝑩𝒂𝒔𝒆𝒅 𝑫𝒆𝒔𝒊𝒈𝒏

Floorplan for Standard Cell Design

▪ Inside the I/O frame which is reserved for I/O cells, the chip area contains rows or columns of standard cells.
▪ Between cell rows are channels for routing.
▪ Over-the –cell routing is also possible.
▪ The physical design and layout of logic cells ensure that
▪ When placed into rows, their height match.
▪ Neighbouring cells can abut side-by-side which provides natural connections for power and ground lines in each
row.

Standard Cell Layout

Feed through cells: to provide vertical

connections
 VLSI Design Style
𝑭𝒖𝒍𝒍 𝑪𝒖𝒔𝒕𝒐𝒎 𝑫𝒆𝒔𝒊𝒈𝒏
▪ Standard cells based design is often called semi custom design.
▪ The cells are pre-designed for general use.
▪ In the full custom design, the entire mask design is done without use of any library.
▪ The development cost of such a design style is high.
▪ The concept of design reuse is becoming popular to reduce design cycle time and cost.
▪ Most rigorous full custom design can be the design of a memory cell.
▪ Static or dynamic
▪ Since the same layout design is replicated, there would not be any alternative to high density memory chip design.
▪ For logic chip design a good compromise can be achieved by using a combination of different design styles on the same
chip.
▪ Standard cells, data-path cells and PLAs
▪ In digital CMOS VLSI full custom design is rarely used due to the high labour cost.
 VLSI Design Style
𝑪𝒐𝒎𝒑𝒂𝒓𝒊𝒔𝒐𝒏
 Design Quality
▪ It is desirable to measure the quality of design in order to improve the chip design.
▪ Following are the important criteria.
▪ Testability
▪ Yield and Manufacturability
▪ Reliability
▪ Technology Updateability
THANK YOU

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