Direct memory access (DMA) Direct memory access (DMA) is a method of transferring data between system memory and

I/O devices without requiring intervention by the microprocessor. DMA is more efficient than programmed I/O, in which the microprocessor reads the data from the sending device and then writes it to the receiving device. In DMA data transfers, data can bypass the system microprocessor as it moves between system memory and I/O devices. DMA improves server performance because the microprocessor does not have to interrupt its processing activities to manage data transfers. The DMA controller is integrated into the processor board and manages all DMA data transfers. Transferring data between system memory and an I/O device requires two steps. Data goes from the sending device to the DMA controller and then to the receiving device. The microprocessor gives the DMA controller the location, destination, and amount of data that is to be transferred. Then the DMA controller transfers the data, allowing the microprocessor to continue with other processing tasks. When a device needs to use the Micro Channel bus to send or receive data, it competes with all the other devices that are trying to gain control of the bus. This process is known as arbitration. The DMA controller does not arbitrate for control of the bus; instead, the I/O device that is sending or receiving data (the DMA slave) participates in arbitration. It is the DMA controller, however, that takes control of the bus when the central arbitration control point grants the DMA slave's request.

Direct Memory Access (DMA)

1. Device wishing to perform DMA asserts the processors bus request signal. 2. Processor completes the current bus cycle and then asserts the bus grant signal to the device. 3. The device then asserts the bus grant ack signal. 4. The processor senses in the change in the state of bus grant ack signal and starts listening to the data and address bus for DMA activity. 5. The DMA device performs the transfer from the source to destination address. 6. During these transfers, the processor monitors the addresses on the bus and checks if any location modified during DMA

operations is cached in the processor. If the processor detects a cached address on the bus, it can take one of the two actions: o Processor invalidates the internal cache entry for the address involved in DMA write operation o Processor updates the internal cache when a DMA write is detected 7. Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal. 8. Processor acknowledges the bus release and resumes its bus cycles from the point it left off.

Why is the device needed?

It generates accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the interval timer to match system requirements and programs the counter for the desired delay or for the desired output. Some common timer/counter/output functions which microprocessors require are: real time clock, event counter, digital one-shot, programmable rate generator, square wave generator, binary rate multiplier, complex wave form generator, and complex motor control.

How does it work?

Basic operation: 1. The user inputs a control word and then an initial count. The Control Word itself specifies which Counter is being programmed and which counting Mode is desired. 2. Counting is enabled via the GATE input. 3. Either at the end of a count or during the count, transitions occur on the Counter OUT pin. 4. These OUT pin transitions are used to do things in the system. 5. The types of OUT pin transitions depend on the Mode which was programmed.

Major device blocks

Data bus buffer: 1. 3-state, bi-directional, 8-bit buffer. 2. Interfaces the 8254 to the system bus. Read Write Logic Block: 1. The Read/Write Logic Block accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254. 2. A1 and A0 select one of the three counters or the Control Word Register to be read from or written into. 3. A low on RD# tells the 8254 that the CPU is reading one of the counters. 4. A low on WR# tells the 8254 that the CPU is writing either a Control Word or an

initial count. 5. Both RD# and WR# are qualified by CS#. Control Word Register: 1. This register is selected by the Read/Write Logic when A1,A0=11. 2. If the CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the counters. 3. The Control Word Register can only be written to. Status information is available with the Read-Back command. Counters: 1. There are three Counters. Each is fully independent of the others. Each Counter may operate in a different Mode. 2. Each counter is a 16-bit synchronous down counter. 3. After power-up, the count value and output of all Counters are undefined. 4. Each counter must be programmed before it can be used. 5. Unused counters need not be programmed. 6. Counters are programmed by writing a Control Word and then an initial count. 7. GATE=1 enables counting, GATE=0 disables counting.

Counter description
Counting element, OLm, OLl, OL: 1. The actual Counter is "CE" in figure 5. 2. OLm and OLl are two 8-bit latches. OL is "Output Latch" The subscripts m and l stand for "Most significant byte" and "Least significant byte". Both are normally referred to as one unit and called just OL. These latches "follow" the CE as it counts. 3. If a suitable Counter Latch Command is sent to the 8254, the latches capture the present count until read by the CPU. Once read, the latches return to "following" the CE. 4. One latch at a time is enabled by the counter's control logic to drive the internal bus. This is how the 16-bit counter communicates over the 8-bit bus. 5. The CE itself cannot be read. If the user wants to read the count, it is the OL that is being read. CE, CRm, CRl, CR: 1. There are two 8-bit registers called CRm and CRl. These are the Count Register (Most significant byte and Least significant byte.) Both are normally just called the CR. 2. When a new count is written to the counter, the count is stored in the CR and later transferred to the CE. 3. The Control Logic allows one register at a time to be loaded from the internal bus. 4. Both bytes are transferred to the CE simultaneously. 5. CRm and CRl cleared when the Counter is programmed so that if the Counter has been programmed for one byte counts (either lsb or msb only) the other byte will be zero. 6. Note that the CE cannot be written into; whenever a count is written, it is written into the CR.

Programming the 8254

1. Counters are programmed by writing a Control Word and then an initial count. 2. Control Words are written into the Control Word Register, which is selected when A0,A1=11. The Control Word itself specifies which Counter is being programmed. 3. Initial counts are written into the Counters, not the Control Word Register. The A0,A1 inputs are used to select the Counter to be written into. 4. The format of the initial count is determined by the Control Word used.

Write operations
There are two conventions for writing to the 8254: 1. For each Counter, the Control Word must be written before the initial count is written. 2. The initial count must follow the count format specified in the Control Word (lsb only, msb only, or lsb then msb). A new initial count may be written to a Counter at any time without affecting the Counter's programmed Mode in any way. However, the actual counting in the Counter will be affected as described in the various Mode definitions.

Read operations
The value of a Counter can be read by any one of the following three methods: 1. A simple READ operation: a. Select the Counter with the A1,A0 inputs. b. Inhibit the CLK of the selected counter by using either the GATE input or external logic. (The CLK must be inhibited or the count may be in the process of changing when it is read, giving an undefined result.) c. Note that stopping the CLK stops the count. 2. Counter Latch Command (does not disturb the count in progress): a. It is written to the Control Word Register like a Control Word, but two bits (D5,D4) distinguish this command from a Control Word. b. The selected Counter's OL latches the count at the time the Counter Latch Command is received. c. The count is held in the latch until it is read by the CPU. d. The count is then unlatched automatically and the OL returns to "following" the CE. 3. Read-Back Command: a. This command allows the user to check the count value, programmed Mode, and current states of the OUT pin and Null Count flag of the selected counter(s). b. This command is similar to several Counter Latch Commands, one for each counter latched.

Mode definitions
CLK PULSE: a rising edge, then a falling edge, in that order, of a Counter's CLK input. Trigger: a rising edge of a Counters GATE input. Counter loading: the transfer of a count from the CR to the CE. MODE 0: Interrupt on terminal count 1. Event counting. 2. After the Control Word is written, OUT is initially low and remains low. 3. When the counter reaches zero. OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter. MODE 1: Hardware retriggerable one-shot 1. OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and remain low until the Counter reaches zero. 2. OUT will then go high and remain high until the CLK pulse after the next trigger. MODE 2: Rate generator 1. Functions like a divide-by-N counter and used to generate a Real Time Clock interrupt. 2. OUT will initially be high. 3. When the initial count has decremented to one, OUT goes low for one CLK pulse. 4. Out then goes high again, the Counter reloads the initial count and the process is repeated. 5. MODE 2 is periodic. The same sequence is repeated indefinitely. MODE 3: Square wave mode 1. Typically used for baud rate generation. 2. Out will initially be high. 3. When half the initial count is expired, OUT goes low for the remainder of the count. 4. MODE 3 is periodic. The same sequence is repeated indefinitely. MODE 4: Software triggered strobe 1. OUT will initially be high. 2. When the initial count expires, OUT will go low for one CLK pulse and then go high again. 3. The counting sequence is "triggered" by writing the initial count. 4. The Counter is loaded on the next CLK pulse following writing a Control Word and initial count. MODE 5: Hardware triggered strobe (retriggerable) 1. OUT will initially be high. 2. Counting is triggered by a rising edge of GATE. 3. When the initial count expires, OUT will go low for one CLK pulse and then go high again. 4. The difference between MODE 4 and MODE 5 is that in MODE 5 the count will not be loaded until the CLK pulse after a trigger.

Operation common to all modes

1. When a Control Word is written to a Counter, all Control Logic is immediately reset and OUT goes to the initial state. It does not take a CLK transition to do this. 2. The GATE input is always sampled on the rising edge of CLK 3. In some MODES the GATE input is level sensitive and some are rising-edge sensitive. In some MODES the GATE input is both edge and level sensitive. 4. New counts are loaded and Counters are decremented on the falling edge of CLK. 5. The largest possible initial count is zero. This is equivalent to 2^16 binary and 10^4 BCD. 6. The Counter does not stop when it reaches zero. In MODES 0, 1, 4, and 5 the Counter wraps around to the highest count (FFFFh or 9999bcd) and continues counting. In MODES 2 and 3 (which are periodic) the Counter reloads itself with the initial count and continues counting from there.