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    Lab 9 (Group 4) - 1

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    MUHAMMAD HUZAIFA
    The document describes an open-ended lab assignment on implementing an excess-3 to Gray code converter using NAND gates. The objectives are to design combinational circuits, understand binary codes and their hardware implementation, and model circuits in Verilog. The lab has three parts: pre-lab tasks of making truth tables and logic diagrams; lab tasks of building the circuit with NAND gates and simulating the design in Verilog; and a post-lab viva. Students are evaluated on pre-lab analysis, modern tool usage in Verilog modeling, and individual and team work in designing and implementing the converter circuit.

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    Lab 9 (Group 4) - 1

    Uploaded by

    MUHAMMAD HUZAIFA
    85 views11 pages
    The document describes an open-ended lab assignment on implementing an excess-3 to Gray code converter using NAND gates. The objectives are to design combinational circuits, understand binary codes and their hardware implementation, and model circuits in Verilog. The lab has three parts: pre-lab tasks of making truth tables and logic diagrams; lab tasks of building the circuit with NAND gates and simulating the design in Verilog; and a post-lab viva. Students are evaluated on pre-lab analysis, modern tool usage in Verilog modeling, and individual and team work in designing and implementing the converter circuit.

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    lab 9 (Group 4)-1

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    The document describes an open-ended lab assignment on implementing an excess-3 to Gray code converter using NAND gates. The objectives are to design combinational circuits, understand binary codes and their hardware implementation, and model circuits in Verilog. The lab has three parts: pre-lab tasks of making truth tables and logic diagrams; lab tasks of building the circuit with NAND gates and simulating the design in Verilog; and a post-lab viva. Students are evaluated on pre-lab analysis, modern tool usage in Verilog modeling, and individual and team work in designing and implementing the converter circuit.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    85 views11 pages

    Lab 9 (Group 4) - 1

    Uploaded by

    MUHAMMAD HUZAIFA
    The document describes an open-ended lab assignment on implementing an excess-3 to Gray code converter using NAND gates. The objectives are to design combinational circuits, understand binary codes and their hardware implementation, and model circuits in Verilog. The lab has three parts: pre-lab tasks of making truth tables and logic diagrams; lab tasks of building the circuit with NAND gates and simulating the design in Verilog; and a post-lab viva. Students are evaluated on pre-lab analysis, modern tool usage in Verilog modeling, and individual and team work in designing and implementing the converter circuit.

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    Department of Electrical Engineering

    Faculty Member: Sir Mughees Ahmed Dated: 21-11-2023

    Semester: 3rd Semester Section: BEE-14B

    Group No.:4

    EE-221: Digital Logic Design

    Lab 09: Excess-3 to Gray Code Conversion using Nand Gates (Open Ended
    Lab)

    PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7


    Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
    Performance of data in Tool Usage Safety and Team marks
    Lab Report Work Obtained

    5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks


    Muhammad Huzaifa 407955

    Fahad Naseer 403897

    Malik Muhammad 406651


    Rizwan

    Muhammad 410884
    Abubaker

    EE221: Digital Logic Design Page 1


    Lab 09: Excess-3 to Gray Code Conversion using Nand Gates

    This Open ended Lab has been divided into two parts:
    In first part you are required to design and implement a Excess-3 to gray code converter.
    The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
    part.
    Objectives:

    ✓ Understand steps involved in design of combinational circuits


    ✓ Understand binary codes for decimals and their hardware realization
    ✓ Write code for combinational circuits using Verilog Gate Level Modeling
    ✓ Design a circuit in Verilog by calling different modules

    Lab Instructions

    ✓ This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab
    Viva session.
    ✓ The lab report will be uploaded on LMS three days before scheduled lab date. The
    students will get hard copy of lab report, complete the Pre-lab task before coming to
    the lab and deposit it with teacher/lab engineer for necessary evaluation.
    ✓ The students will start lab task and demonstrate design steps separately for step-
    wise evaluation(course instructor/lab engineer will sign each step after ascertaining
    functional verification).
    ✓ Remember that a neat logic diagram with pins numbered coupled with nicely
    patched circuit will simplify trouble-shooting process.
    ✓ After the lab, students are expected to unwire the circuit and deposit back
    components before leaving.
    ✓ The students will complete lab task and submit complete report to Lab Engineer
    before leaving lab.
    ✓ There are related questions at the end of this activity. Give complete answers.

    EE221: Digital Logic Design Page 2


    Pre-Lab Tasks: (To be done before coming to the lab)

    1. In the lab you would be implementing an Excess-3 to gray code converter. Make a truth
    table for both the codes by filling in the following tables and Simplify the expressions for
    W,X,Y,Z in terms of A,B,C,D.( Use backside of the page if necessary). Use unused
    combinations as don’t care conditions. Hint, u can take help from
    http://engineeringproblemsandanswers.blogspot.com/2015/03/logic-circuits-1-digit-decimal-in-
    excess-3-to-gray-code-converter.html

    (2Marks- Individual. and Team Work)


    HINT:
    Dec Excess 3 Gray Code
    code Our inputs and outputs are of 4-bit decimal
    A B C D W X Y Z values. You will have to make 4 K-Maps
    0 0 0 0 X X X X (Consider W as independent function of
    0 0 0 1 X X X X input variables A,B,C,D, Make K-Map and
    0 0 1 0 X X X X simplify it). Arrive at the simplest
    expression for each output. Show your k-
    0 0 0 1 1 0 0 0 0
    mapping and equation simplification in
    1 0 1 0 0 0 0 0 1 your lab report. Don’t copy and paste from
    2 0 1 0 1 0 0 1 1 this link, other-wise you will get zero.
    3 0 1 1 0 0 0 1 0
    4 0 1 1 1 0 1 1 0 W=A (B+CD) = ((AB)’(ACD)’)’
    5 1 0 0 0 0 1 1 1 X= A+BCD = ((AA)’(BCD)’)’
    6 1 0 0 1 0 1 0 1
    7 1 0 1 0 0 1 0 0 Y= B’C’D’+B(C+D) = ((BD)’(BC)’(B’C’D)’)’
    8 1 0 1 1 1 1 0 0
    Z=C’=(CC)’
    9 1 1 0 0 1 1 0 1
    1 1 0 1 X X X X
    1 1 1 0 X X X X
    1 1 1 1 X X X X

    EE221: Digital Logic Design Page 3


    2. Draw the logic diagram for Excess-3 to gray code converter using AND, OR and NOT
    gates in the space provided below. You can use 2,3,4 input gates if required. (2 Marks-
    Modern tool usage)

    Proteus:

    EE221: Digital Logic Design Page 4


    3. Draw the logic diagram for Excess-3 to gray code converter using only NAND gates in
    the space provided below, you can use 2,3,4 input Nand gates if required (3 Marks-
    Individual. and Team Work)

    Proteus:

    EE221: Digital Logic Design Page 5


    4. Draw the logic diagram for Excess-3 to gray code converter using only NOR gates in
    the space provided below, you can use 2,3,4 input Nor gates if required (3 Marks-
    Individual. and Team Work)

    Proteus:

    EE221: Digital Logic Design Page 6


    EE221: Digital Logic Design Page 7
    Lab Tasks: (To be completed in the lab)

    Lab Task 1:

    Implement Excess-3 to gray code converter using only NAND gates on hardware. Paste the
    complete circuit diagram, depicting hardware results. (5 Marks - Analysis)

    Dec Excess 3 Gray Code


    Hardware
    result
    A B C D W X Y Z
    0 0 0 1 1 0 0 0 0
    1 0 1 0 0 0 0 0 1
    2 0 1 0 1 0 0 1 1
    3 0 1 1 0 0 0 1 0
    4 0 1 1 1 0 1 1 0
    5 1 0 0 0 0 1 1 1
    6 1 0 0 1 0 1 0 1
    7 1 0 1 0 0 1 0 0
    8 1 0 1 1 1 1 0 0
    9 1 1 0 0 1 1 0 1

    Hardware:

    EE221: Digital Logic Design Page 8


    EE221: Digital Logic Design Page 9
    Lab Task2:

    Design and simulate the circuit k-map equations you obtained in Pre-lab task 1 in Verilog
    dataflow modeling. Give the code and testbench and waveform in the space provided below.
    Data flow code: (3Marks – Modern tool usage)
    module converter(w,x,y,z,A,B,C,D);
    input A,B,C,D;
    output w,x,y,z;
    assign w=(A&B)|(A&C&D);
    assign x=A|(B&C&D);
    assign y=(B&D)|(B&C)|(~B&~C&~D);
    assign z=~C;
    endmodule

    module test1;
    reg A,B,C,D;
    wire w,x,y,z;
    converter t1(w,x,y,z,A,B,C,D);
    initial
    begin
    #100 A=1'b0;B=1'b0;C=1'b0;D=1'b0;
    #100 A=1'b0;B=1'b0;C=1'b0;D=1'b1;
    #100 A=1'b0;B=1'b0;C=1'b1;D=1'b0;
    #100 A=1'b0;B=1'b0;C=1'b1;D=1'b1;
    #100 A=1'b0;B=1'b1;C=1'b0;D=1'b0;
    #100 A=1'b0;B=1'b1;C=1'b0;D=1'b1;
    #100 A=1'b0;B=1'b1;C=1'b1;D=1'b0;
    #100 A=1'b0;B=1'b1;C=1'b1;D=1'b1;
    #100 A=1'b1;B=1'b0;C=1'b0;D=1'b0;
    #100 A=1'b1;B=1'b0;C=1'b0;D=1'b1;
    #100 A=1'b1;B=1'b0;C=1'b1;D=1'b0;
    #100 A=1'b1;B=1'b0;C=1'b1;D=1'b1;
    #100 A=1'b1;B=1'b1;C=1'b0;D=1'b0;
    #100 A=1'b1;B=1'b1;C=1'b0;D=1'b1;
    #100 A=1'b1;B=1'b1;C=1'b1;D=1'b0;
    #100 A=1'b1;B=1'b1;C=1'b1;D=1'b1;
    end
    endmodule

    EE221: Digital Logic Design Page 10


    Waveform:

    Conclusion:
    In this we preform the different operations on the logic gates. We deal
    with OR gates and AND gates and NOT gates also. we use in the Only NAND in one
    task. And one specific task require the only NOR gate. We work hardware on it and
    make clean circuit on board. Make simulation on the Proteus software and we make
    the Verilog code on the Model sim software. We make the truth table of gates. We
    draw the waveform on the Model Sim software. In this lab we learn the conversions
    with NAND gates connections how we will join the gates and take easy work from the
    gates. We converted the excess-3 to gray code. We learnt it.

    EE221: Digital Logic Design Page 11

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