Lect9 Timing Diagram
Lect9 Timing Diagram
Lect9 Timing Diagram
Timing Diagram
Lecture objectives: at the end of this lecture the student will able to:
1- Define the timing diagram.
2- Study and representation of the clock signal.
3- Determine the types of 8085 machine cycles.
9.1 Some of Definitions:
9.1.1 Timing Diagram: Timing diagram is the display of initiation of read/write and
transfer of data operations under the control of 3-status signals
IO / M , S1, and S0.
9.1.2 Instruction Cycle: It is fetching, decoding and executing of a single instruction,
which consists of one to five read or writing operations
between processor and memory or IO devices.
9.1.3 Machine Cycle: It is the one cycle that required to move one byte of data in or
out of the microprocessor. Each one machine cycle consists 3 to
6 clock period, referred to as T-state.
9.1.4 T-state: It is the time of one clock period which depends on operating frequency.
Another definition of the T-state is a portion of an operation carried out
in one system clock period.
There are seven different types of machine cycles in 8085A. Table 9.1 show these types
which its identified depend on status signals IO / M , S1, and S0. These signals are
generated at the beginning of each machine cycle and remained valid for the duration of
the cycle.
9.2 Clock Signal:
The 8085 divide the clock frequency provided by X1 and X2 inputs by 2 which is
called operating frequency. Ideally, the clock signals should be square wave with zero
rise time and fall time, but practically, cannot get zero rise time and fall time. Therefore,
the clock and other signals are always shown with finite rise and fall times see Fig. 9.1.
(a) (b)
Figure 9.1: Clock signal representation; a)ideal, b) Practical
Ex.3/ D0-D7 (Data Bus) it used to transfer the data from IO devices or memory to
microprocessor or from microprocessor to IO device or memory during T2 and T3 states.
It is important to note that through reading data operation, the data will appear on the data
bus during the later part of the T2 state. while, in writing data operation the data will
appear on data bus at the beginning of T2 state, see Fig. (9.6 a & b).
Figure 9.6: Data bus status; a) through reading operation, b) through writing operation.
Why there are difference in appearing of data on data bus through reading and writing
operation.
Ex.4/ A8-A15 (Higher Byte Address) is available on the address bus during T1, T2, and T3
states of each machine cycle, except bus idle machine cycle s shown in Fig. 9.7. below:
Ex.6/ RD and WR are determine the direction of data follow between microprocessor and
IO devices or memory locations. As we noted that these signals activated through T 2 &
T3 states of machine cycle. Both signals are never active at a time. The Fig. 9.9 shows the
timing diagram of RD and WR signals.
Step1: (T1 state) The 8085 processor places the contents of program
counter on the address bus, activate the ALE and send the status signals
IO/M, S1, and S0 with logical status (0 1 1) respectively.
Step 2: (T2 state) The low order address disappears from AD0-AD7 lines.
Also, 8085 processor activates the RD signals to enable the addressed
memory location which places its contents on the data bus (AD0-AD7).
Step 3: (T3 state) The processor loads the contents of data bus on its
Instruction Register and deactivates the RD signal to disables the memory
devices.
Step4: (T4 state) the processor decode the opcode, and on the basis of the
instruction received, it decides whether to enter T5 or to enter T1 of new
machine cycle. One byte instructions those operate on eight bit data (8 bit
operand) are executed in T4. for example: MOV C,B- ANA E- ADD B-
INR C- RAR …etc.
Step5: (T5 & T6 states) the processor performs stack write, internal 16
bits, or conditional return operations depending upon the type of
instruction. One byte instructions those operate on 16 bit data are executed
in T5 & T6. For example DCX H, PCHL, SPHL, INX H, etc.
Step1 (T1 state): processor places the address on the address lines from SP,
Rp, or PC and activates ALE in order to latch low-order of address. Also, it
sends the status signals with logical status (0 1 0) for memory read machine
cycle.
Step2 (T2 state): , 8085 processor activates the RD signals to enable the
addressed memory location which places its contents on the data bus (AD 0-
AD7).
Step 3: (T3 state) The processor loads the contents of data bus on specified
register (F, A, B, C, D, E, H, and L) and deactivates the RD signal to disables
the memory devices.
Figure 9.11 shows the timing diagram and data follow for read memory
machine cycle.
Step1 (T1 state): processor places the address on the address lines from SP or
Rp and activates ALE in order to latch low-order of address. Also, it sends
the status signals with logical status (0 0 1) for memory write machine cycle.
Step2 (T2 state): , 8085 processor places tha data on data bus and activates
the WR signal to writing data into addressed memory location.
Step 3: (T3 state) The processor deactivates the WR signal which disables
the memory device and terminates the write operation.
Figure 9.12 shows the timing diagram and data follow for memory write machine
cycle.
Step1 (T1 state): processor places the address on the address lines from SP,
Rp, or PC and activates ALE in order to latch low-order of address. Also, it
sends the status signals with logical status (1 1 0) for IO read machine cycle.
Step2 (T2 state): , 8085 processor activates the RD signals to enable the
addressed input device which places its contents on the data bus (AD0-AD7).
Step 3: (T3 state) The processor loads the contents of data bus on specified
register (F, A, B, C, D, E, H, and L) and deactivates the RD signal to disables
the input device.
Figure 9.13 shows the timing diagram and data follow for IO read machine
cycle.
Step1 (T1 state): processor places the address on the address lines from SP or
Rp and activates ALE in order to latch low-order of address. Also, it sends
the status signals with logical status (1 0 1) for IO write machine cycle.
Step2 (T2 state): , 8085 processor places the data on data bus and activates
the WR signal to writing data into addressed output device.
Step 3: (T3 state) The processor deactivates the WR signal which disables
the output device and terminates the writing operation.
Figure 9.14 shows the timing diagram and data follow for IO write machine cycle.
Figure 9.16: Timing diagram of INTA machine cycle and execution of CALL instruction.
DAD instruction which add the contents of register pair to HL registers and
save the results in HL. This instruction required 10 T-states for opcode
fetching machine cycle, and the other six T-states. Four for adding operation
into two machine cycle without any reading or writing operations. The last
two machine cycles of DAD instruction called Bus Idle machine cycles as
shown in Fig. 9.17.
Example1:
T1 : The 1st clock of 1st machine cycle (M1) makes ALE high indicating address latch
enabled which loads low-order address (00 H) on AD7 ⇔ AD0 and high-order
address (10 H) simultaneously on A15 ⇔ A8. The address 00H is latched in T1.
T2 : During T2 clock, the microprocessor issues RD control signal to enable the memory
and memory places 41H from 1000H location on the data bus.
T3 : During T3, the 41H is placed in the instruction register and RD = 1 (high) disables
signal. It means the memory is disabled in T3 clock cycle. The opcode cycle is
completed by end of T3 clock cycle.
Example2:
The MVI B,05H instruction requires 2-machine cycles (M1 and M2). M1 requires 4-
states and M2 requires 3-states, total of 7-states as shown in Fig. 9.19. Status signals
IO/M, S1 and S0 specifies the 1st machine cycle as the op-code fetch.
T1: The high order address {10H} is placed on the bus A15 ⇔ A8 and low-order
address {00H} on the bus AD7 ⇔ AD0 and ALE = 1.
T2: The RD line goes low, and the data 06H from memory location 1000H are placed on
the data bus. The fetch cycle becomes complete in.
T3: The instruction is decoded.
T4: During T4-state, the contents of the bus are unknown.
With the change in the status signal, IO/M = 0, S 1 = 1 and S0 = 0, the 2nd machine cycle
is identified as the memory read. The address is 1001H and the data byte [05H] is fetched
via the data bus. Both M1 and M2 perform memory read operation, but the M1 is called
op-code fetch i.e., the 1st machine cycle of each instruction is identified as the opcode
fetch cycle. Execution time for MVI B,05H i.e., instruction cycle time is:
Solution: The STA instruction stands for storing the contents of the accumulator to a
memory location whose address is immediately available after the instruction (STA). The
8085 have 16-address lines, it can address 216 = 64 K. Since the STA instruction is meant
to store the contents of the accumulator to the memory location, it is a 3-byte instruction.
1st byte is the opcode, the 2nd and 3rd bytes are the address of the memory locations.
The storing of the STA instruction in the memory locations is as Opcode 1st byte Low
address 2nd byte High address 3rd byte Three machine cycles are required to executing
this instruction : opcode Fetch transfers the opcode from the memory to the instruction
register. The 2-byte address is then transferred, 1-byte at a time, from the memory to the
temporary register. This requires two Memory read machine cycles. When the entire
instruction is in the microprocessor, it is executed. The execution process transfers data
from the microprocessor to the memory. The contents of the accumulator are transferred
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Microprocessor lectures Timing Diagram 9th lecture
to memory, whose address was previously transferred to the microprocessor by the
preceding 2-Memory Read machine cycles. The address of the memory location to be
written is generated as
The high order address byte in the temporary register is transferred to the address latch
and the low order address byte is transferred to the address/data latch. This data transfer
is affected by a Memory Write machine cycle. Thus 3-byte STA instruction has four
machine cycles in its instruction cycle. The timing and control section of the
microprocessor automatically generates the proper machine cycles required for an
instruction cycle from the information provided by the opcode. The timing diagram of the
instruction STA is shown in Fig. 9.20. The status of IO/M, S1 and S0 for 4-machine
cycles are obtained from Table 9.1. The condition of IO/M, S1 and S0 would be 0, 1 and 1
respectively in MC1. The status of ALE is high at the beginning of 1st state of each
machine cycle so that AD7 ⇔ AD0 work as the address bus. RD remains high during 1st
state of each machine cycle, since during 1st state of each machine cycle AD7 ⇔ AD0
work as address bus. It remains high during 4th state of the 1st machine cycle also as the
4th state is used to decode the op code for generating the required control signals. The
opcode fetch of STA instruction has 4-states (clock cycles). Three states have been used
to read the opcode from the main memory and the 4th to decode it and set up the
subsequent machine cycle. The action of memory read or write cycles containing 3-states
i.e., T1, T2, and T3 are explained as
T1 : During this period the address and control signals for the memory access are set up.
T2 : The μP checks up the READY and HOLD control lines. If READY = 0, indicating a
slow memory device, the μP enters in the wait state until READY = 1, indicating DMA
request, then only the μP floats the data transfer lines and enters into wait until HOLD =
0.
T3 : In memory read cycles the μP transfers a byte from the data bus to an internal
register and in memory write cycle the μP transfers a byte from an internal register to the
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Microprocessor lectures Timing Diagram 9th lecture
data bus. Thus STA instruction requires 4-machine cycles containing 13-states (clock
cycles). With a typical clock of 3 MHz (= 330 ns), the STA instruction requires 13*330
ns = 4.29 ms for its execution.