Technical Article

Interfacing FPGAs to an
ADC’s Digital Data Output
The Applications Engineering Group

Abstract Power Supply

Input
Interfacing field programmable gate arrays (FPGAs) to an analog-to- VREF

digital converter (ADC) output is a common engineering challenge. Analog Data

This article includes an overview of various interface protocols Input
ADC
Output
FPGA
Interface
and standards as well as application tips and techniques for utiliz- Clock
Input
ing low voltage differential signaling (LVDS) in high speed data Control
converter implementations. GND

Figure 1. There are different interface possibilities to connect an ADC to an FPGA.

Interface Styles and Standards
Interfacing FPGAs to ADC digital data outputs is a common engineering chal- I2C uses two wires: clock and data. It supports a large number of devices on
lenge. The task is complicated by the fact that ADCs use a variety of digital the bus without additional pins. I2C is a relatively slow protocol, operating in
data styles and standards. Single data rate (SDR) CMOS is very common for the 400 kHz to 1 MHz range. It is commonly used on slow devices where part
lower speed data interfaces, typically under 200 MHz. In this case, data is size is a concern. I2C is also often used as a control interface or data interface.
transitioned on one edge of the clock by the transmitter and received by the SPI uses three or four wires:
receiver on the other clock edge. This ensures the data has plenty of time
to settle before being sampled by the receiver. In double data rate (DDR) X Clock
CMOS, the transmitter transitions data on every clock edge. This allows for X Data in and data out (4-wire) or bidirectional data in/data out (3-wire)
twice as much data to be transferred in the same amount of time as SDR; X Chip select (one per nonmaster device)
however, the timing for proper sampling by the receiver is more complicated.
SPI supports as many devices as the number of available chip select lines.
Parallel LVDS is a common standard for high speed data converters. It uses It provides speeds up to about 100 MHz and is commonly used as both a
differential signaling with a P-wire and an N-wire for each bit to achieve control interface and data interface.
speeds up to 1.6 Gbps with DDR or 800 MHz in the latest FPGAs. Parallel
LVDS consumes less power than CMOS, but requires twice the number of Serial PORT (SPORT), a CMOS-based bidirectional interface, uses one or two
wires, which can make routing difficult. Though not part of the LVDS stan- data pins per direction. Its adjustable word length provides better efficiency
dard, LVDS is commonly used in data converters with a source synchronous for non-8% resolutions. SPORT offers time domain multiplexing (TDM) sup-
clocking system. In this setup, a clock that is in-phase with the data is trans- port and is commonly used on audio/media converters and high channel
mitted alongside the data. The receiver can then use this clock to capture the count converters. It offers performance of about 100 MHz per pin. SPORT
data easier since it now knows the data transitions. is supported on Blackfin® processors and offers straightforward implemen-
tation on FPGAs. SPORT is generally used for data only, although control
FPGA logic is often not fast enough to keep up with the bus speed of high characters can be inserted.
speed converters, so most FPGAs have serializer/deserializer (SERDES) blocks
to convert a fast, narrow serial interface on the converter side to a wide, slow JESD204 is a JEDEC standard for high speed serial links between a single
parallel interface on the FPGA side. For each data bit in the bus, this block host, such as an FPGA or ASIC, and one or more data converters. The latest
outputs 2, 4, or 8 bits, but at one-half, one-quarter, or one-eighth of the clock spec provides up to 3.125 Gbps per lane or differential pair. Future revisions
rate, effectively deserializing the data. The data is processed by wide buses may specify 6.25 Gbps and above. The lanes use 8B/10B encoding, reducing
inside the FPGA that run at much slower speeds than the narrow bus going effective bandwidth of the lane to 80% of the theoretical value. The clock is
to the converter. embedded in the data stream, so there are no extra clock signals. Multiple
lanes can be bonded together to increase throughput while the data link
The LVDS signaling standard is also used in serial links, mostly on high speed layer protocol ensures data integrity. JESD204 requires significantly more
ADCs. Serial LVDS is typically used when pin count is more important than resources in the FPGA/ASIC for data framing than simple LVDS or CMOS. It
interface speed. Two clocks, the data rate clock and the frame clock, are often dramatically reduces wiring requirements at the cost of a more expensive
used. All the considerations mentioned in the parallel LVDS section also apply FPGA and more sophisticated PCB routing.
to serial LVDS. Parallel LVDS simply consists of multiple serial LVDS lines.

VISIT ANALOG.COM
 Typical CMOS drivers shown in Figure 3 are capable of generating large tran-
FPGA
sient currents, especially when driving capacitive loads. Particular care must
75 MHz Converter be taken with CMOS data output ADCs so that these currents are minimized
× 128 Bits and do not generate additional noise and distortion in the ADC.
SERDES 600 MHz
FPGA × 16 Bits × 16 Bits
Logic Typical Examples
Generates 10 mA/Bit
fS dV
= 1 V/ns Charging Current when
dt
Figure 2. SERDES blocks in an FPGA interface with high speed serial interfaces on a Driving 10 pF Directly
converter. R
Analog ADC with
General Recommendations Input CMOS Outputs N Bits
C = 10 pF

Some general recommendations are helpful in interfacing between ADCs Simulates 1 Gate Load
and FPGAs. 1
Plus PCB Parasitics
Make RC <0.1 f
S
X Use external resistor terminations at the receiver (FPGA or ASIC), rather For fS = 100 MSPS, RC <1 ns
than the internal FPGA terminations, to avoid reflections due to mismatch If C = 10 pF, R = 100 Ω

that can break the timing budget.

Figure 4. Use series resistance to minimize charging current of CMOS digital outputs.
X Don’t use one digitally controlled oscillator (DCO) from one ADC if
you are using multiple ADCs in the system. Figure 4 shows the case of a 16-bit parallel CMOS output ADC. With a 10 pF
X Don’t use a lot of tromboning when laying out digital traces to the load on each output, simulating one gate load plus PCB parasitics, each
receiver to keep all traces equal length. driver generates a charging current of 10 mA when driving a 10 pF load.
X Use series terminations on CMOS outputs to slow edge rates down and The total transient current for the 16-bit ADC can therefore be as high as
limit switching noise. Verify that the right data format (twos comple- 16 × 10 mA = 160 mA. These transient currents can be suppressed by add-
ment, offset binary) is being used. ing a small resistor, R, in series with each data output. The value of the
With single-ended CMOS digital signals, logic levels move at about 1 V/ns, resistor should be chosen so that the RC time constant is less than 10%
typical output loading is 10 pF maximum, and typical charging currents of the total sampling period. For fS = 100 MSPS, RC should be less than 1 ns.
are 10 mA/bit. Charging current should be minimized by using the smallest With C = 10 pF, an R of about 100 Ω is optimum. Choosing larger values
capacitive load possible. This can usually be accomplished by driving only of R can degrade output data settling time and interfere with proper data
one gate with the shortest trace possible, preferably without any vias. capture. Capacitive loading on CMOS ADC outputs should be limited to a
Charging current can also be minimized by using a damping resistor in single gate load, usually an external data capture register. Under no circum-
digital outputs and inputs. stances should the data output be connected directly to a noisy data bus.
An intermediate buffer register must be used to minimize direct loading of
The time constant of the damping resistor and the capacitive load should the ADC outputs.
be approximately 10% of the period of the sample rate. If the clock rate is
100 MHz and the loading is 10 pF, then the time constant should be 10% of Output Driver V+ V–
VDD
10 ns or 1 ns. In this case, R should be 100 Ω. For optimal signal-to-noise
ratio (SNR) performance, a 1.8 V DRVDD is preferred over 3.3 V DRVDD. IS T (3.5 mA)
~1.2 V 350 mV
V– V+
However, SNR is degraded when driving large capacitive loads. CMOS out-
Q1 Q2
puts are usable up to about 200 MHz sampling clocks. If driving two output 100 Ω RTERM
loads or trace length is longer than 1 or 2 inches, a buffer is recommended. A– A+
Z0 = 50 V+
1.2 V
VDD 3.5 kΩ 3.5 kΩ LVDS
Receiver
Z0 = 50
V–
Q3 Q4
dV
PMOS
dt dV
I=C A+ A–
dt
LVDS Output—Constant
Current Output
IS B (3.5 mA) Minimizes Coupling Effect
NMOS
I C
External
Load
Figure 5. Typical LVDS driver design.

Figure 5 shows a standard LVDS driver in CMOS. The nominal current is 3.5 mA
and the common-mode voltage is 1.2 V. The swing on each input at the receiver
Figure 3. Typical CMOS digital output drivers. is therefore 350 mV p-p when driving a 100 Ω differential termination resistor.
This corresponds to a differential swing of 700 mV p-p. These figures are
ADC digital outputs should be treated with care because transient currents derived from the LVDS specification.
can increase the noise and distortion of the ADC by coupling back into the
analog input.

2 // Interfacing FPGAs to an ADC’s Digital Data Output

 EYE: ALL BITS ULS: 10000/15600 EYE: ALL BITS ULS: 10000/15596
500
200
Eye Diagram Voltage (mV)

Eye Diagram Voltage (mV)

0 0

–200

–500

–1 ns –0.5 ns 0 ns 0.5 ns 1 ns –1 ns –0.5 ns 0 ns 0.5 ns 1 ns

(a) (b)
Smaller Output
Swing = Save Power:
~30 mW at 40 MSPS to 65 MSPS

100 100
Tie Jitter Histogram (Hits)

Tie Jitter Histogram (Hits)

50 50

0 0
–100 ps 0 ps 100 ps –100 ps 0 ps 100 ps

(c) (d)

Data Eye for LVDS Outputs in Data Eye for LVDS Outputs in
ANSI Mode with Trace IEEE Mode with Trace
Lengths Less than 12” Lengths Less than 12”
on Standard FR-4 on Standard FR-4

Figure 6. ANSI vs. IEEE LVDS standards.

There are two LVDS standards: one is defined by ANSI and the other by IEEE. Figure 7 compares the ANSI and IEEE LVDS standards with long trace lengths
While the two standards are similar and generally compatible with each other, above 12” or 30 cm. Both graphs are driven at the ANSI version standard.
they are not identical. Figure 6 compares an eye diagram and a jitter histogram In the graph on the right, the output current is doubled. Doubling the output
for each of the two standards. IEEE standard LVDS has a reduced swing of current cleans up the eye and improves the jitter histogram.
200 mV p-p as compared to the ANSI standard of 320 mV p-p. This helps to
Note the effects of a long trace on FR4 material in Figure 8. The left plot shows
save power on the digital outputs. For this reason, use the IEEE standard if it
an ideal eye diagram, right at the transmitter. At the receiver, 40” away, the
will accommodate the application and connections that need to be made to
eye has almost closed and the receiver has difficulty recovering the data.
the receiver.

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 EYE: ALL BITS ULS: 9600/15600 EYE: ALL BITS ULS: 9599/15599
500 400
200 200
Eye Diagram Voltage (mV)

Eye Diagram Voltage (mV)

0 0

–200 –200

–500 –400

–1 ns –0.5 ns 0 ns 0.5 ns 1 ns –1 ns –0.5 ns 0 ns 0.5 ns 1 ns

(a) (b)

Smaller Output
Swing = Save Power:
~30 mW at 40 MSPS to 65 MSPS

100

100
Tie Jitter Histogram (Hits)

Tie Jitter Histogram (Hits)

50

50

0 0
–100 ps 0 ns 100 ps –150 ps –100 ps –50 ps 0 ns 50 ps 100 ps 150 ps
(c) (d)
Data Eye for LVDS Outputs in Data Eye for LVDS Outputs in
ANSI Mode with Trace Lengths ANSI Mode with Double Current
Greater than 12”on Standard FR-4 On, Trace Lengths Greater than 12”
on Standard FR-4

Figure 7. ANSI vs. IEEE LVDS standards with traces over 12”.

3.25 Gbps—Ideal Source 3.25 Gbps—After 40 Inch FR-4

(a) (b)

Figure 8. Effects of FR-4 channel loss.

4 // Interfacing FPGAs to an ADC’s Digital Data Output

Troubleshooting Tips

Figure 9. AD9268 ADC with missing bit 14. Figure 11. AD9268 ADC time domain plot with missing bit 14.
In Figure 9, a Visual Analog® digital display of the data bits shows that Figure 11 is a time domain plot of the same data. Instead of a smooth
bit 14 never toggles. This could indicate an issue with the part, the PCB, or sine wave, the data is offset and has significant peaks at points through-
the receiver, or that the unsigned data simply is not large enough to toggle out the waveform.
the most significant bit.

Figure 12. AD9268 ADC with bit 9 and bit 10 shorted together.
Figure 10. AD9268 ADC frequency domain plot with missing bit 14.
In Figure 12, instead of missing a bit, two bits are shorted together so that
Figure 10 shows a frequency domain view of the previous digital data where the receiver always sees the same data on the two pins.
bit 14 is not toggling. The plot shows that the bit is significant and there is
an error somewhere in the system.

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 Figure 15 shows a converter with invalid timing, in this case caused by setup/
hold problems. Unlike the previous errors, which generally showed them-
selves during each cycle of the data, timing errors are usually less consistent.
Less severe timing errors may be intermittent. These plots show the time
domain and frequency domain of a data capture that is not meeting timing
requirements. Notice that the errors in the time domain are not consistent
between cycles. Also, note the elevated noise floor in the FFT/frequency
domain. This usually indicates a missing bit, which can be caused by incorrect
time alignment.

Figure 13. AD9268 ADC frequency domain plot with bit 9 and bit 10 shorted together.

Figure 13 shows a frequency domain view of the same case where two bits
are shorted together. While the fundamental tone is clearly present, the
noise floor is significantly worse than it should be. The degree to which the
floor is distorted depends on which bits are shorted.

Figure 16. AD9268 zoom-in time domain plot with invalid data and clock timing.

Figure 16 is a closer view of the time domain timing error shown in Figure 15.
Again, note that the errors are not consistent from cycle to cycle, but that
certain errors do repeat. An example is the negative spike on the valley of
several cycles in this plot.

Conclusion
This article discussed the standard interfaces—SPI, I2C, SPORT, LVDS, and
JESD204A—used to connect an FPGA to an ADC. Interfacing FPGAs to ADCs
will continue to be a common challenge as the data rate further increases.
Figure 14. AD9268 ADC time domain plot with bit 9 and bit 10 shorted together.
JESD204B supports 12.5 Gbps, and JESD204C will move to 32 Gbps. Careful
In the time domain view shown in Figure 14, the issue is less obvious. Although design will be required to achieve those high data rates.
some smoothness is lost in the peaks and valleys of the wave, this is also com-
mon when the sample rate is close to the waveform’s frequency.
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Figure 15. AD9268 time domain plot with invalid data and clock timing.

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