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    System On Chip Design For Embedded Systems Applications

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    Kiran Pattnaik
    The document discusses system on chip (SoC) design for embedded systems. It explains that SoC combines processor cores, memory, and peripherals onto a single chip to improve performance while reducing size and cost. The document proposes an SoC architecture using open source IP cores connected by a wishbone bus. The objectives are to design and integrate IP cores to create a hardware architecture for applications like voice over IP and data acquisition, and validate the system functionality.

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    System On Chip Design For Embedded Systems Applications

    Uploaded by

    Kiran Pattnaik
    19 views3 pages
    The document discusses system on chip (SoC) design for embedded systems. It explains that SoC combines processor cores, memory, and peripherals onto a single chip to improve performance while reducing size and cost. The document proposes an SoC architecture using open source IP cores connected by a wishbone bus. The objectives are to design and integrate IP cores to create a hardware architecture for applications like voice over IP and data acquisition, and validate the system functionality.

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    The document discusses system on chip (SoC) design for embedded systems. It explains that SoC combines processor cores, memory, and peripherals onto a single chip to improve performance while reducing size and cost. The document proposes an SoC architecture using open source IP cores connected by a wishbone bus. The objectives are to design and integrate IP cores to create a hardware architecture for applications like voice over IP and data acquisition, and validate the system functionality.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    19 views3 pages

    System On Chip Design For Embedded Systems Applications

    Uploaded by

    Kiran Pattnaik
    The document discusses system on chip (SoC) design for embedded systems. It explains that SoC combines processor cores, memory, and peripherals onto a single chip to improve performance while reducing size and cost. The document proposes an SoC architecture using open source IP cores connected by a wishbone bus. The objectives are to design and integrate IP cores to create a hardware architecture for applications like voice over IP and data acquisition, and validate the system functionality.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    System on Chip Design for Embedded Systems Applications

    The rapid development in the field of mobile communication, digital signal processing (DSP) motivated the design engineer to integrate complex systems of multimillion transistors in a single chip. The integration of the transistor in a single chip greatly increases the performance of the system while reduction in system size. Recently, there is a considerable increase in the application front in several areas of engineering and technology. Moores law states that integration density gets doubled every two years, so the complexity of the integrated circuit also increases by keeping the used chip area constant. In order to keep pace with the levels of integration available, design engineers have developed new methodologies and techniques to manage the increased complexity in these large chips. System-on-Chip (SoC) design is proposed as an extended methodology to this problem where pre-designed and pre-verified IP cores of embedded processors, memory blocks, interface blocks, and analog blocks are combined on a single chip targeting a specific application. These chips may have one or more processors on chip, a large amount of memory, bus-base architectures, peripherals, co processors, and I/O channels. These chips integrates systems far more similar to the boards designed ten years ago that to the chips of even a few years ago. The primary drivers for this are the reduction of power, smaller form factor, and lower overall cost. SoC offers many benefits such as smaller space requirements with higher performance. Design reuse- the use of predesigned and pre-verified cores is now the cornerstone of SoC design. It uses reusable IP blocks that supports plug and play integration and in turn allows huge chips to be designed at an acceptable cost, and quality. The benefits of SoC design methodology also comes with challenges such as: larger design space, higher design and prototype costs. Apart from these challenges, the design again needs an expertise in both hardware and software levels for proper hardware and software co-design. Another important aspect of SoC integration is the development of a proper test methodology for post manufacturing test. All these integration issues makes the design time consuming and also expensive. To deal with this inherent integration problems and reduction in design cycle time, platform based SoC design was proposed where new designs could be quickly created from the original platform over many design derivatives. More specifically a platform is an abstraction level that covers a number of refinements to a lower level resulting in improvement of the design productivity. In other side, a new concept that is gaining interest is the Open Core SoC design methodology which is based on publishing all necessary information about the hardware. Open Core group has provided many pre-synthesized and pre-verified hardware core for the designer under GPL/LGPL license. This research proposal uses the Open core based design methodology for designing SoC for embedded system applications. Open Core uses a standard bus WISHBONE to alleviate System-on-Chip

    problem. Open Core is having a collection of many pre-synthesized and pre-verified hardware core for the designer. These cores are well documented with design specifications, RTL codes, and simulation test benches and therefore can be re-used for different applications. Making a design compatible with an onchip bus interface is one way to produce re-usable design. Different IP cores developed independently can be tied together and tested by standardizing the IP core interfaces. Many re-usable digital designs available in the Open Core site are compatible with a standard on-chip interface called WISHBONE bus interface.

    Embedded System Hardware Requirements:


    A comparative study has been done for different applications of embedded systems such as automatic chocolate vending machine, data acquisition system, and robot, mobile phone and voice processor. The corresponding hardware requirements are listed in Table 1.
    Table 1 Hardware Requires Automatic Chocolate vending machine Micro controller 8 CISC Data Acquisition system Robot Mobile phone Adaptive Cruise control System Micro processor 32 RISC Voice Processor (DSP Instruction) Micro processor+DS P 32 RISC

    Processor

    Micro controller 8 CISC

    Micro controller 8 CISC

    Multiprocessor SoC 32 RISC

    Bus Width CISC or RISC Architecture Caches or MMU PROM or ROM or Memory EEPROM OR Flash RAM Interrupts Handler Input Output Ports

    No 4kb

    No 8kb

    No 8kb

    Yes 1MB

    No 64kb

    Yes 1MB

    No

    512B 256B on chip Multiple Ports

    256B

    32kb

    4kb

    4MB+

    256B Onchip Multiple Ports

    256B onchip Multiple Ports

    1MB+ On SoC Key pad and Display ports

    4KB offchip Switch and Display Ports

    1MB Off-chip Input for Speech and Output for replay

    Proposed SoC Architecture:


    Figure 1 shows the proposed architecture of SoC design which is mainly based on the OR1200 processor MASTER, a debug unit for debugging purpose, a Direct Memory Access (DMA), a memory controller that controls an external Flash and SDRAM memory, an Universal Asynchronous Receiver Transmitter (UART), an Audio codec for Voice coding, a standard Ethernet that transmit data over the internet and an internal boot memory. All the cores are connected through the open Core WISHBONE bus interface to form a system that can be used for embedded system applications.

    Figure 1

    Objective and Scope of Research:


    The objectives and scope of this research project are as follows: Design or collection of Intellectual Property cores from Open Core Site. Verification of the cores by writing suitable test bench Integration of these cores to perform final hardware architecture for applications such as VOIP,DAQ Application software development for the hardware architecture. Validation of Functionality of the system by dumping application software in the architecture. FPGA can be used initially for development and validation of the complete systems. Finally the ASIC implementation of the system can be done.

    Hardware and Software Required:


    Virtex FPGA, Xilinx ISE, Synopsys and Cadence Tools for ASIC development.

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