10

7 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
index register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store the contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
JMP <address> Jump to the given address
CMP <address> Compare the contents of ACC with the contents of <address>
CMI <address> Indirect addressing. The address to be used is at the given address. Compare
the contents of ACC with the contents of this second address
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
END Return control to the operating system
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

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(a) Trace the program currently in memory using the trace table, stopping when line 90 is
executed for a second time.
112 (address)
Address Instruction Instruction Memory address
ACC IX
address 100 101 102 103 110 111 112
75 LDR #0

LDX 110+2 = 112 0 0 112 4 1 4 0

76

77 CMI 102 75 0
76 1
78 JPE 91
77 1=0
79 CMP 103
79 1 = 4 (false)
80 JPN 84
80
81 ADD 101
84 1+1=2
82 STO 101
85 2
83 JMP 86 86 0
84 INC ACC 87 1
85 STO 101 88 1
86 LDD 100 89 1
87 INC ACC 90

88 STO 100 76 4

INC IX 77 4=0(false)
89
79 4=4(true)
90 JMP 76
81 4+2=6
91 END
82 6
… 86 1
87 2
100 0
88 2
101 0
89 2
102 112
76 0
103 4
77 0=0(true)

110 1

111 4

112 0

[5]

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(b) The following table shows another part of the instruction set for the processor.

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right-hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left-hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

The contents of memory addresses 50 and 51 are shown:

Memory address Data value

50 01001101

51 10001111

(i) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

XOR B00011111

...........................................................................................................................................

...........................................................................................................................................

[1]

© UCLES 2022 9618/12/O/N/22

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(ii) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

AND 50

...........................................................................................................................................

...........................................................................................................................................

[1]

(iii) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

LSL #3

...........................................................................................................................................

...........................................................................................................................................

[1]

(iv) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

OR 51

...........................................................................................................................................

...........................................................................................................................................

[1]

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(c) Write the register transfer notation for each of the stages in the fetch-execute cycle described
in the table.

Description Register transfer notation

Copy the address of the next instruction into
the Memory Address Register.

Increment the Program Counter.

Copy the contents of the Memory Data

Register into the Current Instruction Register.
[3]

© UCLES 2022 9618/12/O/N/22