CMOS Transceiver Front-Ends in Mobile Communication Handsets - Architectures and

Building Blocks

Cijvat, Pieternella

2004

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Cijvat, P. (2004). CMOS Transceiver Front-Ends in Mobile Communication Handsets - Architectures and
Building Blocks. [Doctoral Thesis (compilation), Department of Electrical and Information Technology].
Department of Electroscience, Lund University.

Total number of authors:

1

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CMOS Transceiver Front-Ends in Mobile
Communication Handsets

Architectures and Building Blocks

Ellie Cijvat

Department of Electroscience

Lund, 2004
 2004 Ellie Cijvat except where stated otherwise

Department of Electroscience
Lund University
P.O. Box 118
221 00 Lund, Sweden

Printed in Sweden by Tryckeriet i E-huset, Lund

November 2004.

ISSN 1402-8662, No. 49.

ii
ABSTRACT

For mobile communication systems in the low-GHz range, CMOS has increasingly
become the technology of choice, and the level of integration in mobile handsets has
risen. The use of off-chip components, which increases the handset assembly time
and costs, is preferably avoided. However, integrating a complete transceiver on a
single chip leads to disturbances between building blocks. This imposes new and
more stringent requirements on building block and transceiver performance, as well
as impacts the choice of transceiver architecture.
In the general introduction, an overview is given of front-end receiver and trans-
mitter aspects as well as RF CMOS technology. This includes the impact of mobile
communication system specifications on architectures and building blocks, transistor
and monolithic inductor modeling, and disturbance issues. Special attention is given
to power amplifiers, the most challenging building blocks in CMOS transceivers.
Papers I, II and III address CMOS receiver front-end aspects and implementations,
while in papers IV and V design and challenges of CMOS power amplifiers are
described.

iii
iv Abstract
ACKNOWLEDGEMENTS

First and foremost, I would like to thank my advisor Henrik Sjöland. Without him I
would not have made it this far, and this thesis would not be in the shape it is now.
I thank my colleagues at the Dept. of Electroscience who made it a pleasant
working environment. A special ’thank you’ goes to the administative and technical
staff at the department, for help with paper work, computers, programs and printed
circuit boards. Anders Karlsson, Lars Olsson, Niklas Troedsson (Dept. of Electro-
science) and Costantino Pala (Conexant) deserve credit for reading (part of) my the-
sis and giving useful feedback.
Furthermore I wish to thank some persons who have helped and supported me in
the past: Dr. Mehran Mokhtari, now at Hughes Research Laboratory (HRL), for his
supervision in the early days, and Prof. Asad A. Abidi, at the University of Califor-
nia, Los Angeles (UCLA), for giving me the opportunity to visit his research group.
The list of people who helped and influenced me could be much larger, but I will
stop here.
I would like to thank my friends for being there for me and showing me different
perspectives on anything from mobile phones to world peace. And last but not least,
I sincerely thank my parents and my sister for supporting me all these years.

Ellie Cijvat

Lund, December 2004

v
vi Acknowledgements
PREFACE

This thesis describes the work I have done in the field of RF CMOS design. The
research was performed at several places: The Royal Institute of Technology, Stock-
holm, the University of California, Los Angeles and the Department of Electro-
science at Lund University.
Both transmitter and receiver front-end architectures and building blocks are
described. In part I, the general introduction, a framework is given of architectural
considerations, mobile communication specifications and RF CMOS integrated cir-
cuit basics. These aspects were all used when performing the research that led to the
papers presented in part II. Some topics are covered more extensively in the general
introduction, such as the disturbance in a receiver caused by spurious signals, and
power amplifiers.

Included Papers
I. E. Cijvat, “A 0.35 µm CMOS DCS Front-end with Fully Integrated VCO”, in
Proceedings of the 8th IEEE International Conference on Electronics, Circuits
and Systems (ICECS 2001), Malta, 2001, pp. 1595-1598.

II. S. Tadjpour, E. Cijvat, E. Hegazi and A. Abidi, “A 900 MHz Dual Conver-
sion, Low-IF GSM Receiver in 0.35 µm CMOS”, IEEE Journal of Solid-State
Circuits, Vol. 36, No.12, pp. 1992 - 2002, Dec. 2001.

III. E. Cijvat, S. Tadjpour and A.A. Abidi, “Spurious mixing of off-channel sig-
nals in a wireless receiver and the choice of IF”, IEEE Transactions on Circuits
and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 8, pp. 539 -
544, Aug. 2002.

IV. E. Cijvat and H. Sjöland, “A Fully Integrated 2.45 GHz 0.25 µm CMOS
Power Amplifier”, in Proceedings of the 10th IEEE International Conference on
Electronics, Circuits and Systems (ICECS 2003), United Arab Emirates, 2003,
pp. 1094-1097.

vii
viii Preface

V. E. Cijvat, N. Troedsson and H. Sjöland, "A Fully Integrated CMOS RF Power

Amplifier with Internal Frequency Doubling", submitted to Analog Integrated
Circuits and Signal Processing.

Related Publications
The following papers are not included but contain both overlapping and comple-
menting material related to this work.

Licentiate of Engineering Thesis:

E. Cijvat, A study of CMOS receiver architectures in Mobile Communication
Handsets for GSM. Tech. Lic. Thesis, Royal Institute of Technology, Dept. of
Electronics, May 2000.

Conference Papers:
S. Tadjpour, E. Cijvat, E. Hegazi and A. Abidi, “A 900 MHz Dual Conversion,
Low-IF GSM Receiver in 0.35 mm CMOS”, in Technical Digest of the IEEE
2001 International Solid-State Circuits Conference (ISSCC), USA, 2001, pp.
292-293.

E. Cijvat, P. Eriksson, N. Tan and H. Tenhunen, “A 1.8 GHz Subsampling

CMOS Downconversion Circuit for Integrated Radio Applications”, in Proc. of
the 5th IEEE International Conference on Electronics, Circuits and Systems
(ICECS 1998), Portugal, 1998, pp. 149-152.

E. Cijvat, P. Eriksson, N. Tan and H. Tenhunen “A 1.8 GHz Subsampling CMOS

Downconversion Circuit for Integrated Radio Circuits”, in Proc. of the IEEE
1998 International Symposium on Circuits and Systems (ISCAS’98), USA,
1998, pp. II-65-68.

E. Cijvat, P. Eriksson, N. Tan and H. Tenhunen “A 1.8 GHz Subsampling CMOS

Downconversion Circuit with Integrated A/D Converter”, in Proc. of the 1997
15th Norchip Conference, Estonia, 1997, pp. 352-359.

N. Tan, E. Cijvat, and H. Tenhunen, “Design and Implementation of High-Per-

formance CMOS D/A Converter”, in Proc. of the IEEE 1997 International Sym-
posium on Circuits and Systems (ISCAS’97), Hong Kong, 1997, pp. 421-424.
CONTENTS

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

Part I - General Introduction

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1. Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2. Mobile Communication Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3. Structure of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Receivers for Mobile Handsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2. Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1. Heterodyne Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2. Direct Conversion Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3. Image Rejection Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4. Subsampling Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3. Receiver Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1. Total Receiver Noise Figure and IIP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2. System Specifications vs. Receiver Requirements . . . . . . . . . . . . . . . . . 18
2.4. Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.1. A Front-End Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.2. Main Mechanisms for Disturbance from Spurious Signals . . . . . . . . . . . 27

3. Transmitters for Mobile Handsets . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2. Transmitter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.1. Direct Conversion Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.2. Two-step Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

ix
x Contents

3.2.3. Direct-Modulation Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2.4. Harmonic Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3. Transmitter Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.1. Transmitter Noise and Non-linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.2. System Specifications vs. Transmitter Requirements . . . . . . . . . . . . . . . 38
3.3.3. Transceiver Calculation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4. Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.1. PA Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.2. Other PA issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5. Transmitter Linearization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6. Disturbance Issues in Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.6.1. Disturbance Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.6.2. Effects of Disturbance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.6.3. Methods to Reduce the Effect of Disturbance . . . . . . . . . . . . . . . . . . . . . 59

4. RF CMOS Technology Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2. Basic MOSFET Characteristics and Models . . . . . . . . . . . . . . . . . . . . 61
4.2.1. Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2.2. Second-Order Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.3. Frequency Dependent Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2.4. Short-Channel Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.3. Noise Sources in a MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3.1. MOSFET Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.2. MOSFET Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.4. Monolithic Inductors in CMOS Technology . . . . . . . . . . . . . . . . . . . . 76
4.4.1. Monolithic Inductor Physics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.4.2. Monolithic Inductor Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Part II - Included Papers

I. A 0.35 µm CMOS DCS Front-end with Fully Integrated VCO . . . . . . . . . . . . . . . . . . 97

 xi

II. A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 µm CMOS. . . . . . . . 109

III. Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the

Choice of IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

IV. A Fully Integrated 2.45 GHz 0.25 µm CMOS Power Amplifier . . . . . . . . . . . . . . . 153

V. A Fully Integrated CMOS RF Power Amplifier with Internal Frequency

Doubling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
xii Contents
 xiii

LIST OF ABBREVIATIONS

3G third generation
ACLR adjacent channel leakage power ratio
AD, A/D, ADC analog-to-digital, analog-to-digital converter
AM-to-PM amplitude modulation to phase modulation
BB baseband
BER bit error rate
BJT bipolar junction transistor
BPF band pass filter
BW bandwidth
CALLUM combined analog locked loop universal modulator
CDMA code division multiple access
CMOS complementary metal-oxide-semiconductor
C/(N+I) carrier-to-noise and interference ratio
CS common source
D/A, DAC digital-to-analog, digital-to-analog converter
DC direct current
DCS digital cellular system
DDD double doped drain
DIBL drain induced barrier lowering
DSP digital signal processing
EER envelope elimination and restoration
F noise factor
FDD frequency division duplexing
FDMA frequency division multiple access
FM frequency modulation
FS frequency synthesizer
FSK frequency shift keying
GaAs gallium arsenide
GMSK Gaussian minimum shift keying
GSM global system for mobile communications
HSDPA high speed downlink packet access
I and Q in-phase and quadrature phase
IC integrated circuit
IF intermediate frequency
IPi i-th order intercept point
xiv List of Abbreviations

IRF image reject filter

LDD lightly doped drain
LINC linear amplification with non-linear components
LNA low noise amplifier
LO local oscillator
LPF low pass filter
MN matching network
MOSFET metal-oxide-semiconductor field effect transistor
NF noise figure
PA power amplifier
PAE power added efficiency
PGA programmable gain amplifier
PWM pulse width modulation
RF radio frequency
RX receiver
SH, S/H sample and hold
Si silicon
SNR signal-to-noise ratio
SoC system-on-chip
TDD time division duplexing
TDMA time division multiple access
TX transmitter
UMTS universal mobile telecommunication system
UWB ultra wide band
VCO voltage controlled oscillator
VLSI very large scale integration
WiMax worldwide interoperability for microwave access
η efficiency
 Part I

General Introduction
xvi
CHAPTER 1

INTRODUCTION

1.1. MOTIVATION
The maturing of communication systems such as GSM, Bluetooth and UMTS, oper-
ating in the low-GHz range, together with technological advancements for CMOS
technologies, has resulted in increased research activities in so-called Radio Fre-
quency CMOS circuits, i.e. analog circuits in a CMOS technology for frequencies up
to several GHz. CMOS circuits for frequencies as high as 60 GHz have been
reported. Most important for this development is the drive for highly-integrated, low-
cost mobile handsets. If both the analog and digital part of a receiver/transmitter
(transceiver) can be implemented in CMOS, a complete system may be implemented
on a single chip. This System-on-Chip (SoC) development brings about issues of
disturbance between the different parts or building blocks of the system, caused by
coupling, either on-chip, through the substrate, or off-chip, through adjacent bond-
wires. These subjects will be briefly touched upon in this thesis.
One of the most challenging analog parts to implement in CMOS is the power
amplifier (PA), for several reasons. Firstly, the transconductance to current ratio gm/I
of a CMOS device is generally lower than that of a bipolar or III-V device, implying
that for the same gain a higher current is needed. Secondly, with decreasing device
length (scaling) in current CMOS technologies the oxide thickness is decreasing as
well, resulting in a lower breakdown voltage. On the other hand, the cut-off fre-
quency fT and the maximum frequency of oscillation fmax for CMOS devices are
approaching the values for Si bipolar devices. In the general introduction of this the-
sis, special attention is given to PA properties such as linearity and efficiency, as well
as to CMOS device modeling and scaling.
Another issue stemming from an increased level of integration and a drive for
low-cost handsets is off-chip filters. These filters are costly, they take up consider-
able space and they complicate handset assembly. Therefore an important goal of
integrated transceiver design is the reduction of the number of these filters. This

1
2 Part I. General Introduction

work addresses receiver and transmitter analog front-end architectures, and an analy-
sis is presented of the effects of removing these filters from the transceiver.

1.2. MOBILE COMMUNICATION SYSTEMS

Before addressing transmitter and receiver properties in detail, some basic concepts
in mobile communication systems will be described. A mobile communication sys-
tem allows a user to communicate by means of a wireless link to a base station (see
Fig. 1.1). Traditionally this was based on speech transmission, where relatively low
data rates can be used while still maintaining a reasonable sound quality. Nowadays
higher data rates are pursued, so that besides speech transmission high data rate
transmission becomes a viable option as well. Third-generation (3G) wireless sys-
tems, capable of higher data rates, are now operated in many countries, and
improved data rates of 3G (e.g., HSDPA [5]) are soon to be deployed. Other systems
aiming at high data rates are for instance WiMax [3] and Ultra Wide Band (UWB)
based systems [4].
As depicted in Fig. 1.1, a mobile communication system can consist of several
cells with one or more base stations serving a number of users. The uplink is defined
as the communication from the user to the base station, while the downlink entails
the communication from the base station to the user. From a user’s point of view the
uplink is equivalent to transmission while the downlink is equivalent to reception [6].
For most modern communication systems different frequency bands are used for
the uplink and downlink. This permits transmission and reception simultaneously,
and is called frequency division duplexing (FDD) [6]. A disadvantage of FDD com-
pared to time division duplexing (TDD), is that users cannot communicate with each
other directly but have to communicate via the base station. A second disadvantage
is that when both transmit and receive modes are on at the same time, the transmitted

uplink

k
nlin
dow user

base station
cells

Fig. 1.1. A mobile communication system.

Chapter 1 Introduction 3

signal will leak to the receive path since the duplex filter located between the trans-
ceiver and the antenna has a finite transmitter-to-receiver isolation.

System Specifications
All mobile communication standards have more or less similar specifications, such
as required bit error rate (BER), minimum detectable signal (sensitivity), blocking
and interference performance, channel bandwidth, modulation scheme, output power
range, frequency bands, et cetera. For each system the value of these requirements
may differ. The maximum output power from the antenna for a mobile handset is for
instance 30 dBm for GSM or DCS class 1 [7], 0 dBm for Bluetooth class 2 [8] and
24 dBm for UMTS (WCDMA) class 3 [9]. System level simulations must be per-
formed to translate system specifications to building block specifications.

Multiple access methods

In order to accommodate several users simultaneously, different so-called multiple
access schemes are in use. GSM and DCS use time division multiple access
(TDMA), i.e. consecutive time slots are assigned to different users [6]. In this way
eight users may use the same frequency band. Bluetooth uses a special kind of fre-
quency division multiple access (FDMA), namely frequency hopping, i.e. each user
is assigned a certain frequency band, but the assigned frequency band changes with
the hopping rate. Finally, UMTS is a code division multiple access system (CDMA)
where a pseudorandom code is used to spread the data over a wider frequency range
before transmission. Many users may then send in the same frequency band simulta-
neously; at reception, each user’s data can be extracted by using the code assigned to
that user.

Transceiver architecture
In Fig. 1.2 a typical handset transmitter/receiver (or transceiver) architecture is
shown. In the receive (RX) path the signal is generally amplified and downconverted
from the radio frequency (RF) to the baseband frequency in one or several steps. The
baseband signal is then digitized in the analog to digital converter (ADC) and
demodulated in the digital signal processing (DSP) part. On a system level a deci-
sion must be taken regarding the amount of signal processing to be performed in the
analog domain. A range of solutions is being or has been investigated, from directly
sampling the RF signal with an AD converter, to full channel selection in the analog
domain. This is a trade-off between complexity, performance and power consump-
tion in the analog and digital part, respectively.
4 Part I. General Introduction

RX baseband
ADC DSP

=
RF
Duplexer

DAC DSP
TX baseband

Fig. 1.2. A general transceiver architecture.

In the transmit (TX) part a baseband signal is modulated in the DSP, converted
to an analog signal in the digital to analog converter (DAC) and then filtered and
upconverted to RF in one or several steps. A power amplifier is used to give the RF
signal the desired power. Similar trade-offs exist in the transmitter part as in the
receiver part. In this thesis the focus will be on the front-end, which may roughly be
defined as the part between the antenna and the baseband. Hereafter ’receiver front-
end’ is meant when ’receiver’ is used, and similarly for ’transmitter’.

1.3. STRUCTURE OF THE THESIS

The thesis is divided in two parts: a general introduction in part I and a selection of
relevant papers in part II.

Part I: General Introduction

In part I, basic aspects of communication systems are revised, divided in receivers,
transmitters, and CMOS technology. In chapter 2 general receiver aspects are
described, such as architectures, noise and linearity, system specifications and build-
ing block requirements, and frequency planning. Chapter 3 describes transmitters,
including architectures, system specifications and building block requirements, fre-
quency planning and power amplifiers including considerations on efficiency and
linearity. Also, disturbance issues in highly integrated RF CMOS transceivers are
addressed. In chapter 4 CMOS technology aspects are investigated, extended to RF
operation, deep-submicron scaling issues, and noise. Inductors are also described,
since they are key elements in several RF building blocks. Both MOSFET and induc-
tor modeling are discussed briefly. Conclusions are presented in Chapter 5.
Much of the contents in chapter 2 and 4 has already been presented in [1]. How-
ever, the author has chosen to incorporate these parts since they complement the
other chapters and cover many issues that come into play in integrated transceiver
design.
Chapter 1 Introduction 5

Part II: Included Papers

The papers included in part II cover many of the aspects described in part I. Papers I,
II and III focus on receiver front-ends. Paper I describes the design of a DCS receiver
with a low-noise amplifier (LNA), a mixer and a voltage controlled oscillator (VCO)
integrated on the same chip. Paper II describes the design, implementation and mea-
surements of a low-IF GSM receiver front-end. In paper III an analysis is presented
of spurious signals in a receiver and the effects on the choice of intermediate fre-
quency (IF).
Papers IV and V both describe issues related to fully integrated CMOS transmit-
ters. In paper IV the design of a class AB power amplifier with power control is pre-
sented, and in paper V the design and measurements of a class C power amplifier
with internal frequency doubling and on-chip VCO is described.
6 Part I. General Introduction
CHAPTER 2

RECEIVERS FOR MOBILE HANDSETS

2.1. INTRODUCTION
In this chapter an overview is given of the most common receiver architectures, such
as the direct-conversion receiver and the heterodyne receiver. Moreover, some less
common receivers are described, such as image-reject receivers and subsampling
receivers. Thereafter system specifications and parameters such as noise figure and
intercept point are presented, as well as frequency planning in a receiver to avoid the
impact of spurious signals.

2.2. RECEIVER ARCHITECTURES

As shown in Fig. 1.2, the function of the receiver front-end is to convert the incom-
ing RF signal to a lower frequency so that the AD converter (ADC) may digitize the
signal. The front-end must ensure a sufficient Signal-to-Noise ratio (SNR). The
receiver therefore typically consists of a Low-Noise Amplifier (LNA) to amplify the
incoming signal without adding too much noise, one or more mixers to convert the
RF signal to a lower frequency, and one or more filters to select the desired signal or
frequency band and to block disturbing signals. Several methods of downconversion
will be described here, such as direct conversion, heterodyne, and subsampling.
Moreover, image reject receivers will be discussed briefly.

2.2.1. HETERODYNE RECEIVERS

One of the most common architectures is the heterodyne receiver 1 (see Fig. 2.1).
The radio frequency (RF) signal passes through a band pass filter (BPF) which is

1. Historically the heterodyne receiver was a single downconversion receiver for which ωIF was rela-
tively low (in the audible frequency region). The superheterodyne receiver as patented by Arm-
strong had a higher ωIF, but still used a single downconversion. Nowadays, generally no
distinction is made between the ‘superheterodyne’ and ‘heterodyne’ receiver. This convention will
be followed in this thesis as well.

7
8 Part I. General Introduction

BPF IRF Mixer fLO

RF LNA
IF

LO 0 fRF f [Hz]
a. b.
Fig. 2.1. A heterodyne receiver architecture, a). architecture, b).
downconversion in the frequency domain.

used to suppress some of the undesired signals outside the receive band. Then the RF
signal is amplified by a low noise amplifier (LNA) and sent through a second band
pass filter, which is sometimes called image reject filter (IRF). The two filters
together can provide an attenuation in the order of 100 dB for signals lying several
hundreds of MHz away from the passband. In many - though not all - mobile com-
munication receivers these two filters are used. Due to the high frequency and the
steepness required, these filters typically are off-chip elements [10], [6], [11], [12],
[13], [14].
The RF signal is downconverted in the mixer, which is also provided with a
local oscillator (LO) signal. The intermediate frequency, or IF, is given by
ω IF = ω RF – ω LO [rad/s] where ω = 2πf . For the case of ω IF > 0 - but ωIF low
enough to be considered a baseband signal - the term ‘low-IF downconversion’ may
be used [15].
Often fLO and fRF are so far apart that the signal is not downconverted to base-
band but to a relatively high IF. Therefore it is common to have a second downcon-
version stage, resulting in a double-conversion heterodyne architecture (see Fig. 2.2).
If ω RF < ω LO then the IF signal will be at negative frequencies. If no special
measures such as complex mixing are taken, the output signal will be indistinguish-
able from one having the same IF at positive frequencies.

fLO1
BPF IRF Mixer Mixer
RF LNA IF2
IF1 IF2

LO1 LO2 0
IF1 fRF f [Hz]

a. b.

Fig. 2.2. A double-conversion heterodyne receiver architecture, a).

architecture, b). downconversion in the frequency domain.
Chapter 2 Receivers for Mobile Handsets 9

An advantage of double-conversion heterodyne receivers is that the total gain in

the receive path can be distributed over several blocks, possibly accompanied by fil-
ters. The issue of gain distribution is related to receiver noise figure versus linearity,
and will be covered more extensively in paragraph 2.3.1. Having the gain distributed
over different frequencies also reduces the risk for self-oscillation.
The main disadvantage of the double-conversion heterodyne receiver is its com-
plexity, including the fact that two LO signals are necessary, and the need for several
filters which generally cannot be integrated on-chip.

Image Frequency
One of the main problems of the heterodyne receiver is the presence of an undesired
signal at the so-called image frequency. This is explained first before methods to
address this problem are discussed.
A downconversion block converts the desired signal at ωRF to
ω IF = ω RF – ω LO . For convenience it is assumed that ω RF > ω LO . Undesired signals
that reach the downconverter input are downconverted as well. A signal situated at
ω RF – 2ω IF will be downconverted to -ωIF, as shown in Fig. 2.3, and can thus distort
the desired signal at +ωIF if positive and negative frequencies are not separated.
Two possible solutions for this problem exist: Firstly, the undesired signals can
be prevented from reaching the downconverter input by means of filtering, and sec-
ondly, the positive and negative frequencies can be separated after downconversion
by so-called image-reject mixing.
The former is highly dependent on filter characteristics, e.g. selectivity, in com-
bination with the allowed blocking signal strengths in a communication system,
while the latter is based on accurate complex mixing to separate the negative and
positive frequency component. In paragraph 2.2.3 some image reject receiver archi-
tectures are described.
In order to get substantial image suppression from filtering, two conditions must
be fulfilled (see Fig. 2.4):
undesired signal

P P

IF IF

f f
fLO f -fIF 0 +fIF
RF
Fig. 2.3. The problem of the image frequency.
10 Part I. General Introduction

interferer
BPF characteristic

IF

fLO fRF f [Hz]

Fig. 2.4. A band pass filter utilized to provide image rejection.

• ωIF must be relatively large, so that the distance between the desired signal and the
image located at ω RF – 2ω IF is substantial,
• the attenuation characteristic of the filter must be relatively sharp.
The filter requirements generally lead to the use of higher-order (> 4th) band pass fil-
ters. A discrete (off-chip), passive band pass filter (BPF) is commonly used [15]. A
typical discrete filter characteristic (see [16]) gives a suppression of 20 dB at 30
MHz from the center frequency, increasing to maximum 60 dB at 200 MHz and
more from the passband. So, if 110 dB of image rejection must be achieved, as in the
GSM handset receiver, two discrete filters may be necessary, e.g. the BPF and IRF in
Fig. 2.1.
Using a discrete filter between the LNA and the mixer has severe disadvantages.
Both the output of the LNA and the input of the mixer have to be matched to the
characteristic impedance of the filter, which may be 50Ω or 300Ω, in order for the fil-
ter to work properly. In the LNA generally an extra stage is added to achieve the
LNA output matching, so that the power consumption will most likely increase.
Moreover, because the filters generally are single-ended, either the building blocks
need to be single-ended as well or differential-to-single-ended converters (baluns)
must be used. Also, the filters suffer from losses in the passband, amounting to 2 - 3
dB for a typical BPF and 3 - 6 dB for a typical IRF.

2.2.2. DIRECT CONVERSION RECEIVERS

A direct conversion receiver has a single downconversion stage, as depicted in Fig.
2.5. In order to convert the desired channel to baseband, the LO frequency must be
equal or close to the RF carrier frequency, the exact location of which is determined
by the channel that is used. The receiver is called ‘homodyne’ if the input signal fre-
quency ωRF and LO frequency ωLO are related such that ω RF = ω LO . In this case the
IF is given by ω IF = ω RF – ω LO = 0 .
The baseband signal can be filtered with a low pass filter (LPF). Depending on
the amount of adjacent channel interference this LPF may need to have a sharp flank
Chapter 2 Receivers for Mobile Handsets 11

fLO
RF BPF LPF
LNA baseband

LO 0 fRF f [Hz]
a. b.
Fig. 2.5. A direct conversion receiver, a). architecture, b). direct
downconversion in the frequency domain.
[6], corresponding to a high-order filter. However, due to the relatively low operating
frequency this filter may be integrated.
The main advantage of direct conversion is the simple structure, since it has no
image frequency problem, and the possibility of utilizing a low pass filter for channel
selection. Thus, this architecture offers a high level of integration and a potentially
low power consumption. However, complex mixing (I and Q, or in-phase and quad-
rature, having 90° LO phase difference [6]) is typically required, since in most com-
munication systems information is also contained in the phase of the signal. Using a
single mixer, this information is lost and cannot be recovered in the baseband.
Some serious drawbacks exist for this architecture [6], [17]. If ω IF = 0 the
desired signal will be corrupted by any DC offset occurring in the circuitry. This off-
set can be minimized using careful design of the front-end, and can then to a large
extent be cancelled in the baseband by further digital signal processing. The penalty
is an increase in complexity. Another problem is the so-called 1/f noise (see also
paragraph 4.4), a low-frequency noise that can be very large at frequencies near DC,
where the received signal will reside after downconversion. The signal-to-noise ratio
(SNR) at baseband will be deteriorated if the designer does not take measures to
reduce the effect of 1/f noise. This problem is particularly prominent in CMOS tran-
sistors. Moreover, the LO signal may leak to either the antenna and thus become an
in-band interferer for other users, or to the RF mixer input where this leaked signal is
self-mixed with the LO signal, causing a large DC component at the mixer output.

2.2.3. IMAGE REJECTION RECEIVERS

As explained in section 2.2.1, the image constitutes a severe problem in heterodyne
receivers. Besides filtering, image reject mixing may be used to reduce this problem.
Several solutions exist:
• a Hartley or Weaver architecture
• the use of a polyphase filter
• keeping the I and Q paths separate throughout the front-end, performing the image
rejection in the baseband.
12 Part I. General Introduction

In any image reject architecture, mismatch in the I and Q signal paths is a crucial
issue. Generally the achievable image rejection using this strategy is in the range of
30 to 40 dB. If the I and Q paths are relatively long, reasonable image rejection will
be difficult to achieve. Several highly integrated receivers achieving high image
rejection have been reported [15], [18], [19].

Hartley and Weaver Image Reject Architectures

A Hartley downconversion architecture is depicted in Fig. 2.6. The RF input signal,
after passing the BPF and LNA, is fed into two mixers driven by quadrature LO sig-
nals. The LO signal for each mixer generally is differential, implying that for a set of
two quadrature mixers as in Fig. 2.6 four phases of the LO signal are needed.
After the RF signal has passed the mixer, the desired frequency component is
selected by means of a low-pass filter (LPF). Thanks to the separation of the IF sig-
nal in two branches, an undesired component originating from the image frequency
can be cancelled, so it is not seen at the output. This is done by means of a 90° phase
shift network and an adder.
Assuming ideal components and an ideal phase shift network, the image is
rejected completely. The 90° phase shift network can be split in two phase shift net-
works of +45° and -45°, one in each branch. If simple RC networks are used to
implement this phase shift, the amplitude in the two paths is only equal for
ω = 1 ⁄ RC . Therefore, this is a very narrowband solution sensitive to mismatches in
R and C. Non-idealities typically limit the image rejection to 30 to 40 dB.
For a Weaver architecture, the phase shifting block in the Hartley architecture is
replaced by a second set of mixers, with ωLO2 much lower than ωLO1 (see Fig. 2.7).
This architecture suffers less from gain mismatch in the phase shifting blocks, but
the secondary image frequency may cause problems. This image component is not
suppressed when ωLO2 is small (see [6]). A Weaver architecture is used in [20].
A special case of image reject receivers, the ‘double-quadrature downconverter’,
was presented in [15]. Here both the RF and LO signals are in quadrature. A higher

LPF
IF
90°
BPF
RF LNA LOI LPF + out

LOQ

Fig. 2.6. The Hartley image reject receiver architecture.

Chapter 2 Receivers for Mobile Handsets 13

LPF

BPF
LNA LO1,I LPF LO2,I +

LO1,Q LO2,Q

Fig. 2.7. The Weaver image reject receiver architecture.

image rejection is thus achieved at the expense of an increased complexity and

higher power consumption.

Polyphase Filters
The low pass filters, phase shifters and adder of the Hartley architecture can be
replaced by a single block, a polyphase filter, which may suppress the undesired
component. The effective image rejection is dependent on the number of stages, and
is related to the bandwidth of the polyphase network [21]. The most convenient way
of making a polyphase network is to use 4 x 90° phase shifts, because they can
readily be implemented as an RC combination. Therefore, each polyphase network
consists of one or several stages, which in their turn consist of four RC combinations,
as shown in Fig. 2.8. At a certain frequency and a certain phase difference between
the four input ports, positive frequencies will be passed while negative frequencies
will be suppressed, since they have a different phase relation. The negative frequency
component suppression is at its maximum for ω i = 1 ⁄ R i C i . By cascading several
stages, each with a slightly different ωi, a relatively broadband band stop filter for
negative frequencies is created, with a bandwidth BW and a rejection L, as shown in

R1 R2

C1 C2

Stage 1 Stage 2

Fig. 2.8. An unloaded two-stage polyphase filter.

14 Part I. General Introduction

Positive frequencies Positive frequencies

1 1
Av Av
Negative frequencies L Negative frequencies
BW

f f

a. b.
Fig. 2.9. Schematic polyphase characteristic, a). one stage, b). two
stages.
Fig. 2.9b. One of the problems of polyphase filters is component accuracy related to
processing spread; another problem is loading by subsequent building blocks [21].

2.2.4. SUBSAMPLING RECEIVER

Since most of the receive bands in communication systems are narrowband, the prin-
ciple of subsampling can be used [22], [23], i.e., an RF signal, with a carrier fre-
quency fc, is sampled with a much lower frequency fs. This is illustrated in Fig. 2.10.
In the case of ideal sampling, the bandlimited RF signal at the carrier frequency
fc is multiplied with an impulse train in the frequency domain. The result of ideal
sampling is shown in Fig. 2.10c, where both positive and negative frequency compo-
nents are shown on the same frequency axis. The term subsampling is used when the
sampling frequency fs is substantially lower than the highest frequency component in
the sampled signal. If the sampling rate is higher than twice the bandwidth, BW, of
the RF signal, the Nyquist criterion may still be met. More precise requirements are
dependent on the bandwidth of the RF signal and its exact frequency location [24],
[25].
After sampling the RF signal, filtering can be used to select the desired fre-
quency component, which generally is the baseband component. In Fig. 2.11 a sub-

Psample
A A downconverted to first
Nyquist band
Ao A0/Ts
f F=f*Ts
fs fc fs fc f 1/2 1 3/2
a. b. c.

Fig. 2.10. Principle of subsampling: a). The RF input signal, where fc

>> fs, b). Ideal sampling pulse train, c). Discrete-time signal after
ideal sampling.
Chapter 2 Receivers for Mobile Handsets 15

RF BPF IRF LPF

LNA ADC DSP

LO

Fig. 2.11. A subsampling receiver architecture.

sampling receiver architecture is shown. A sample-and-hold (SH) downconversion

circuit can perform both the sampling and selection of the baseband component [22],
[23], which is otherwise done inside the A/D converter. The sampled signal is
directly converted by the ADC. The receiver architecture is quite simple in compari-
son to for instance a heterodyne receiver.
An advantage of the subsampling downconverter, compared to for instance the
heterodyne downconverter, is that the LO operates at a lower frequency, which with
equal power consumption would allow for a better phase noise performance. How-
ever, it can be shown [26] that the single side-band noise power density to carrier
ratio, L(∆f), of the sampled signal and the LO (or clock) signal are related by:
fc 2
L signal ( ∆f ) = L LO ( ∆f ) ×  ----- (2.1)
 f s

where ∆f is the frequency offset from the RF carrier frequency fc. It is then obvious
that for large subsampling ratios fc/fs, the clock must have a very good phase noise
performance. Since the thermal phase noise is dependent on the square of the oscilla-
tion frequency fLO [27], a similar VCO power consumption will be needed for a sim-
ilar overall phase noise performance. This advantage of the lower fLO is thus nulled.
Note that at larger frequency offsets the phase noise is determined by the relation of
the oscillator output power and its noise floor and by the noise of any additional cir-
cuitry between the oscillator and the sampling switch, such as a clock driver [28]. It
can therefore be expected that for applications which require good phase noise per-
formance at larger frequency offsets, e.g receivers with stringent blocking require-
ments, the subsampling ratio fc/fs must be kept low.
The major disadvantage of the subsampling mixer is that noise and interfering
signals that reach the mixer input, will be aliased to the baseband as well [24]. This
results in a fundamentally higher noise figure for the subsampling mixer compared to
for instance a Gilbert-cell based mixer, unless the sampling frequency is in the same
order of magnitude as the designed analog bandwidth. To reduce the effect of the
noise, a pre-select filter can be used [17].
16 Part I. General Introduction

2.3. RECEIVER REQUIREMENTS

The system parameters used in the various communication system specifications
(e.g. [7], [8] and [9]) influence the requirements on the front-end building blocks.
Before describing these relations the total receiver noise figure and linearity is linked
to the noise figure and linearity of the individual blocks in the signal path.

2.3.1. TOTAL RECEIVER NOISE FIGURE AND IIP3

The description of noise and linearity performance in terms of the total noise figure
(NF) and i-th order input related intercept point, or IIPi, of a receiver is general and
widely used. Fig. 2.12 shows a system consisting of a chain of m building blocks,
each with a certain available power gain Api, a voltage gain Avi, a noise factor Fi and
an input related 3rd order intercept point IIP3,i.
According to Friis’ equation [29] the total noise figure of this chain can be
expressed as:
N F tot = 10 log F tot [dB] (2.2)

with the noise factor Ftot as

F2 – 1 Fm – 1
F tot = 1 + ( F 1 – 1 ) + ---------------- + … + ------------------------------------------- (2.3)
A p1 A p1 … A p ( m – 1 )

If the input- and output impedance of each block are matched, then Av [dB] is
equal to Ap [dB], taking A v [ dB ] = 20 log V out ⁄ V in and A p [ dB ] = 10 log P out ⁄ P in .
From the above equation it can be seen that when looking at the noise at the input,
the noise of each building block is divided by the gain of preceding blocks. There-
fore, it is crucial to have an amplifier contributing little noise, i.e. a low noise ampli-
fier (LNA), as a first building block. Generally in CMOS integrated circuits the input
and output impedances of building blocks are not matched, so that an error is made
in the total noise figure calculation if Friis’ equation is used. This error can be as
large as several dB. Therefore, it is preferred to consider the integrated part of the

Av1 Av2 Av3 Avm

in out
Ap1 Ap2 Ap3 Apm

IIP3,1 IIP3,2 IIP3,3 IIP3,m

F1 F2 F3 Fm

Fig. 2.12. Representation of a system as consisting of m building

blocks.
Chapter 2 Receivers for Mobile Handsets 17

receiver as a single unit, where the noise sources can be transferred to the input to
calculate the equivalent voltage and current noise spectral density based on circuit
analysis [29]. In chapter 4 the physical mechanisms of noise in a MOSFET will be
described. For noise in receiver building blocks such as LNAs and mixers see [6],
[30], [1].
The input-related 3rd order intercept point IIP3 is defined as the input amplitude
A0 of two input tones ∆ω apart, for which the output third order intermodulation
product has the same magnitude as the fundamental output tones. Using simple alge-
bra it can be shown that the third order intermodulation product increases with A03,
which in dB is shown in Fig. 2.13. Thus, the slope for the fundamental is equal to 1,
while the slope for the 3rd order intermodulation product is equal to 3. However, only
at low amplitudes the slopes of the fundamental and intermodulation product may be
in accordance with the theory. In real circuits this approximation will not hold since
the gain will be compressed and thus the slope of the fundamental will be less than 1
before the intercept point is reached. Moreover, the slope of the 3rd order intermodu-
lation curve may deviate from 3 due to the influence of higher-order harmonics. For
a more detailed analysis see [6].
From the plot one can find two ways to extract the IIP3:
• Plotting the fundamental and the third-order intermodulation product at low
amplitudes and extrapolate to the point where the two lines cross.
• A ‘short-cut’ method based on the slopes of 1 and 3: applying one two-tone input
∆P
signal and using II P 3 = ------- + P in . Of course this input signal must be chosen
2
with care.

If the IIP3 of each block in the receiver chain is known, the total IIP3 can be cal-
culated as:

Pout
[dB]

∆P

Pin IIP3 Pi [dB]

Fig. 2.13. The fundamental and 3rd order output signal for a non-lin-
ear block.
18 Part I. General Introduction

2 2 2
Av 1 Av 1 ⋅ A
1 1 v2
2
-+…
-------------------------2- = ---------------------2- + ---------------------2- + --------------------------- (2.4)
( II P 3, tot ) ( IIP 3, 1 ) ( IIP 3, 2 ) ( IIP 3, 3 )

where Avi is the voltage gain of block i (not in dB). For a receiver with a BPF, LNA,
IRF, a mixer and some IF blocks (see Fig. 2.14), this leads to:
2 2 2 2 2
1 2  1 A vLNA ⋅ A vIRF A vLNA ⋅ A vIRF ⋅ A vmixer 
-------------------------2- = A BPF ⋅  ----------------------------2- + -------------------------------------- + - + …
--------------------------------------------------------------
( II P 3, tot )  ( IIP 3, LNA ) ( IIP 3, mixer )
2
( IIP 3, IFblock )
2


(2.5)
where it is assumed that the filters are perfectly linear. Under the assumption that Avi
and Api behave similarly, it can be seen from Eq. 2.3 and Eq. 2.4 that in order to opti-
mize both the noise performance and the linearity performance of a receiver, a trade-
off must be sought for the distribution of the gain. In other words, if most of the gain
is designed to be in the first few blocks of the chain, the noise performance is
improved while the linearity performance lags. If most of the gain is put in the last
few stages, the linearity performance is improved while the noise performance is
degraded.

2.3.2. SYSTEM SPECIFICATIONS VS. RECEIVER REQUIREMENTS

In this section the GSM system is used as an example to illustrate the relation
between system specifications and receiver requirements such as noise figure and
IIPi. Other standards such as Bluetooth [8] and UMTS [9], [31], [32] have similar
specifications but different values.
A GSM mobile receiver must, under various specified test conditions such as the
presence of blocking signals, maintain a maximum BER of 10-4 [7] 1. In Fig. 2.15
and Fig. 2.16, the GSM blocking requirements are visualized. For the in-band block-
ing signals the offset relative to the carrier frequency fc of the desired signal is given,
while for the out-of-band blocking signals the absolute frequencies are used. The
blocking requirements provide the worst-case test conditions under which the GSM

BPF IRF Mixer

RF LNA IFblock
IF

LO
ABPF AvLNA AvIRF Avmixer
Fig. 2.14. A possible receiver front-end architecture.

1. For Bluetooth and UMTS this is 10-3 [8], [9].

Chapter 2 Receivers for Mobile Handsets 19

0 0
GSM system

Interfering Level [dBm]

Receive Band
-23 935-960 MHz -23

-33 -33

-43 -43

out of band -99

out of band

fc

fc+0.6

fc+1.6
fc-1.6

980
fc+3
fc-0.6

960
Input frequency, MHz
935
915

fc-3

Fig. 2.15. In-band and out-of-band blocking levels for GSM.

receiver has to operate properly. The blocking signals are compared to a small
desired signal of -99 dBm, while the co-channel and adjacent-channel interferers are
compared to a desired signal of -82 dBm, according to the GSM test specifications
[7].
The blocking signals can disturb the desired signal in a number of ways, such as
through intermodulation, de-sensitization and reciprocal mixing. In-band blocking
signals mainly determine the performance requirements of the frequency synthesizer
and the channel-select filter, while out-of-band blocking levels mainly determine the
band pass filter (BPF, or pre-select-filter) requirements at the input (see Fig. 2.1).

Desensitizing
One of the problems in existing circuits is gain compression, i.e. a reduction of the
gain for large input signals. Due to non-linearities, higher order harmonic compo-
nents exist which become more prominent for large signals (see Fig. 2.17).
For RF circuits a 1-dB compression point is usually characterized, i.e., the input
power for which the gain is reduced by 1 dB. From algebraic analysis it follows that
a fundamental relation exists between the 1-dB compression point and the IIP3 (in
dBm) [6]:

-41
Interfering level [dBm]

-73
-82
fc+0.2

Input freq. [MHz]

fc+0.4
fc

co-channel: -91

Fig. 2.16. Co-channel and adjacent channel blocking signals

20 Part I. General Introduction

Pout ideal

gain
compression

Pin

Fig. 2.17. Gain compression for large input signals.

II P 3 ≈ P –1dB + 10dB (2.6)

so that if the compression point is known, the IIP3 can be estimated. Deviation from
this relation is due to the influence of higher-order odd harmonics.
If a small desired signal is accompanied by a large blocking signal, the blocking
signal can cause gain compression for the desired signal, due to the non-linearity of a
building block or element. This is called desensitization of the circuit. The noise fig-
ure will deteriorate and small signals can no longer be detected, and thus the sensi-
tivity is reduced.

Harmonics and Intermodulation

Another effect of non-linearities in building blocks is the generation of spurious
components. If a single input signal is fed into a non-linear system, higher order spu-
rious signals (harmonics) will be seen at the output besides the fundamental compo-
nent (see Fig. 2.20). The spurious signals can corrupt the desired signal at any stage
in the receiver. This is highly dependent on receiver architecture and building block
specifications, as will be shown in par. 2.4.

In Paper III an analysis is made of internal spurious signals, applied to a GSM

receiver.

finterf Gaindes ideal

P
blocker

gain
compression

fRF f
Pblocker
a. b.
Fig. 2.18. Desensitizing due to a large blocking signal, a). input, b).
gain compression for the desired signal due to the blocking signal.
Chapter 2 Receivers for Mobile Handsets 21

Single input signal Output signals

P
P non-linear
element

in out

f
fin fout f

Fig. 2.20. Non-linear system with a single tone input signal.

Intermodulation is defined as the generation of spurious components when two
or more signals are fed into a non-linear building block or element (see Fig. 2.19).
The principle of intermodulation is valid both for a complete receiver and for a build-
ing block such as an LNA or a mixer.
The third-order intermodulation is generally considered to be the most harmful,
because the resulting spurious components of two large blocking signals at f1 and f2
can fall directly on the desired signal, e.g. if 2 f 1 – f 2 = f c . This situation occurs for
all odd higher-order intermodulation, but the third-order non-linearity of an element
is generally the most troublesome. Even-order non-linearity on the other hand results
in intermodulation products at DC or low frequencies. These products may be trou-
blesome in a low-IF or direct conversion receiver.
Only one intermodulation test is specified in the GSM specifications [7]: the
intermodulation product of a sinusoidal signal of -49 dBm at ± 800 kHz and a modu-
lated -49 dBm signal at ± 1600 kHz from the desired signal 1, is compared to a
desired signal of -99 dBm. In order for the receiver to meet the BER requirement the
intermodulation product must be at least 9 to 12 dB below the desired signal 2. If for
simplicity it is assumed that the two interfering signals are sinusoidal, the GSM
intermodulation specification leads to a total receiver IIP3,tot of:

Output signals (for 3rd. order non-linearity):

Two-tone input signals
2f2+f1
2f1+f2

non-linear
2f2-f1
2f1-f2

element ∆P
∆f
in out
f1 f2 f1 f2 3f1 3f2

Fig. 2.19. Intermodulation in a non-linear element.

1. so that |f1-f2| = 800 kHz and 2f1 - f2 = fc

2. The minimum necessary carrier-to-noise and interference ratio C/(N+I)min is dependent on the
type of GMSK detector that is used [33]. Therefore, various numbers can be found for C/(N+I)min,
ranging from 9 to 12 dB.
22 Part I. General Introduction

∆P ( – 49 + 99 + 12 )
II P 3, tot = ------- + P in = -------------------------------------- – 49 = – 18 [dBm] (2.7)
2 2
where ∆P is the difference in power [dBm] between the fundamental component and
the intermodulation component at the output, as indicated in Fig. 2.19. In this case,
Pin is the power of the interfering signals.
The single intermodulation test may appear to be somewhat superficial, since
larger blocking signals can degrade the performance, while not mentioned in the
GSM intermodulation test requirements. As an example, the GSM blocking spec-
trum could be applied to the intermodulation test for any two interfering signals sat-
isfying f c = 2 f 1 – f 2 . This would increase the IIP3,tot requirement dramatically. For
instance, two interferers of -23 dBm - the largest in-band blocking signals - would
give a minimum IIP3,tot of +21 dBm. If this situation occurs and the desired signal
can not be detected, another channel must be chosen.
For third order intermodulation the difference ∆P between the fundamental
component and the intermodulation product at the output can be calculated using the
IIP3, as was shown in Fig. 2.13:
∆P = 2 ( II P 3 – P in ) = P fund, out – P 3, out (2.8)

where Pin is the input power and Pfund,out and P3,out are the fundamental and third
order output component, respectively. All signal powers are in dBm. More generally,
for kth order intermodulation the following relation is valid:
∆P = ( k – 1 ) ( II P k – P in ) = P fund, out – P k, out (2.9)

For single-tone interferers a definition analog to IIPk may be deduced, namely

the input-related harmonic intercept point Pk,oi:
∆P h = ( k – 1 ) ( P k, oi – P in ) = P fund, out – P k, out . (2.10)

The relationship between IIPk and Pk,oi is given by

P k, oi = II P k + 10 log k . (2.11)

Since it is more customary to characterize a building block’s linearity through IIPk,

this will be used hereafter, even when only single-tone interferers are considered.

Receiver Noise Figure

The noise figure of a receiver determines how much noise it contributes, and is spec-
ified at the input of the receiver. Depending on system specifications such as refer-
ence sensitivity and the minimum necessary carrier- to-noise and interference ratio,
C/(N+I)min, the maximum receiver noise figure may be expressed as
Chapter 2 Receivers for Mobile Handsets 23

signal corrupted
blocker
∆f
phase noise
fIF
∆f
∆f

f
fLO fRF f
fIF

Fig. 2.21. Reciprocal mixing due to phase noise in the LO signal.

N F RX < P des – L bpf – C ⁄ ( N + I ) min + 174dBm – 10 log BW . (2.12)

Here Pdes is the power of the desired signal in dBm, C/(N+I)min is the minimum nec-
essary carrier-to-noise+interference ratio in dB, Lbpf is the insertion loss of the band-
pass filter in dB and BW is the bandwidth of the signal in Hz. Note that this is the
noise figure for the receiver excluding the BPF at the input. Using
C/(N+I)min = 9 - 12 dB
BW = 200 kHz
Lbpf = 2 dB
Pdes = reference sensitivity (-102 dBm)
Eq. 2.12 gives
N F RX < 5 [dB]. (2.13)

Phase Noise Requirements

The mechanism that causes in-channel interference due to phase noise is called
reciprocal mixing. The blocking signal is mixed with the LO signal including phase
noise, and the tail of the resulting unwanted signal corrupts the desired signal at IF
(see Fig. 2.21).
From the blocking and adjacent channel specifications the phase noise require-
ments for the LO signal of the receiver can be deduced as
L ( ∆f ) = P des – P int ( ∆f ) – C ⁄ ( N + I ) min – 10 log ( BW ) [dBc/Hz] (2.14)

where L(∆f) is given in [dBc/Hz] and is defined relative to the power of the carrier,
i.e. the LO signal power. Furthermore, ∆f is the offset frequency from the carrier and
Pint is the power (in dBm) of the blocker which is located at ∆f from the desired sig-
nal. In the derivation of the above equation it was assumed that the phase noise has a
constant power spectral density over the bandwidth BW.
24 Part I. General Introduction

The blocking specifications as a function of the offset frequency as shown in

Fig. 2.15, and the minimum desired signal Pdes being -99 dBm, result in the follow-
ing table of phase noise requirements.
TABLE 1. GSM RECEIVER PHASE NOISE REQUIREMENTS

∆f [MHz] 0.2 0.4 0.6 - 0.8 0.8 - 1.6 1.6 - 3 >3 out-of-band

L [dBc/Hz] -74 -106 -121 -121 -131 -141 -164 a

a. Assuming no filter is present at the receiver input

The requirements for ∆f > 3 MHz and out-of-band are considered to be the most crit-
ical for a fully integrated CMOS VCO/frequency synthesizer [34].

Image Rejection
Image rejection can be seen as a special case of blocking signals, since the strength
of the image signal is given by the blocking requirements. As was presented in para-
graph 2.2.1, the image is located at 2ωIF from the desired signal at ωRF (see Fig.
2.3).
From the GSM specifications it follows that an image rejection of 110 dB is nec-
essary, assuming that the image frequency falls out of band, i.e. an IF of more than
10 MHz. Several measures can be taken to achieve this, besides using a highly selec-
tive band pass filter (BPF) preceding the LNA. Some alternatives, such as image
reject mixing, were discussed in chapter 2. Another alternative strategy is to use the
so-called ‘spurious response frequencies’ [7]. These are defined in the GSM specifi-
cations as exceptions for the blocking signals, with a non-predefined frequency, so
that the blocking requirement decreases from 110 dB to approximately 80 dB. These
exceptions can also be used as a solution for problems with the internal spurious
response (see section 2.4). However, since the number of exceptions is limited, uti-
lizing them for the aforementioned two problem areas may conflict.

Cross Modulation
If two signals are fed into a non-linear system, amplitude variations of one signal can
appear in the other signal. The effect of this cross-modulation is similar to the effect
of desensitization. The amplitude of the desired signal is modulated, possibly lead-
ing to this signal being blocked. Again, this is determined by the system non-linear-
ity in combination with the blocking specifications.
Chapter 2 Receivers for Mobile Handsets 25

The influence of system specifications on design parameters is summarized in

table 2.
TABLE 2. SYSTEM SPECIFICATIONS VS. RECEIVER DESIGN ISSUES

Internal Spurious Response

Cross Modulation
Image Rejection

Intercept Point
De-sensitizing

Noise Figure

Phase Noise
Blocking characteristics X X X X X
Adjacent channel signals X
Intermodulation characteristics X
Reference sensitivity level X X X X X X X
Bit Error Rate X X X X X X X

2.4. FREQUENCY PLANNING

Receiver frequency planning related to intermodulation problems [20], [12], [13],
[35], [36], [37] is analyzed in this section, taking into account the GSM in-band and
out-of-band blocking specifications as shown in Fig. 2.15. The analysis is focused on
the front-end of a heterodyne receiver, and a relatively high fIF > 10 MHz is
assumed. The analysis relates building block design parameters to both communica-
tion system specifications and predefined or predictable receiver parameters. The
impact of the use of filters in a receiver and the consequences for the frequency plan-
ning of the receiver are clearly demonstrated.

2.4.1. A FRONT-END MODEL

A typical receiver front-end was depicted in Fig. 2.14. The IF block may consist of a
programmable gain amplifier (PGA), an IF filter and a second downconversion
mixer, followed by a channel select filter and an ADC, but is not specified further at
this point. Three main harmonics problem areas can be defined in the front-end:
• Non-linearity in the LNA. This causes different frequency components to occur at
the output of the LNA, at fin, 2fin, 3fin etc. where fin can be an interfering signal or
a desired signal.
26 Part I. General Introduction

(kth order) (mth order)

finterf =(nfLO±fIF/m)/k nfLO±fIF/m ±fIF/m
LNA IFblock

nfLO

Fig. 2.22. Generation and mixing of harmonics in a receiver front-

end.
• Non-idealities in the frequency synthesizer (such as harmonics of fLO or of the ref-
erence frequency). Harmonics of fLO appear at 2fLO, 3fLO, 4fLO etc. The even-
order LO harmonics are assumed to be 40 dB below the fundamental due to
imperfections in the differential LO path. A square-wave differential LO has odd-
order harmonic components with amplitudes of 1/3, 1/5, etc. (i.e. 10 dB, 14 dB
lower harmonic output signal). The reference frequency from a crystal oscillator is
ignored at this time.
• Non-linearity in the IF block. Mixer output signals at fmix can generate harmonics
at 2fmix, 3fmix, etc. The non-linearity of the mixer has been incorporated in the ‘IF
block’, i.e., it is assumed that a signal is first downconverted after which non-lin-
earity occurs. This is a simplification and an issue to be investigated further.

The above described sources of non-linearity are illustrated in Fig. 2.22. If the fol-
lowing equation is satisfied, the interferer falls on the desired signal [13]:
f interf = ( n f LO ± f IF ⁄ m ) ⁄ k or kf interf = n f LO ± f IF ⁄ m (2.15)

where finterf is the frequency of an interfering signal, and k, m and n are integers rep-
resenting the non-linearity of the LNA, the IF block and the LO signal, respectively.
In Fig. 2.23 a more extended model of the basic front-end is shown. The LNA
input matching network, causing attenuation, has been incorporated in the term

LO (Ln)
LNA IF block
BPF IRF

Mixer
GLNA Gmixer IIPm,IF
LBPF IIPk,LNA

Attbpf(∆f) Attlna(∆f)
Fig. 2.23. Block schematic of a receiver front-end incorporating gain,
attenuation and non-linearity of the building blocks.
Chapter 2 Receivers for Mobile Handsets 27

Attbpf(∆f), while the attenuation caused by the output tuning network is included in
the term Attlna(∆f). The amount of LNA input attenuation is dependent on the type of
LNA; for a Common-Source amplifier the attenuation may be a few dB, while for a
Common-Gate amplifier with its broadband input matching no significant attenua-
tion will be seen. The loss of the IRF is incorporated in the mixer gain, Gmixer,dB. Ln
represents the relative loss of the nth LO harmonic compared to the LO fundamental.
For each combination of n, k and m the parameters indicated in this block schematic
will be weighted differently, as will be shown in the next section.

2.4.2. MAIN MECHANISMS FOR DISTURBANCE FROM SPURIOUS SIGNALS

Different mechanisms can be distinguished for different combinations of n, k and m
as defined in the previous section.
• Mechanism 1: n>1, k>1, m=1 or kf interf = n f LO ± f IF
A harmonic of the interferer is downconverted with a harmonic of the LO signal.
This mechanism depends on the linearity of the LNA, the suppression by various
filters and the non-ideality of the frequency synthesizer.
• Mechanism 2: n>1, k=1, m=1 or f interf = n f LO ± f IF
An interferer is downconverted with a harmonic of the LO signal. This mechanism
is dependent on the frequency synthesizer non-ideality and the suppression by the
filters before the mixer.
• Mechanism 3: k=n=1, m>1 or f interf = f LO ± f IF ⁄ m
The non-linearity of the blocks after the mixer causes the downconverted inter-
ferer to fall on fIF. This mechanism depends on the suppression by the filters and
the linearity of the IFblock.
• Mechanism 4: k>1 (n, m arbitrary) or kf interf = f RF
An interferer located at a subharmonic of fRF produces a component at fRF before
mixing. This mechanism is only dependent on the non-linearity of the LNA and
suppression by the filter before the LNA.

Various combinations of mechanisms can occur as well. However, the effect of these
combinations will be negligible in practically every case, since with every mecha-
nism the magnitude of the disturbing signal component is reduced. Therefore the
analysis is limited to the aforementioned cases.
If n=k=m=1 in Eq. 2.15, it follows that f interf = f LO ± f IF and the interferer is
either a co-channel interferer or an image signal. These issues were discussed in the
previous paragraph. Another special case is the so-called half-IF problem [6]. An
interfering signal in between fRF and fLO, i.e. f interf = ( f LO + f RF ) ⁄ 2 (see Fig. 2.24)
28 Part I. General Introduction

interferer
P

fIF

fLO fRF f

Fig. 2.24. Illustration of the ‘half-IF’ problem.

may fall on fIF, by means of mechanism 1 (n=k=2, m=1) or mechanism 3 (n=k=1,

m=2).

Mechanism 1: Mixing of LO Harmonics with Interferer Harmonics

For mechanism 1 the intermodulation products originating from the LNA non-linear-
ity are multiplied with LO harmonics. The products of this multiplication can fall
directly on fIF. Eq. 2.15 becomes kf interf = n f LO ± f IF (m=1). In order not to
degrade the performance these terms must have less power than the desired signal by
a margin of C/(N+I)min, the carrier-to-noise and interference ratio:
P inter f , IF < P des, IF – C ⁄ ( N + I ) min (2.16)

The desired signal at the output of the mixer is given by:

P des, IF = P des – L BPF + G LNA + G mixer (2.17)

where GLNA and Gmixer are the power gain of LNA and mixer, respectively. The
interfering signal, downconverted with mechanism 1 for k=3, is then given by:
P interf ( IF ) = 3P interf – 3L BPF – 3 Att bpf ( ∆f ) + G ln a – 2IIP 3, LNA
– Att ln a ( ∆ f 3 ) – L n + G mixer – 10dB
(2.18)
where
Pinterf = power of interfering signal
Lbpf = insertion loss of the band pass filter in the GSM receive band
Attbpf(∆f) = attenuation of the BPF (frequency dependent), including the attenuation of
the LNA input matching network

P
fLO 3fLO 5fLO

fIF
fIF

finterf kfinterf f

Fig. 2.25. Illustration of mechanism 1.

Chapter 2 Receivers for Mobile Handsets 29

∆f = distance of interferer to the GSM receive band (935 - 960 MHz)

Attlna(∆f3) = attenuation of the LNA output + image reject filter between LNA and
mixer (frequency dependent)
∆f3 = distance of 3rd order harmonic at LNA output to the GSM receive band
Ln = relative loss of the nth harmonic of the frequency synthesizer relative to the funda-
mental
Pdes = smallest desired signal (-99 dBm)

More generally, for kth order intermodulation the interfering signal at the mixer out-
put is
P inter f , IF = k ( P int erf – L bpf – Att bpf ( ∆f ) ) + G lna – ( k – 1 ) ( II P k + 10 log k )
(2.19)
– Att lna ( ∆f k ) – L n + G mixer

An expression can now be derived for mechanism 1 giving a criterion for IIPk of
the LNA:
k k 1
II P k, LNA > -----------P interf – L bpf – ----------- Att bpf ( ∆f ) – ----------- ( Att lna ( ∆ f k ) + L n )
k–1 k–1 k–1

– 10 log ( k ) – -----------  P des – ------------------ 

1 C
k – 1 ( N + I ) min (2.20)
where C/(N+I)min is 9-12 dB for GSM. For a single-ended LNA, IIP2 and IIP3 are
generally considered to be the most critical.
If the circuit parameters such as IIPk are known, Eq. 2.20 can be used to deter-
mine the required BPF attenuation by rearranging it as:

k–1 1
Att bpf ( ∆f ) > P interf – -----------L – --- ( Att lna ( ∆ f k ) + L n ) (2.21)
k bpf k
– ----------- ( II P k + 10 log k ) – ---  P des – ------------------ 
k–1 1 C
k k  ( N + I ) min
If all circuit parameters including the BPF attenuation are known, the distance in fre-
quency ∆f can be considered to be the unknown variable. The desired signal and
interferer are compared after downconversion, and both the attenuation of different
building blocks and the interferer specifications are frequency dependent. Thus, it
depends on the choice of IF whether the above requirements will be met. This may
be seen from Fig. 2.25; if fIF is smaller, 5fLO will lie at a higher frequency, and more-
over, the frequency of a possibly disturbing harmonic 3finterf will lie closer to the
new 5fLO since fIF is smaller, resulting in a higher frequency for 3finterf. Thus, finterf
will be higher as well, and this interfering signal will most likely have undergone a
larger attenuation from the band pass filter.
30 Part I. General Introduction

interferer
3fLO
P

fIF fIF

f
fLO fRF

Fig. 2.26. Mechanism 2 illustrated.

This is elaborated further in Paper III.

Mechanism 2: Mixing of an Interferer with an LO Harmonic

An interferer, located at a relatively high frequency, may be downconverted with a
harmonic of the LO, and appear at fIF, according to f interf = n f LO ± f IF . This mech-
anism is independent of LNA or mixer non-linearity, because the fundamental of the
interfering signal is involved. Therefore, a slightly different expression follows:
C
P interf – Att bpf ( ∆f ) – Att lna ( ∆f ) – L n < P des – ------------------ (2.22)
( N + I ) min
or
C
L n > P interf – Att bpf ( ∆f ) – Att lna ( ∆f ) – P des + ------------------ . (2.23)
( N + I ) min
The ability to deal with these interferers is dependent on the ideality of the fre-
quency synthesizer and the attenuation of different parts (such as filters). With this
mechanism ∆f will be large, resulting in a large attenuation.

Mechanism 3: Harmonics of Downconverted Interferers

An interferer that is downconverted to fIF/m, suffers from mth-order non-linearity
after the mixer and produces a component at fIF. Thus, k=n=1, m>1. The most criti-
cal interferer is situated in between fLO and fRF, closest to fLO. An interferer located
at the other side of fLO could downconvert to the same f IF ⁄ m , but this interferer
interferer

P
fIF/3
2nd 3rd
fIF

fLO f
fIF fRF

Fig. 2.27. Schematic representation of mechanism 3.

Chapter 2 Receivers for Mobile Handsets 31

will be subject to more suppression from the filters since the distance in frequency to
the RF passband is larger.
For this mechanism a similar expression as for mechanism 1 has been derived,
expressing the required IIPm,IF of the IF block in other front-end parameters:
m m m
II P m, IF > ------------- P interf – L bpf – ------------- Att bpf ( ∆f ) – ------------- Att lna ( ∆f )
m–1 m–1 m–1
(2.24)
– 10 log ( m ) – -------------  P des – ------------------  + G mixer + G LNA
1 C
m – 1 ( N + I ) min
The IF blocks generally are fully differential (see for example [10]) so that even-
order non-linearities are cancelled to the first order. Therefore, IIP2,IF will presum-
ably be 20 dB higher than IIP3,IF and thus the case for m=2 will have considerably
less impact.

Mechanism 4: An Interferer Located at a Subharmonic of the Desired Signal

This mechanism describes the case when the interferer is located at a subharmonic of
the desired signal, and a harmonic appears at fRF before the mixer (see Fig. 2.28). No
downconversion is involved, and only the non-linearity of the LNA is of importance.
For this mechanism it has been derived that:
k k
II P k, LNA > -----------P interf – L bpf – ----------- Att bpf ( ∆f )
k–1 k–1
(2.25)
– 10 log ( k ) – -----------  P des – ------------------ 
1 C
k–1  ( N + I ) min
∆f will be larger for this mechanism than for mechanism 1 or 3, resulting in a larger
attenuation. Since in most cases a BPF is used after the antenna, this mechanism has
very limited impact.

Practical calculation examples including representative BPF and IRF and building
block characteristics were presented in [1] and in Paper III.
interferer

P
2nd 3rd

fRF f

Fig. 2.28. Mechanism 4 depicted.

32 Part I. General Introduction

Summary
The mechanisms discussed above lead to distortion of the desired signal at different
points in the receiver. In some cases, such as mechanism 1 and 3, this can be allevi-
ated by the choice of intermediate frequency, IF. This determines the LO frequency
as well as the operating frequency of the IF blocks. The filter attenuation characteris-
tics have a large impact on the resulting IF frequency ranges, as have the building
block non-linearities. Mechanism 2 may be the most critical one, since it is only
dependent on filter attenuation and LO harmonics. The choice of a specific IF does
not have any significant effect on this mechanism, although it is slightly better to
choose fLO > fRF than vice versa.
If an image-reject filter is used, then mechanism 1 and 2 will hardly play any
role and mechanism 4 will not be that severe. However, due to other considerations,
such as reduction of the number of external components, this is not the most desir-
able solution. For GSM, a possible solution may be to use the blocking exceptions
(‘spurious response frequencies’ with an input level of -43 dBm [7]), where the
exceptions can be redefined for each GSM channel.

In Paper III the above theory is described and applied to a GSM receiver, supported
by measurement results.
CHAPTER 3

TRANSMITTERS FOR MOBILE HANDSETS

3.1. INTRODUCTION
In this chapter an overview is given of the most common transmitter architectures as
well as some more unusual ones. It is followed by a brief discussion on the impact of
communication system specifications on transmitter requirements, as well as trans-
ceiver disturbance issues and frequency planning. Special attention is given to power
amplifiers, the most challenging building block of an integrated CMOS transmitter.

3.2. TRANSMITTER ARCHITECTURES

The main task of a transmitter is to submit a signal to the antenna at a certain fre-
quency, with a certain power and a certain modulation. Moreover, the signal should
not disturb communication in other bands or channels too much. These requirements
are set in the communication system specifications. As in receiver design, a balance
must be found between performance and issues such as complexity, number of exter-
nal components and power consumption.

3.2.1. DIRECT CONVERSION TRANSMITTERS

A direct conversion transmitter has a single upconversion stage (see Fig. 3.1 and [6]).
The baseband (BB) signal is first modulated, then upconverted to the desired RF fre-
quency by means of a mixer stage driven by an LO signal. The RF signal is then
amplified in the PA to get sufficient output power. A band-pass filter may be used
between the mixer and the PA in order to prevent the LO harmonics from reaching
the antenna. The matching network (MN) between the PA and antenna, which may
be either integrated or off-chip, transforms the impedance of the antenna to an opti-
mum load impedance for the PA. Also, a band-pass filter or duplex filter may be used
between the matching network and the antenna. A duplex filter provides band pass

33
34 Part I. General Introduction

BPF/ RF
BB duplex
fLO
modulator PA MN

LO

VCO 0 fRF f [Hz]

a. b.

Fig. 3.1. A direct conversion transmitter, a). architecture, b). direct

upconversion in the frequency domain.

filtering for both receiver and transmitter, and moreover, it provides isolation
between the two parts.
In most communication systems the baseband signal is double side band and
asymmetrical around 0 Hz, and is therefore modulated to consist of an I- and Q- part,
so-called quadrature modulation. In that case the upconverter generally consists of
two parallel mixers, driven by LO signals with 90° phase difference (quadrature mix-
ers), and an adder, as depicted in Fig. 3.2.
The main advantage of a direct conversion transmitter is its simple structure,
which makes it suitable for integration. A disadvantage of this architecture is that the
PA output has the same frequency as the VCO (LO). Especially in cases when the
two building blocks are parts of a single-chip transmitter and if the isolation between
the VCO and PA is not perfect, the PA signal may disturb the VCO signal, a mecha-
nism called injection pulling or injection locking (see par. 3.6, [6], [38] and [39]).
This problem is more severe the closer the two signals are in frequency. Strategies to
alleviate this problem are discussed in sections 3.2.2 and 3.6.

3.2.2. TWO-STEP TRANSMITTERS

In analogy to heterodyne receivers, also in transmitters an architecture with two
mixer stages may be used (see Fig. 3.3), called a two-step transmitter [6]. The modu-
lated baseband signal is first upconverted to a frequency ωIF, where

BBI
LOI BPF/ RF
BB
mod. VCO PA MN duplex

LOQ
BBQ

Fig. 3.2. A direct conversion transmitter with quadrature modulation.

Chapter 3 Transmitters for Mobile Handsets 35

BBI
LO1I BPF BPF BPF/ RF
BB
mod. VCO1 PA MN duplex

LO1Q LO2
BBQ

Fig. 3.3. A two-step transmitter architecture.

ω IF = ω BB + ω LO1 . A band-pass filter is then typically used to suppress IF harmon-

ics. The second mixer stage upconverts the IF signal to the RF frequency:
ω RF = ω LO2 + ω IF . However, a similar signal is created at the image frequency
ω LO2 – ω IF . This signal must be filtered out by the band-pass filter between the sec-
ond mixer and the power amplifier. If ωLO1 is low, these two signals are close to each
other in frequency, and thus a high-quality off-chip BPF may be necessary. Alterna-
tively image-reject mixing may be used in analogy to image rejection in the receiver.
Another problem is LO leakage; the LO signal must be suppressed by filtering or
other means.
An advantage of this architecture is that the PA output is not operating at the
same frequency as any of the VCOs. Moreover, quadrature upconversion and addi-
tion occur at a lower frequency (ωIF instead of ωRF), thus with possibly better I- and
Q matching. Disadvantages are its complexity, the necessity for two LO signals and
the large number of filters.

3.2.3. DIRECT-MODULATION TRANSMITTERS

In some communication systems such as GSM [40], [41] and Bluetooth [42], con-
stant-envelope modulation schemes are used. This allows for so-called direct modu-
lation, i.e., the baseband signal operates on the control voltage of the VCO. The
VCO then generates a modulated RF signal directly, without any need for upconver-
sion mixers. The number of filters may be reduced as well (see Fig. 3.4).
If a frequency synthesizer (FS) is used to stabilize the VCO output frequency,
the direct modulation may be compromised by the feedback loop. Thus, in transmit

VCO
BPF/ RF
BB
mod. PA MN duplex

Fig. 3.4. A direct modulation transmitter architecture.

36 Part I. General Introduction

mode the FS loop must be open. Alternatively the baseband signal can be added
either to the reference signal or in the feedback path, thus employing the feedback
loop to modulate the output signal [40], [43]. In this way the wide-band noise at the
reference input may be suppressed by the FS loop, reducing the need for a duplex fil-
ter so that a simple RF switch may be used instead [40].

3.2.4. HARMONIC TRANSMITTERS

Instead of using the fundamental LO signal and amplifying the resulting fundamen-
tal RF signal, higher-order harmonic signals may be used as the main LO signal. So-
called harmonic mixing has been applied mainly in receivers, where a harmonic of
the LO signal was used to drive the downconversion mixer. This harmonic was gen-
erated by a non-linear circuit, such as an anti-parallel diode pair [44], [45], [46],
[47], or an amplifier [48]. In this architecture the VCO and PA will operate at a dif-
ferent frequency.
Another strategy is to use frequency multiplication in the PA. Since the multipli-
cation occurs in the signal path, this may have a severe impact on the signal content.
If frequency doubling is used in a narrowband FM system, i.e., m ∫ x BB ( t ) dt « 1 , the
input signal is given by x ( t ) = A cos ω c t – Am sin ( ω c t ) ∫ x BB ( t ) dt , where m is the
modulation index, xBB(t) is the baseband signal and ωc is the (angular) frequency of
the carrier signal. The second order output signal may then be written as:

1
x ( t ) ≈ A DC + --- cos ( 2ω c t ) – m sin ( 2ω c t ) ∫ x BB ( t ) dt
2 2
(3.1)
2
Thus, for a narrow-band system the 2nd order harmonic carries the same signal infor-
mation as the fundamental. Frequency doubling in the signal path is possible for FM-
like modulation systems such as frequency shift keying (FSK) and Gaussian mini-
mum shift keying (GMSK, used in GSM [7], DECT and Bluetooth [8]).
If an amplifier is used to generate the higher-order harmonic, then direct modu-
lation may be used as shown in Fig. 3.5; also in this way the PA and VCO operate at
different frequencies. One of the disadvantages is that a harmonic usually is smaller
than the fundamental. A power amplifier with a strong 2nd order component was
described in [49].

VCO
BB fin fout=kfin
mod.

Fig. 3.5. A direct modulation transmitter with frequency multiplica-

tion.
Chapter 3 Transmitters for Mobile Handsets 37

In Paper V a CMOS power amplifier with internal frequency doubling is described.

3.3. TRANSMITTER REQUIREMENTS

Important communication system specifications for the transmitter, such as adjacent
channel leakage power ratio (ACLR), spectral mask requirements, receive band leak-
age and spurious emissions, determine transmitter properties such as noise and lin-
earity, and thus building block parameters such as VCO phase noise and PA noise
and linearity.

3.3.1. TRANSMITTER NOISE AND NON-LINEARITY

Linearity Requirements
Power amplifier (PA) non-linearity largely determines the out-of-band emission of
the transmitter, while non-linearity in other building blocks such as mixers may con-
tribute as well. Like for the total receiver IIP3 presented in par. 2.3.1, the same equa-
tion is valid for the transmitter chain:
2 2 2
Av1 Av2 ⋅ A
1 1 v3
2
-+…
-------------------------2- = ---------------------2- + ---------------------2- + --------------------------- (3.2)
( II P 3, tot ) ( IIP 3, 1 ) ( IIP 3, 2 ) ( IIP 3, 3 )

In case of the transmitter the output related intercept point is of more interest:
2
 Av 1
2
Av 1 ⋅ A
2

1 1  1 v2
- + …
----------------------2- = ------------------------------------------------------------ ---------------------2- + ---------------------2- + ---------------------------
 2 
OI P 3, tot A 2
⋅ A
2
⋅ A
2
⋅ …   ( IIP 3, 1 ) ( IIP 3, 2 ) ( IIP 3, 3 ) 
 v1 v2 v3 
(3.3)
where Avi is the voltage gain and IIPi the input-related 3rd order intercept point of
block i. From this equation it can be seen that the non-linearity of the last block - the
power amplifier - will dominate the transmitter non-linearity. It must be noted that
for highly non-linear amplifiers there is no generally valid relationship between IIP3
and adjacent channel leakage power ratio (ACLR) - the main UMTS transmitter
specification related to linearity [9]. Generally, the PA is characterized by its ACLR,
which should be a few dB below the total required ACLR in order to allow for some
non-linearity in other building blocks.

Output Noise
Transmitter output noise can be described as a composition of thermal noise and
phase noise, where thermal noise determines the noise floor and phase noise causes
38 Part I. General Introduction

TX signal
BB

PA thermal noise
phase
noise
VCO duplex

fc f

a. b.
Fig. 3.6. Transmitter, a). common architecture, b). the output signal
spectrum including noise.
additional noise around the output signal carrier frequency (see Fig. 3.6). Thermal
noise is constant in the frequency domain (so-called ’white noise’), while phase
noise originates from the VCO and forms ’skirts’ around the carrier frequency hav-
ing a certain frequency dependency [29], [27].
The transmitter output noise requirements are mainly bound by emission
requirements, but also by the receiver noise floor, in case of a non-TDD system such
as UMTS, where transmitting and receiving occur simultaneously. Taking UMTS as
an example [9], assuming that no duplex filter is present and that no other noise or
distortion is seen at the receiver input, the output noise power requirement for the
transmitter becomes -167 dBm/Hz. With a duplex TX-to-RX isolation of 50 dB this
will be -117 dBm/Hz. Using the out-of-band spurious emission specifications, the
toughest requirement (from the frequency range 935-960 MHz) becomes -129 dBm/
Hz without duplex filter. A duplex filter attenuation of 40 dB in this frequency band
eases this requirement to -89 dBm/Hz. From the above figures it can be seen that a
duplex filter is hard to avoid for UMTS. In paragraph 3.3.3 more calculations are
presented.

3.3.2. SYSTEM SPECIFICATIONS VS. TRANSMITTER REQUIREMENTS

Adjacent channel / spectral mask requirements
In constant-envelope systems such as GSM the transmitter power emission is gener-
ally limited by the spectral emission mask requirements (see for instance [7], [40]),
while in variable-envelope systems such as UMTS the adjacent channel leakage
power ratio (ACLR, see [9]) is given as well.
The ACLR is simply defined as
P adj
ACLR = ------------------
- (3.4)
P channel
Chapter 3 Transmitters for Mobile Handsets 39

output
signal TX output signal
P
spectral
ACLR emission
[dBm] mask
3rd order
5th order AC1
AC2

f f
a. b.

Fig. 3.7. a). Adjacent Channel Leakage Power Ratio illustration, b).
spectral emission mask illustration.
where Pchannel is the power in a channel of a certain bandwidth according to the
communication system specifications, and Padj is the power in one of the adjacent
channels, as indicated in Fig. 3.7a. It is a measure that comprehends all distortion
appearing in the adjacent channel. Intermodulation contributes heavily to ACLR.
Thus, when increasing the signal power, the power in the two adjacent channels
(AC1 and AC2) will increase faster than that in the desired channel, in accordance
with Fig. 2.13, and the ACLR decreases for increasing output power. This is also
called ’spectral regrowth’. In system specifications, ACLR is therefore specified for a
certain output power.
Spectral mask requirements limit the transmitter output signal spectrum close to
the desired signal, as is illustrated in Fig. 3.7b. Both the ACLR and the spectral emis-
sion mask have an impact on the transmitter noise and linearity requirements. Calcu-
lation examples will be presented in section 3.3.3.

Out-of-band emissions
Besides limited disturbance to adjacent channels, the disturbance from the transmit-
ter to other communication systems must be limited as well. This is ensured by
means of the out-of-band emission requirements. For instance, UMTS has emission
requirements for the GSM and DCS bands [9].
A mobile user may be disturbed by a neighboring handset, for instance when
handset 1 is transmitting with high power, and handset 2 tries to receive a small sig-
nal at the same time. Since in some systems the two handsets may operate indepen-
dently, the “send” time slot of handset 1 may coincide with the “receive” time slot of
handset 2, even for a TDD system. This is illustrated in Fig. 3.8.
Because of the separation in frequency between the transmit and receive bands
for GSM, this mechanism is determining the far-out phase noise requirement. In the
Bluetooth system, communication does not pass through a base station. Instead each
40 Part I. General Introduction

handset 1 LNA TX signal

PA Pout

∆f
Duplexer
handset 2 fTX fRX f

a. b.
Fig. 3.8. a). The transmitted signal of handset 1 is disturbing the
received signal of handset 2, b). Frequency domain illustration.
device can be a master or a slave in a point-to-point network. Transmitting and
receiving occur in the same frequency band, and thus it is a non-FDD system.
In analogy to the receiver phase noise requirements, which are largely deter-
mined by blocking specifications, these out-of-band emission specifications play a
large role for transmitter phase noise specifications.

Transmitter Feedthrough
Another problem of transceiver design is transmitter feedthrough: a high-power TX
signal leaks through the duplexer and disturbs the signal to be received by the LNA
(see Fig. 3.9). This phenomenon is only problematic for systems where the transmit-
ter and receiver are operating simultaneously, i.e. non-TDD systems such as UMTS/
FDD [9], CDMA-I and CDMA-II [50]. Communication systems such as GSM and
Bluetooth use TDD and will thus not be affected by this problem. Since the
feedthrough is disturbing the received signal, receiver specifications such as sensitiv-
ity level and maximum BER come into play.
The influence of system specifications on transmitter design parameters is sum-
marized in Table 3. Moreover, system properties such as duplexing scheme (TDD/

LNA

Duplexer VCO

PA

Fig. 3.9. Feedthrough of the transmitter signal into the receiver.

Chapter 3 Transmitters for Mobile Handsets 41

FDD) have an impact on the required transmitter phase noise and linearity, as will be
shown in the examples below.
TABLE 3. SYSTEM SPECIFICATIONS VS. TRANSMITTER DESIGN ASPECTS

TX output noise floor

TX phase noise

TX linearity
Adjacent channel leakage power ratio X X
Spectral emission mask X X
Out of band emission requirements X X
RX reference sensitivity level X X
Output power levels X X X

3.3.3. TRANSCEIVER CALCULATION EXAMPLES

Noise and Distortion Related to Receiver Noise Floor
The effect of all noise and distortion related to the receiver noise floor will be shown
by means of a UMTS example. The total noise and distortion in a 3.84 MHz channel,
PN,tot, at the receiver input must be lower than P des – E b ⁄ N t + PG – IL = – 101dB
where the duplexer insertion loss IL is estimated to be 2 dB, and the following
parameters have been used [9]:
TABLE 4. KEY UMTS RECEIVER/TRANSMITTER SPECIFICATIONS

parameter description value

Pdes RX minimum desired signal a -117 dBm

Pout TX output power b 24 dBm

Eb/Nt RX combined received energy per infor- 6 - 7 dB

mation bit to effective noise psd ratio nec- [51], [51]
essary to meet BER specification
PG processing gain (chip rate/bit rate) 25 dB
BW channel bandwidth 3.84 MHz
a. In the so-called Dedicated Physical Channel, DPCH.
b. The maximum transmitter Class 3 output power.
42 Part I. General Introduction

NRX RX
Pdes = desired signal
Nth
NTX-RX NRX = RX noise (at input)
Pdes D Nth = thermal noise
NTX-RX = noise from TX to RX
Duplexer
D = distortion
TX

Fig. 3.10. The noise and distortion signals seen at the receiver input.

Taking into account receiver noise, leakage of transmitter output noise to the
receiver input and distortion reaching the input, PN,tot can be expressed as (see Fig.
3.10):
P N , tot = 10 log ( 1000kT ) + 10 log ( BW ) + 10 log ( F RX + N TX – RX + D )
< – 101dBm
(3.5)
where FRX is the noise factor of the receiver, NTX-RX is the noise leaked from the
transmitter to the receiver input normalized to 4kTRs, and D is the normalized total
distortion reaching the receiver output. k is Boltzmann’s constant (1.38x10-23 J/K)
and T is the temperature of operation, assumed to be 300K. Thus, for the noise and
distortion at the receiver input, i.e. 10 log ( F RX + N TX – RX + D ) , 7 dB is left [51], [52].
NTX-RX is dependent on the isolation of the duplex filter, ISOdupl, and may be
expressed as

2
v tx
N TX – RX = ---------------------------------------
- (3.6)
ISO dupl ⋅ 4kT R S
2
where v tx (in V2/Hz) is the noise at the transmitter output in the receiver frequency
band. If it is assumed that the transmitter noise and distortion contribute equally and
may each contribute 5% to the total noise at the receiver input, the transmitter ther-
mal noise should be -180 dBm/Hz, or -130 dBm/Hz with a duplex filter isolation of
105 (50 dB). Moreover, the receiver noise figure should be less than 6.5 dB.
The transmitter to receiver leakage is problematic for systems where transmit-
ting and receiving occur simultaneously, such as UMTS.

Transmitter Phase Noise Requirements to meet the Spectral Emission Mask

The spectral emission mask limits the emission close to the desired signal, and thus
limits the allowed close-in phase noise. This is illustrated in Fig. 3.11. The phase
noise requirements may be expressed as follows:
Chapter 3 Transmitters for Mobile Handsets 43

TX output signal:
BB
spectral
emission
PA mask
Prel
VCO

f
Fig. 3.11. Spectral emission specifications determining the phase
noise requirements.

L ( ∆f ) = P rel ( ∆f ) – 10 log ( BW ) (3.7)

where Prel is the relative power to the desired signal power at a certain distance ∆f
from the carrier frequency, and BW is the measurement bandwidth as used in the
specifications. For the GSM system, the phase noise requirements of the transmitter
VCO are given in the table below.
TABLE 5. GSM TX PHASE NOISE REQUIREMENTS TO MEET THE SPECTRAL EMISSION MASK
SPECIFICATIONS [7].

∆f [MHz] 0.2 0.4 1.8 3 6

L [dBc/Hz] -75 -105 -113 -115 -121

The spectrum mask and spurious requirements for Bluetooth result in the following
close-in phase noise requirements:
TABLE 6. BLUETOOTH TX CLOSE-IN PHASE NOISE REQUIREMENTS TO MEET THE SPECTRAL
EMISSION MASK SPECIFICATIONS [8].

∆f [MHz] 0.5 1.5 ≥ 2.5

L [dBc/Hz] -80 -100 -120

However, it must be noted that spectral emissions are mainly due to non-linearities in
the PA. The VCO phase noise should therefore be well below these limits.

Transmitter Phase Noise Requirements to meet the Out-of-Band Emission Limits

As explained before, the transmitter out-of-band emissions are limited especially in
the receive band and in frequency bands where other systems operate. For GSM, the
44 Part I. General Introduction

most stringent requirements are in the GSM receive band. They result in certain far-
out transmitter phase noise requirements, which are given in the table below:
TABLE 7. GSM TX PHASE NOISE REQUIREMENTS TO MEET OUT-OF-BAND EMISSION
SPECIFICATIONS [7].

∆f [MHz] 10 a 20 b

L [dBc/Hz] -122 -139

a. Emission specified for the frequency

range 925-935 MHz.
b. Emission specified for the frequency
range 935-960 MHz.

If a duplex filter is present, the VCO phase noise requirements are eased according to
the attenuation from the duplex filter. For a typical GSM duplexer this would amount
to more than 30 dB [16].
For UMTS the out-of-band emissions are even specified in the GSM and DCS
bands. Both the resulting phase noise and output noise requirements are presented in
the table below.1
TABLE 8. UMTS TX FAR-OUT PHASE NOISE AND OUTPUT NOISE REQUIREMENTS TO MEET
OUT-OF-BAND SPURIOUS EMISSION SPECIFICATIONS [9].

925-935 935-960 1805-1880

f [MHz]
(∆f=40)

L [dBc/Hz] -101 -113 -105

noise power PN [dBm/Hz] -77 -89 -81

Once again, other noise and distortion are not taken into account.
The out-of-band emissions are related to the problem of neighboring handsets.
Taking GSM as an example, if one handset transmits the maximum allowable output
power and a close-by handset wants to receive the smallest signal, the following
equation may be used to determine the phase noise requirements:

L ( ∆f ) = P des – P out + Att dupl ( ∆f ) – C ⁄ ( N + I ) min – 10 log ( BW ) . (3.8)

Because of the separation in frequency between the transmit band and receive
band for GSM and UMTS, this mechanism determines the far-out phase noise
requirement. Relevant parameters are given in Table 9 [7].

1. A typical UMTS duplex filter is assumed, having an attenuation of 40 dB [16].

Chapter 3 Transmitters for Mobile Handsets 45

TABLE 9. GSM RX/TX SPECIFICATIONS

parameter description value

Pdes RX minimum desired signal -102 dBm

Pout TX maximum output power 33 dBm

C/(N+I)min RX required carrier to noise and interference ratio 9 - 12 dB

BW Channel bandwidth 200 kHz

∆f TX/RX band separation 20 MHz
Attdupl(∆f) Duplexer attenuation in RX frequency range 40 dB [16]

This results in a transmitter phase noise requirement of -160 dBc/Hz at 20 MHz.

Without a duplex filter this decreases to -200 dBc/Hz.
Arguably the TX output power used in the equation above may be chosen as 0
dBm, since according to the GSM specifications the receiver has to function with a
maximum blocking signal of 0 dBm. For that case the minimum desired signal that
must be received increases to -99 dBm. Thus, the phase noise requirement without
duplexer becomes -164 dBc/Hz at 20 MHz [40]. From these examples it can be seen
that the spurious emission requirements do not include the worst-case situation
described above.

Transmitter Phase Noise Requirements due to TX-RX feedthrough

Besides the output thermal noise, also the transmitter phase noise may disturb a
small received signal, depending on the isolation from transmitter to receiver. For a
CDMA system, the phase noise requirements may be expressed as:
L ( ∆f ) = P des – IL – P out + Iso dupl ( ∆f ) – ( E b ⁄ N t ) min + 10 log ( PG ) – 10 log ( BW )
(3.9)
where Isodupl is the isolation from transmitter to receiver at receive band frequencies.
For UMTS, the same parameters as in Table 4 were used. Additional parameters are:
TABLE 10. ADDITIONAL UMTS PARAMETERS

parameter description value

∆f Minimum TX/RX band separation 135 MHz

IL Insertion loss of duplexer to RX input 2 dB
Isodupl(∆f) Duplexer isolation from TX to RX 50 dB [52]
46 Part I. General Introduction

These parameters result in a transmitter far-out phase noise requirement of -141 dBc/
Hz at 135 MHz. Without a duplexer this would decrease to -191 dBc/Hz. This num-
ber is very unrealistic, both for a VCO and for a transmitter as a whole.

3.4. POWER AMPLIFIERS

The power amplifier is one of the most crucial building blocks in a transmitter. Its
linearity determines spectral regrowth and spurious emissions while its efficiency
determines much of the efficiency of the transmitter. For medium or high output
powers it is a large contributor to the transceiver power consumption, and thus has a
large impact on the battery lifetime.
In this section a brief overview will be given of basic PA parameters, starting
with the PA classes, efficiency and linearity. For a more thorough description see
[53], [54], [55], [56].

3.4.1. PA CLASSES
The number of classes for power amplifiers and their properties may seem to be
exhaustive, with names such as A, B, C, AB, D, E, F, and S. However, these classes
can be divided in three groups, starting with A, AB, B and C, then D, E and F, and
treating class S individually.

Class A, AB, B and C

For the classes A through C the PA structure is the same (see Fig. 3.12), the only dif-
ference being the biasing point [55]. The DC current is supplied through the RF
Choke inductor (RFC), while capacitor CDC functions as a DC block, making sure
no DC current reaches the output. The input voltage Vin will lie above the threshold
voltage Vth for a limited time, depending on the biasing level at the gate of the MOS-
FET, as illustrated in Fig. 3.13. For class A, the input voltage exceeds Vth at all times,
giving a conduction angle α of 2π. For class B, the conduction angle is exactly

RFC
CDC

Vin + L1
C1
RL
-

Fig. 3.12. A general class A through C power amplifier.

Chapter 3 Transmitters for Mobile Handsets 47

halved to π. A class AB amplifier has a conduction angle between these values, i.e.
2π < α < π , and a class C has a conduction angle less than π.
Equations for the DC current IDC, the fundamental output current I1 and second
harmonic I2 may be derived as a function of α, assuming the transistor can be mod-
eled as an ideal transconductance [53]:
I max 2 sin α ⁄ 2 – α cos α ⁄ 2
I DC = ---------- ⋅ ---------------------------------------------------- (3.10)
2π 1 – cos α ⁄ 2
α⁄2
1 I max
I 1 = ---
π ∫ - [ cos θ – cos α ⁄ 2 ] cos θ dθ
---------------------------
1 – cos α ⁄ 2
(3.11)
–α ⁄ 2
I max α – sin α
= ---------- ⋅ ----------------------------
2π 1 – cos α ⁄ 2

and
α⁄2
1 I max
I 2 = ---
π ∫ - [ cos θ – cos α ⁄ 2 ] cos 2θ dθ
---------------------------
1 – cos α ⁄ 2
(3.12)
–α ⁄ 2
I max α
= ---------- ⋅ ----------------------------  – --- sin ------- + sin ---
1 1 3α
2π 1 – cos α ⁄ 2  3 2 2

Here Imax is the maximum current drawn by the MOSFET. The ideal DC, fundamen-
tal and second-order components, normalized to Imax, are plotted in Fig. 3.14. It can
be seen that the fundamental output component is lower for class C (α < π) than for
class A (α = 2π). The second-order component, however, is larger for class C than
for class A. This is logical as the former is a non-linear amplifier while the latter ide-

class A Class A: α = 2π [rad]

Class B: α = π [rad]
Vin
Class C: α < π [rad]
class B
Class AB: 2π<α<π [rad]

Vth
0 α [rad]
t

class C

Fig. 3.13. PA input voltage waveforms indicating conduction angle α.

48 Part I. General Introduction

0.7

0.6

I1
0.5

Io/Imax
0.4
Idc
0.3

0.2 I2

0.1

0
0 1 2 3 4 5 6 7
alfa

Fig. 3.14. Ideal normalized DC, fundamental and second order out-
put current as a function of the conduction angle α.

ally is perfectly linear. The parallel LC circuit (L1 and C1 in Fig. 3.12) passes the
desired output component while attenuating other tones. Ideally these tones do not
reach the antenna.

Class D, E and F
A class D power amplifier (see Fig. 3.15) is based on the use of transistors as
switches. The amplifier basically works as an inverter, with the PMOSFET supply-
ing current for a low Vin and the NMOSFET supplying current for a high Vin. The
signal at the drains of the two MOSFETs is a square wave. The series LCR network
stops undesired harmonics from reaching the antenna. The theoretical maximum
drain efficiency (see section 3.4.2) is 100%; non-zero ON-resistance of the switches
and finite switching speed will, however, reduce the efficiency [53], [55]. Output
power control or amplitude modulation is not possible without changing the supply
voltage.
In a class E amplifier, a single MOSFET is used as a switch. The output network
as shown in Fig. 3.16 gives the drain voltage a specific shape in the time domain, and
the component values must be chosen with care [57]. The voltage over the MOSFET

C1

+
Vin
-

Fig. 3.15. A class D power amplifier.

Chapter 3 Transmitters for Mobile Handsets 49

RFC VDS
C1 L1

Vin + C2 RL
-
t T

Fig. 3.16. A class E power amplifier and voltage waveform for one
period T.
is shaped so that it has both a value of 0 and a slope of 0 when the switch turns on,
thus reducing the power loss of the switch. The theoretical efficiency is 100%,
depending on the switch ideality. The power handling capability is limited since the
peak voltage is high, increasing the risk for breakdown in the MOSFET. Also, power
control or amplitude modulation is in principle not possible at a constant supply volt-
age.
The principle behind a class F power amplifier is a boosting of the higher-order
harmonics in order to decrease the peak voltage over the MOSFET when the current
is maximum, thus decreasing the power consumption [58]. A simplified schematic
and ideal waveforms are shown in Fig. 3.17.
Also for this PA the MOSFET operates as a switch. The theoretical maximum
efficiency is 100%. Note that the only difference from a standard class A through C
PA (see Fig. 3.12) is the section formed by L2 and C2, apart from the MOSFET
behaving as a switch in this PA. In classical microwave class F amplifier design a
transmission line is used instead of this section [30].

Class S
A class S PA basically is a class D PA with input pulse width modulation (PWM),
where a sigma-delta modulator may be used for the modulation [59]. However, the

VDS

RFC
C2
CDC
t T
ID

Vin + L1 RL
L2 C1
-

t T

Fig. 3.17. A class F power amplifier with ideal voltage over and cur-
rent through the MOSFET.
50 Part I. General Introduction

desired modulation puts higher speed requirements on the switches, which makes
this class unsuitable for GHz range PAs. Technology advancements may allow for
these switching speeds, but this will come with increased power consumption,
decreasing the overall efficiency.

3.4.2. OTHER PA ISSUES

The knee voltage
The knee voltage, Vknee, is the drain-source voltage at which the MOSFET starts to
operate as an amplifier. Assuming the PA consists of one single MOSFET (as in Fig.
3.12), Vknee is the same for the PA as for the MOSFET. If a cascode stage is used the
PA knee voltage will be increased.
Traditionally the knee voltage is taken to be the voltage where the PA has
reached 90% of its drain current in a typical I-V characteristic (see also chapter 4).
However, if this is applied to a MOSFET, the knee voltage will be impairingly high.
A typical MOSFET definition would be the drain-source voltage where the FET
enters the saturation region.
One of the consequences of Vknee is a reduction of the maximum voltage swing
at the drain, from 2VDD to 2(VDD-Vknee). This will have a negative impact on the effi-
ciency.

Efficiency
A key performance measure for power amplifiers is efficiency. Several definitions
exist. First, the drain efficiency is defined as
P out
η = ---------
- (3.13)
P DC

i.e. the ratio of the output power to the DC power. Another definition is power added
efficiency (PAE):
P out – P in
PAE = ----------------------- (3.14)
P DC

Here the input power is taken into account as well. For a PA with a high power gain,
the drain efficiency and PAE will be almost equal.
For a class A amplifier the maximum fundamental output power Pout,max is given
by

î max v̂ max I max V DD

P out, max = --------------------
- = ---------------------
- (3.15)
2 4
Chapter 3 Transmitters for Mobile Handsets 51

where î max and v̂ max are the maximum amplitude of the current and voltage swing at
the drain. It is assumed that the PA has an optimum load impedance, that the knee
voltage is 0 and that the MOSFET acts as a current source drawing a maximum cur-
rent of Imax. The DC power is given by
I max V DD
P DC = ---------------------
- (3.16)
2
so that the efficiency η = 0.5 = 50%.
Similar derivations can be made for all classes. In the table below the theoretical
maximum efficiency is given for each class [55].
TABLE 11. THEORETICAL MAXIMUM DRAIN EFFICIENCY FOR PA CLASSES

PA class max. drain efficiency η [%]

A 50
AB 50-78.5
B 78.5
C 78.5-100
D 100
E 100
F 100
S 100

If the input power of the PA is lower than the input power associated with the
maximum output power, maximum efficiency is not reached. Assuming an ampli-
tude of A at the drain, which sees a load resistance Ropt, the output power of the PA is
2
A
P out ( A ) = ------------- (3.17)
2R opt

Here the knee voltage is ignored, and thus A ≤ V DD 1. For class A amplifiers the DC
power is given by Eq. 3.16, resulting in an amplitude-dependent efficiency of

P out ( A ) A
2
η ( A ) A = ------------------
- = -------------------------------- . (3.18)
P DC, A R opt I max V DD

For class B, the DC power is

1. Assuming the output signal is voltage limited, not current limited.

52 Part I. General Introduction

2 A
P DC, B = --- ---------- V DD (3.19)
π R opt

resulting in an efficiency of
P out ( A ) πA
η ( A ) B = ------------------
- = -------------- . (3.20)
P DC, B 4V DD

In Fig. 3.18 the amplitude-dependent efficiencies for class A and B are shown.
Assuming the PA is backed off with 3 dB, the amplitude of the output voltage is
reduced by a factor of 2 [53]. The efficiencies for class A and B are then:
V DD V DD
η  ----------- = 25 % and η  ----------- = 56 %. (3.21)
 2 A  2 B

Linearity
As was described previously, PA non-linearity is an important issue in transmitter
design, especially for systems with variable envelope modulation. The non-linearity
causes various problems, such as gain compression, intermodulation distortion, and
AM-to-PM (amplitude modulation to phase modulation) conversion. Both gain com-
pression and intermodulation distortion were already discussed in chapter 2; they
affect a power amplifier in a similar way, with some significant differences. The PA
is operated with large signals, implying that it is very likely operating in the gain
compression region. Thus, amplitude distortion will occur. Moreover, intermodula-
tion behavior is quite complicated in this region and will most likely not follow a 3
dB slope for 3rd order intermodulation. Thus, the intercept point is of limited use for
a PA.

78%
η(A)

50%

ηB

ηA

VDD
A
Fig. 3.18. The amplitude-dependent maximum efficiency for class A
and B.
Chapter 3 Transmitters for Mobile Handsets 53

AM-to-PM conversion can be defined as an amplitude-dependent phase shift [6].

It is caused by signal-dependent device elements or non-linear resistances, such as
the MOSFET input capacitance and resistances in the depletion layer and junctions
(see also chapter 4). It is difficult to model these effects accurately, especially since
the device is operated at large signals. AM-to-PM conversion results in distortion at
the same frequencies as intermodulation distortion.
The ACLR for a transmitter was already discussed in section 3.3. Also for power
amplifiers the ACLR is often characterized, since it is a measure of the PA linearity
for which realistic signals are used.

3.5. TRANSMITTER LINEARIZATION

Depending on the communication system, the linearity of the transmitter may be a
crucial issue. In a system such as UMTS, where a variable envelope modulation is
used, a non-linear transmitter would cause a loss of signal information. In systems
using a constant-envelope modulation (e.g. GSM, Bluetooth), however, no informa-
tion is contained in the signal amplitude and linearity is not a critical issue [6], [53].
One way of achieving a better linearity is to back-off the power amplifier [53], i.e to
reduce the input signal. This gives a severe reduction in efficiency, and thus other lin-
earization techniques are preferred. In this paragraph a brief overview is given of
such techniques.

Predistortion
If the non-linear characteristic of the PA is known in advance, a ’reverse distortion’
may be added before the PA, as shown in Fig. 3.19. It must be noted that the non-lin-
earity of a PA may be difficult to predict and is dependent on many factors such as
process variations, temperature, impedances, etc. To have a fixed predistortion cir-
cuit may thus not yield sufficient improvement in linearity. However, in some appli-
cations even a few dB increase in linearity may be significant. More elaborate

pre-distortion
circuit PA
BB
mod.

LO

Fig. 3.19. Predistortion linearization technique.

54 Part I. General Introduction

Vin Vout
Av +
-1/Av

+ Av

Fig. 3.20. Feedforward linearization technique.

predistortion techniques may be used, incorporating for instance feedback loops and
look-up tables [53].

Feedforward
In a feedforward system, the difference between the undistorted input signal and a
fraction of the output of the main PA is fed to an auxiliary PA, as shown in Fig. 3.20
[6]. This auxiliary amplifier thus only sees small input signals. Assuming equal gain
in both amplifiers as well as ideal adders and connections, the output voltage
V out = A v V in . However, phase and gain mismatches in the amplifiers, interconnects
and adders (or power combiners) limit the performance of the feedforward architec-
ture. Also amplifier delay may cause problems [53].

Feedback
PA linearization feedback loops generally incorporate a downconversion mixer, so
that the output signal can be compared to the baseband signal (see Fig. 3.21), and the
loop bandwidth may be kept low. In this figure, θ is the excess phase used to ensure
stability in the loop. It is dependent on PA output power, process variations and tem-
perature, implying that it is undesirable to use a fixed value.
For quadrature modulated baseband signals the feedback loop must be expanded
into I- and Q paths; the feedback is then called “Cartesian feedback” [6].

VBB
VRF
Av PA

LO

LO+θ

Fig. 3.21. Feedback linearization technique.

Chapter 3 Transmitters for Mobile Handsets 55

(envelope information)

Envelope
Detector Av

Vin

Vout
Limiter PA

(phase information)

Fig. 3.22. Envelope Elimination and Restoration (EER) linearization

technique.

Envelope Elimination and Restoration (EER)

With EER the RF signal is first split into a phase- and envelope signal. The phase
signal drives a switching PA and the envelope signal controls the PA supply voltage.
Thus, the two components are combined again in the output signal (see Fig. 3.22)
[60], [61].
This technique does not require a linear PA. However, the performance is limited
by non-ideality of the limiter, non-linearity in the envelope detector, unequal delay in
the branches and supply-to-input isolation of the PA. Also, the PA may suffer from
AM-to-PM and AM-to-AM conversion, which causes distortion. One of the chal-
lenges in this architecture is that the signals in the two branches are of a different
nature; the envelope signal is low-frequency, while the phase signal is high-fre-
quency.

Linear Amplification with Non-Linear Components (LINC)

LINC is based on the notion that an amplitude- and/or phase modulated bandpass
signal may be decomposed in two constant-amplitude phase modulated signals (see

v1 (const. env.)
PA V1
Vout
Vin Vout
Signal
Separator +
- -V2

PA
v2 (const. env.)

a. b.
Fig. 3.23. LINC linearization technique, a). architecture, b). signal
component vector diagram.
56 Part I. General Introduction

Fig. 3.23) [62], [63]. The most complex part is the signal separator. LINC perfor-
mance is dependent on mismatch in the two signal paths as well as the isolation
between the inputs of the adder. The latter is necessary due to the different phases of
the signals in the two branches.

Combined Analog Locked Loop Universal Modulator (CALLUM)

A feedback variety of LINC is called CALLUM [64]. Like the Cartesian feedback
architecture it incorporates downconversion. A signal separator is operating at base-
band frequency, the two signals are upconverted, amplified, added and fed to the out-
put. The output signal is then downconverted and fed back to the signal separator
(see Fig. 3.24).
Advantages of CALLUM compared to LINC are that the signal separator is
operating at a lower frequency. Moreover, negative feedback suppresses all distortion
independent of origin, depending on the loop gain. Disadvantages are its increased
complexity (e.g., several VCOs are necessary) and potential loop stability problems.

Cancellation
Besides transmitter linearization architectures, some work has been done on the
building block level, i.e. amplifier linearization. One strategy is to have parallel
devices with different bias and dimensions, so that intermodulation products may be
nulled when summing the signals at the output [65]. Another strategy is to inject sig-
nals at the PA input that cancel the intermodulation products of the original signal at
the output [66]. A disadvantage of such techniques is that nulling of intermodulation
generally occurs only for a certain bias point or input level. Moreover, reliable simu-
lation of these designs is highly dependent on the quality of the device model.

The PA described in Paper IV has a similar structure as the PA described in [65], but
is more focused on efficiency improvement than linearity improvement.

PA

I,Q mixer Vout

Vin Signal I,Q
Separator

PA

Fig. 3.24. CALLUM linearization technique.

Chapter 3 Transmitters for Mobile Handsets 57

3.6. DISTURBANCE ISSUES IN TRANSCEIVERS

One of the main issues in integrated transmitter or receiver design is the isolation
between different signal nodes, since large signals are active on the same chip as sen-
sitive desired signals. In a mixed-signal chip, large digital switching circuits may
cause a large switching current, which creates transient voltages on the supply nodes
(ground and VDD). In the RF part, high-power PA or VCO signals may leak to other
parts of the chip.
The isolation on a chip is limited since there are many paths for disturbances, for
example through bondwire coupling or due to finite substrate resistivity. This section
will give an introduction to some important disturbance mechanisms in RF circuits.
Some consequences of this disturbance are described, as well as solutions, some of
which are on the architectural level.

3.6.1. DISTURBANCE MECHANISMS

Substrate Coupling
An important source of disturbance in silicon technologies is coupling through the
substrate [74]. Through capacitive coupling of the device to the substrate, distur-
bance is injected into the latter, which then may reach other circuit elements. Also
disturbance on supply nodes may be transferred through the substrate. This is espe-
cially problematic for standard CMOS; if other technologies are used such as III-V
or silicon-on-isolator, the substrate is highly resistive or isolating, and disturbance
will not propagate as easily through the substrate.

Bondwire Coupling
Mutual coupling exists between bondwires, depending on the distance and angle
between them, their length and the surrounding medium. If high-power and sensitive
signals use adjacent bondwires, the mutual coupling can cause disturbance such as
LO-to-RF feedthrough (see [6]) in case of an off-chip VCO, or power amplifier-to-
LNA feedthrough.

3.6.2. EFFECTS OF DISTURBANCE

Influence on Devices
Firstly, MOSFETs may pick up disturbances directly from the substrate through the
capacitances to substrate. A second mechanism is due to the body effect, described
in paragraph 4.2.2, where the body (substrate) can be regarded as a second gate, a
back-gate, of the transistor. This generates a drain current depending on the bulk
58 Part I. General Introduction

(body)-to-source voltage vBS. If the source and bulk are connected on-chip, they will
see the same disturbance, and vBS will be 0.
Inductors and other passive devices are mainly exposed to disturbances through
capacitive coupling to the substrate. While most passive structures will act as a
medium to pass disturbance to other parts of the circuit, elements such as junction
capacitors are voltage dependent (see paragraph 4.3.1) and can thus suffer from
altered characteristics or component values due to the disturbance.

Influence on LNA and VCO

A transceiver as depicted in Fig. 3.25, with a power amplifier (PA), a duplexer for
frequency domain duplexing (FDD), and an LNA at the receiver end, will suffer
from feedthrough from the PA output to the LNA input. This is mainly due to the
non-ideal filtering characteristic of the duplexer, which allows a small portion of the
transmitted power through the duplexer to reach the LNA. This small portion may be
large enough to desensitize the LNA, since the maximum output power of the PA is
on the order of several tens of dBm [22]. Other leakage paths can be the package of
the duplexer, bondwires or the printed circuit board on which the components are
mounted [19].
Two sources can be pointed out for high power signals reaching the oscillator,
namely a signal originating from the power amplifier, and a large interferer in the
receive path, both indicated in Fig. 3.25. If the interfering signal frequency is rela-
tively far away from the oscillation frequency fLO, this frequency will not change,
but the interfering signal will merely add to the oscillator phase noise.
If the interferer has a frequency close to fLO, then fLO will move towards the fre-
quency of the interfering signal. This is called oscillator pulling and is described in
[38]. The issue of oscillator pulling should be taken into account when considering
the frequency planning of the transceiver.

LNA baseband
ADC DSP

RF
Duplexer VCO

PA
DAC DSP
baseband

Fig. 3.25. A transceiver with disturbance paths indicated.

Chapter 3 Transmitters for Mobile Handsets 59

3.6.3. METHODS TO REDUCE THE EFFECT OF DISTURBANCE

Layout
On a physical layout level, the placement of sensitive parts is crucial, as is the use of
guarding techniques. For a lightly doped silicon substrate (as is used for bipolar and
BiCMOS technologies) so-called guard rings can largely reduce the disturbance,
since they may act as a current sink for lateral currents. It is important to use a sepa-
rate ground pin for the guard rings [74]. Physical separation of the circuits or build-
ing blocks plays a large role in reducing the effect of disturbances.
A heavily doped substrate behaves more as a single grounded node. The distur-
bance is much less dependent on physical distance, and eventually stays constant
with increasing distance between two blocks [68].

Frequency Planning
The issue of frequency planning for a transmitter is quite different from receiver fre-
quency planning, in that disturbing signals are not coming from the outside world but
are generated on-chip or on-board. A critical issue is the coupling of the high-power
PA signal to the VCO, especially if they operate at the same frequency. In order to
prevent oscillator pulling in the transceiver, a frequency plan must be designed
where both transmitter and receiver signals are taken into account. If the system is
TDD the receiver and transmitter may share one VCO. However, for a system such
as UMTS/FDD the transmitter and receiver may be operating simultaneously, with
the possible result of having two VCO signals and one PA signal on at the same time.
Several strategies may be used to circumvent this problem, for instance using a
two-step transmitter with a relatively high IF1 and IF2 (see Fig. 3.3). If a direct con-
version transmitter architecture is used, the LO signal may be composed by mixing
two VCO signals (so-called offset LO [6]), or by frequency multiplication [44]-[48].
Another alternative is to have the VCO operate at twice the desired LO frequency,
and then use a divider to create the desired LO frequency. An additional advantage of
this strategy is that quadrature signals may easily be generated [6].

In Paper V the issue of oscillator pulling is addressed by utilizing a PA with internal

frequency doubling.
60 Part I. General Introduction
CHAPTER 4

RF CMOS TECHNOLOGY ASPECTS

4.1. INTRODUCTION
The utilization of CMOS VLSI technologies for RF applications is becoming more
and more established. It is made possible mainly by the channel length decreasing to
submicron sizes, providing an opportunity to increase the cut-off frequency fT and
maximum oscillation frequency fmax.
The advantages of scaling down the transistor dimensions are apparent in digital
design, where a steady decrease is seen in the power-delay product [69], [71]. How-
ever, in analog design some disadvantages appear. One disadvantage is that the
breakdown voltage decreases with reduced physical dimensions, so that lower sup-
ply voltages must be used and stacking of transistors is less efficient.
In this chapter CMOS technology and MOSFET operation are briefly discussed
[69], [70], [71]. An overview will be given of the influence of scaling, and some
problems related to deep-submicron technology are described. Finally inductors will
be treated, since they are important for the performance of RF circuits such as LNAs,
VCOs, and PAs.

4.2. BASIC MOSFET CHARACTERISTICS AND MODELS

4.2.1. BASIC OPERATION
For most modern standard CMOS technologies a p-type substrate is used. This is a
heavily doped substrate (bulk), with a resistivity ρ < 0.1 Ω−cm, covered with a
lightly doped epitaxial layer with a thickness of 5 to 15 µm. The heavily doped sub-
strate is utilized to reduce the risk for so-called latch-up, the malfunctioning or
destruction of a CMOS circuit through parasitic bipolar transistors forming a thyris-
tor structure [69]. Other measures to prevent latch-up can be found in [69]. The epi-
taxial layer will be neglected further in this chapter.

61
62 Part I. General Introduction

polysilicon L
W
gate oxide G G
S/D S/D S/D S/D
epitaxial layer
p- n-well Leff
n+

p substrate p+
B

Fig. 4.1. An NMOS (left) and PMOS (right) transistor in a p-type

substrate.
In Fig. 4.1 the two basic MOSFETs - n-channel and p-channel - are shown for a
p-type substrate. The gate length L is the so-called drawn gate length, which is
reduced during manufacturing to the effective gate length Leff [70]. Due to the sym-
metry of the devices the source and drain are not defined until terminal voltages are
applied.
Typically the p-type substrate is connected to the lowest supply voltage, thus
keeping the NMOS source- and drain junction in reverse bias condition, while each
n-well is generally connected to VDD, but they could theoretically be biased at differ-
ent voltages.
The n-channel MOSFET will be considered in more detail. The PMOSFET
shows similar behaviour, but is not used as often in RF circuits. Depending on the
gate-to-source voltage 1, vGS, the MOSFET is said to operate in different ’inversion
regions’:
• vGS > VH: strong inversion region
• VM < vGS < VH: moderate inversion
• vGS < VM: weak inversion
where V H – V M ≈ 0.5 – 0.6 V, VM < Vth < VH, and Vth is the threshold voltage. This
will not be explained further; for a more thorough description see [71]. Assuming
v DS > 0 , the NMOSFET shows two basic regions of operation dependent on the
drain-to-source voltage, vDS, and vGS:
• vDS < Veff: triode (or linear) region
• vDS > Veff: saturation region

1. Each terminal voltage vIJ may consist of a constant bias voltage, VIJ, and a time-varying signal
voltage, vij: v IJ = V IJ + v ij . For small signals the bias point and region of operation may be
considered constant, but for large signals the bias point and region of operation may become sig-
nal-dependent.
Chapter 4 RF CMOS Technology Aspects 63

vG
inversion layer vG
inversion layer
vS vD vS vD
-- ---- -- - -- depletion region ----------
n+ n+
n+ n+

p substrate
p substrate

vB
vD
a. b.
Fig. 4.2. Schematic representation of charges in the channel for a).
triode, b). saturation region.

where Veff is the overdrive voltage ( V eff = v GS – V th ). For the most relevant regions
of operation expressions can be derived for the drain current ID and transconduct-
ance gm. These expressions have been derived under certain ideality assumptions,
such as constant carrier mobility in the channel, no reverse leakage current and a
bulk-source voltage vBS=0. Some of these second-order effects will be covered in
section 4.2.2.

The Triode Region

Starting from vDS = 0, if vGS is large so that Veff > 0 and Veff > vDS, the MOSFET is in
triode region and an inversion layer is formed as shown in Fig. 4.2a. If a small vDS is
applied, drain current can flow:
W
I D ≈ µ n C ox --------- V eff V DS (4.1)
L eff

where
Leff = the effective gate length (see Fig. 4.1)
µn = mobility for electrons
Cox = oxide capacitance (see section 4.2.3)
W = transistor width (see Fig. 4.1).

The transconductance gm, defined as ∂I D ⁄ ∂v GS , then becomes

W
g m = µ n C ox --------- v DS (4.2)
L eff

In this region of operation the MOSFET can be seen as a voltage controlled resis-
tance, controlled by Veff, where the resistance RON is given by [70]
64 Part I. General Introduction

S D
Ron

Fig. 4.3. A MOSFET in triode, modeled as a resistance Ron.

1
R ON = ----------------------------------- (4.3)
W
µ n C ox --------- V eff
L eff

Note that only in deep triode region, i.e. vDS << Veff, the MOSFET can be expected to
behave as a linear resistance. A simple triode region MOSFET model is shown in
Fig. 4.3. For larger vDS, but with the MOSFET still in triode region, the drain current
is given by

I D = µ n C ox ---------  V eff v DS – --- v DS

W 1 2
(4.4)
L eff  2 

The Saturation Region (strong inversion)

If the drain-source voltage vDS is increased so that v DS > V eff , the MOSFET will
enter the saturation region and the channel will be pinched off (see Fig. 4.2b). Rais-
ing VDS further moves the pinch-off point slightly towards the source. In this region
the drain current can be approximated as
1 W 2
I D ≈ --- µ C ox --------- V eff (4.5)
2 n L eff

which appears to be independent of vDS, assuming the effective channel length to be

constant. In this region the transconductance gm is given by

∂I D W 2I D W
gm = = µ n C ox --------- V eff = ---------
- = 2µ n C ox --------- I D (4.6)
∂ v GS L eff V eff L eff

In reality the channel length is not constant, but is dependent on vDS. This so-called
channel length modulation will be considered in the next section. For small signals
and constant bias point, gm is constant. The most basic small-signal model for the
MOSFET in saturation is the hybrid-π model shown in Fig. 4.4.
The MOSFET can achieve higher gain in the saturation region than in the triode
region. Therefore, in gain stages MOSFETs are usually biased in the saturation
region.
Chapter 4 RF CMOS Technology Aspects 65

G D
+
vgs
gmvgs
-

Fig. 4.4. Basic small-signal hybrid-π model of a MOSFET in satura-

tion.

The Weak-Inversion Region

In the weak-inversion region, where Veff is slightly below 0 V, the drain current
shows exponential behavior and may be expressed as:
v GS
I D ≈ I 0 exp  ---------- (4.7)
 ζV T 

where VT is the thermal voltage defined as kT ⁄ q , which is about 26 mV at room

temperature (T=300K). ζ is a factor larger than 1. The expression for the transcon-
ductance gm becomes:
ID
g m = ---------
- (4.8)
ζV T

and is similar to the expression for gm in a BJT except for the factor ζ.
This region is not suitable for high-frequency operation, but is of use in some
low-power/low-frequency applications such as hearing aids. The weak-inversion
region points to a problem apparent in digital circuits, which is leakage current: the
drain current is not cut off abrubtly for vGS < Vth, but decreases exponentially. This is
one of the main reasons for keeping the threshold voltage Vth at a relatively high
level instead of scaling down with the technology (see paragraph 4.2.4).

4.2.2. SECOND-ORDER EFFECTS

Two important second-order effects are the channel length modulation and the body
effect. As was already indicated in the previous paragraph, the effective channel
length in the saturation region can not be assumed constant, but is dependent on vDS.
The drain current including channel length modulation may be given by [70]
1 W 2
I D = --- µ n C ox --------- ( V eff ) ( 1 + λv DS ) (4.9)
2 L eff

with λ ∝ 1/L. A typical value for λ is 0.1. For short-channel MOSFETs this linear
approximation is inaccurate [70].
66 Part I. General Introduction

In the previous paragraph it was assumed that the bulk - source voltage vBS = 0.
However, this approximation is not always valid. If the source voltage vS is varied
such that vBS < 0 while all other voltage differences are kept constant- alternatively
decreasing vB while keeping all other voltages constant - it can be seen that the
depletion region will become larger and thus the threshold voltage for creating an
inversion layer will increase. This phenomenon is referred to as the body effect [70].
It is dependent on the substrate doping Nsub and the oxide capacitance Cox, two
important parameters in device scaling of modern technologies. An analysis based
on charges can be found elsewhere [70], [71] and will not be given here.

Modeling of Second-Order Effects

In the small-signal model the body effect can be represented by an additional current
source controlled by vbs, parallel to the current source controlled by vgs (see Fig.
4.5). The body small-signal transconductance gmb is [70]
γ
g mb = g m ⋅ ------------------------------- (4.10)
2 2φ F + v SB

where φF is the Fermi potential and γ is the body effect coefficient. The channel
length modulation can be modeled as a resistance rds at the output [70] with

qN sub ( v DS – V eff )
r ds ≈ -------------- ⋅ L ⋅ --------------------------------- (4.11)
2ε Si ID

Both the body effect and channel length modulation are taken into account in the
small-signal model shown in Fig. 4.5.
A MOSFET quality parameter is gmrds, which is the intrinsic gain of the transis-
tor, or the maximum voltage gain that can be achieved in an amplifier using a single
MOSFET 1. This is given by

G D
+ gmvgs
vgs rds

- gmbvbs
-
S vbs
B +

Fig. 4.5. A small-signal model where the body effect and channel
length modulation are modeled with gmbvbs and rds, respectively.

1. Ignoring the body effect; otherwise this is only valid for a CS configuration.
Chapter 4 RF CMOS Technology Aspects 67

2qN sub ( v DS – V eff )

g m r ds = ------------------ ⋅ L ⋅ --------------------------------- (4.12)
ε Si V eff

and is usually larger than 10 for modern technologies [70]. It is bias dependent, as
can be seen from the above expression.

4.2.3. FREQUENCY DEPENDENT OPERATION

In this paragraph device capacitances and microwave parameters such as ft and fmax
will be considered. It must be stressed that short-channel effects are still not taken
into account.

Device Capacitances
Based on a quasi-static analysis of the NMOSFET, the major capacitances in the
device are shown in Fig. 4.6 (after [70]). Cox is the capacitance between the channel
and the polysilicon gate, given by
C ox = W L eff C ox' (4.13)

with
C ox' = ε 0 ε r ⁄ t ox (4.14)

where εr is the relative permittivity of the silicon dioxide (about 3.9), ε0 is the per-
mittivity of free space, and tox is the oxide thickness. Leff can be approximated as
L – 2L D , where LD is the overlap of the gate on the source- and drain regions (see
Fig. 4.6).
The overlap capacitances Cov are due to the physical overlap between the
source- and drain areas and the gate:
C ov = W C ov' (4.15)

where C ov' is the overlap capacitance per unit width.

D L

Cov Cov
Cox

Cjs Cjd

LD
p substrate

Fig. 4.6. An NMOSFET with parasitic capacitances.

68 Part I. General Introduction

Cjs and Cjd are junction capacitances between the n-doped source and drain
regions and the p-doped substrate. Both the bottom-plate and side-walls contribute to
the capacitance:
C j0, side/bottom
C j, side/bottom = ----------------------------------------------------------------------
m ( side, bottom )
- (4.16)
( 1 + V rev ⁄ 2Φ F )

where Vrev is the reverse voltage across the junction. The value of m depends on the
doping profiles, and is typically in the range 0.3-0.4 [70]. The bottom-plate capaci-
tance Cj,bottom has the unit of capacitance per unit area, and the total bottom-plate
area is the transistor width multiplied by source- or drain- length D. The side-wall
junction capacitance Cj,side is given in capacitance per unit length, and the total side-
wall length is equal to the transistor width W. This gives
C j ( s, d ) = WDC j, bottom + W C j, side (4.17)

It is not straightforward to calculate the zero-bias capacitance Cj0 for small dimen-
sions. Thus, its value for both the side-wall and the bottom-plate junction capaci-
tance is commonly determined by measurements. If the transistor is placed in an n-
well (see Fig. 4.1) the junction capacitance of the well must also be taken into
account.
If the device is on, the inversion layer acts as a shield between the gate and bulk
[70]. Moreover, the capacitance between source and drain is very small and is usu-
ally neglected. The capacitances for the device in saturation can now be written as:
2
C GS = --- W L eff C ox' + W C ov' (4.18)
3
C GD = W C ov'

C SB ≈ C DB = WDC j, bottom + W C j, side

The basic model for a MOSFET in saturation may thus be extended to the model
shown in Fig. 4.7.
In the triode region, the capacitances as shown in Fig. 4.8 are given by
CGD
G D
+
CGS rds
vgs
gmvgs gmbvbs
- CDB
-
S vbs
B +
CSB

Fig. 4.7. Model of a MOSFET in saturation with device capacitances.

Chapter 4 RF CMOS Technology Aspects 69

G
CGS CGD

S D
Ron
CSB CDB

Fig. 4.8. A MOSFET in triode modeled as a resistance Ron with para-

sitic capacitances.

1
C GS = C GD = --- C ox + W C ov' (4.19)
2
C DB = C SB ≈ WDC j, bottom + W C j, side

Since the channel is not pinched off, it is assumed that the oxide capacitance (Cox in
Fig. 4.6) is equally divided between source and drain, so that CGS = CGD.

MOSFET Microwave Characteristics

A semiconductor technology can generally be characterized by parameters such as
fT, the cut-off frequency, and fmax, the maximum frequency of oscillation for a device
[71], [72], [73]. The cut-off frequency fT is defined as the frequency at which the
small-signal current gain of the transistor with shorted output is equal to 1. Using Y
or H parameters, this can be written as
y 21
---------
- = 1 or h 21 = 1 (4.20)
y 11

For CMOS, fT can be calculated as [72]

gm 1
f T ≈ ------------- = µ eff ⋅ V eff ⋅ -----2 (4.21)
2πC g L
which is independent of the transistor width W. Here µeff is the effective mobility,
influenced by velocity saturation (see paragraph 4.3).
The maximum oscillation frequency fmax is defined as the frequency at which
the available power gain of the MOSFET is reduced to 1 [72], thus
2
y 21 – y 12
----------------------------------------------------------------------------------------------------
- = 1 (4.22)
4 ( Re ( y 11 ) ⋅ Re ( y 22 ) – Re ( y 12 ) ⋅ Re ( y 21 ) )

so that
70 Part I. General Introduction

fT
f max = ---------------------------
- (4.23)
8πR g, i C GD

where Rg,i is the intrinsic gate resistance which can be expressed as

R poly, W
R g, i = ------------------------- (4.24)
3L
The factor of 3 is due to the distributed nature of this resistance and R poly, is the
sheet resistance of the polysilicon gate [72]. If the gate is contacted at both ends this
factor will be 12. In many analog CMOS designs the gate resistance is neglected.
However, it will not only affect fmax but will also add noise and will influence the
input impedance of the device. It can be shown that fmax is inversely proportional to
W ⋅ L [72].
The model described above is useful for relatively low frequencies. For higher
frequencies non-quasi-static effects must be considered. Firstly, in strong inversion
the inversion layer will not be able to respond directly to fast changes in the terminal
voltages. Thus, a change in the source or drain voltage will cause a delayed change
in gate charge. Moreover, the drain current will not respond immediately to changes
in the gate voltage. Similar notions are valid for the substrate (the back-gate). Sec-
ondly, distributed effects in the extrinsic part may be modeled by using several RC
sections [71]. In the model shown in Fig. 4.9 both intrinsic and extrinsic effects are
taken into account. The latter have the subscript e. τ represents a certain delay. For
the model parameters see [71] and [72]. It must be noted that calculating the model
parameters from the physical behaviour of the MOSFET is difficult. Typically these
parameters are fit to measurement results, which reduces the general validity of the
model.

CGD,e
G D
+ gm(τ)vgs RD,e
RG,e vgs
rds
CGS,e - CGS
RS,e RGS gmb(τ)vbs
S
CBD+CBD,e
CBS,e RBS
CGB+CGB,e
-
RB,e CBS vbs
+
B

Fig. 4.9. A small-signal high-frequency model for a MOSFET in satu-

ration.
Chapter 4 RF CMOS Technology Aspects 71

4.2.4. SHORT-CHANNEL EFFECTS

There is an ongoing drive to shrink the channel length of MOSFETs [77]. Digital cir-
cuits benefit most, since total chip size shrinks for equal functionality and the power-
delay product decreases. RF CMOS design benefits from this trend as well, due to
improved high-frequency properties. Typical RF circuits that used to be designed in
technologies such as silicon bipolar or gallium arsenide (GaAs) [74], [75] can now
be implemented in CMOS [10], [15], [17], [20].

Scaling
In order to maintain similar performance or even increase it with decreased channel
lengths, ideal MOSFET scaling (so-called constant field scaling) has been proposed
[76], [77], [78] as presented in the table below, where K is a scaling factor larger than
1.
TABLE 12. IDEAL SCALING OF SHORT-CHANNEL DEVICES

parameter scaling

L, gate length 1/K

W, gate width 1/K
tox, gate oxide thickness 1/K

xj, junction depth 1/K

Nsub, substrate dopant concentration K

VDD, supply (drain) voltage 1/K

ID, drain current 1/K

Vth, threshold voltage 1/K

The two parameters that deviate the most from ideal scaling are the supply voltage
VDD and the threshold voltage Vth. Scaling Vth increases the leakage current in digi-
tal circuits (see paragraph 4.2, weak-inversion region). Therefore neither VDD can be
scaled down as much as suggested in table 12.
The main problem with scaling down MOSFETs is the increased electric field in
the devices [71]. Several problems arise. First of all, velocity saturation occurs for
lower voltages. This can be modeled as a mobility reduction, where the effective
mobility, µeff, depends on the field strength [71]:
72 Part I. General Introduction

µ0
µ eff = ------------------------------------------
- (4.25)
1
1 + V eff ⋅ -------------------
L ⋅ E crit

where Ecrit is the critical field strength, above which the velocity has saturated. Typi-
cal values for Ecrit are 8x103 - 3x104 V/cm for electrons and 2x104 - 105 V/cm for
holes [71]. As was seen in Eq. (4.21), fT is related to µeff, so for decreasing channel
lengths fT will gradually lose its dependence on Veff and will be inversely propor-
tional to L rather than L2. A second effect of the high field strengths is punchthrough,
where, somewhat simplified, the source and drain depletion region are extended so
that they touch each other [71]. This can be prevented by increased doping in the
channel. A third problem is the hot-carrier effect. In the case of an NMOSFET, elec-
trons in the channel gain enough energy to enter the gate oxide and thus charge it.
This will eventually degrade the device, as Vth increases and gm decreases. More-
over, some electrons may cross the gate oxide, resulting in a gate current. Also
impact ionization may exist, resulting in more electron/hole pairs close to the drain
(so-called ’weak avalanche’). The holes will be transported to the substrate, resulting
in a drain-to-substrate current. Two possible remedies to prevent the hot carrier effect
are a lightly doped drain area (LDD) and a double doped drain area (DDD) [69].
Fourthly, the depletion region is extended deeper into the substrate, and especially if
VDS > 0 the depletion region around the drain will extend towards the source deple-
tion region (see Fig. 4.10). This causes barrier reduction, and is known as drain-
induced barrier lowering (DIBL) [30], [71]. As a consequence the threshold voltage
Vth is reduced and becomes dependent on vDS. It affects the output impedance.
The gate oxide may break down if the electric field across it becomes too high.
The reduction of oxide thickness has led to a lower breakdown voltage, which in its
turn has forced a reduction of VDD, although this reduction does not follow the scal-

VG

VS VD

depletion region
n+ n+

p substrate (bulk)

Fig. 4.10. Illustration of the depletion region in a short-channel

MOSFET.
Chapter 4 RF CMOS Technology Aspects 73

ing presented in table 12. For even thinner gate oxides direct tunneling may become
a problem [77].

4.3. NOISE SOURCES IN A MOSFET

In this section noise sources in a MOSFET will be discussed as well as a MOSFET
noise model.

4.3.1. MOSFET NOISE SOURCES

Since the channel resistance is in fact a physical resistance, a thermal noise current
of

2
i n = 4kTγ g d0 (4.26)
2
can be associated to it [29], where gd0 is the channel conductance for VDS=0, and i n
is the spectral noise power density in [A2/Hz]. T is the absolute temperature and k is
Boltzmann’s constant. For a high-resistivity substrate one can assume gd0=gm, but
for a low-resistivity substrate the ratio g d0 ⁄ g m will become larger than 1 [29], imply-
ing an increased noise current for equal gm.
In the triode region γ is equal to 1, so that with Eq. (4.26)

2
i n, triode = 4kT g d0 (4.27)

while in the saturation region γ can be as low as 2/3 for a long-channel device and as
high as 4 for a short-channel device. In addition to channel length, this parameter is
dependent on biasing conditions. Values of γ have been deduced from measurements
[79].
The so-called induced gate noise also originates from the random movements of
the charges in the channel, but is capacitively coupled from the channel to the gate
[29], [71]. This noise can be expressed as [29]
2 2
2 ω C GS
i n, ig ≈ 4kT ----------------- (4.28)
3g m

Because of the term ω2 in the denominator this noise is a problem mainly for high
frequencies, but may also be problematic in LNAs where high-Q inductive source
degeneration is used [80].
The gate leakage current IG tunneling through the reverse-biased source-sub-
strate junction causes shot noise, which is best represented as a current source at the
gate of value
74 Part I. General Introduction

2
i n, leak = 2qI G (4.29)

Especially for long-channel devices this leakage current is usually quite small.
Therefore this noise source is commonly neglected.
Flicker noise (or 1/f noise) is believed to occur due to the Si-SiO2 interface [70],
[29]. Carriers can be trapped in empty bonds at the silicon surface, and released
again randomly. Since the flicker noise power is dependent on the ‘cleanness’ of the
interface, this noise can differ from wafer to wafer and from process to process. If
there is no bias current, no 1/f noise is seen either. The flicker noise can be modeled
as a voltage source in series with the gate as

2 K 1
v n, 1 ⁄ f = ----------------- --- (4.30)
C ox WL f

where K is a process dependent constant. This constant is larger for NMOSFETs

than for PMOSFETs, and the latter thus have a better 1/f noise performance.
MOSFETs have more 1/f noise than bipolar devices, and the noise is larger for mod-
ern CMOS technologies than for older ones. Even though this is a low-frequency
phenomenon, it is important in RF circuits, because in non-linear circuits such as
VCOs and mixers the noise is transformed to higher frequencies. Moreover, the 1/f
noise may disturb the downconverted signal, as was pointed out in chapter 2. To cir-
cumvent the 1/f noise problem passive CMOS mixers may be used.
Noise is also generated in the gate resistance, according to

2
v n, gate = 4kT R g (4.31)

Note that this noise source is highly dependent on the layout: a multi-finger structure
will reduce the gate resistance and thereby the noise voltage as well.

4.3.2. MOSFET NOISE MODEL

In the MOSFET noise model the noise sources mentioned in paragraph 4.4.1 are
taken into account: thermal noise due to the channel resistance, induced gate noise,
1/f noise (modeled as a current source), the gate leakage current noise and gate resis-
tance noise (see Fig. 4.11). The thermal noise of the resistances rs and rd (see Fig.
4.9) are neglected here. The power spectral densities of the noise sources are
repeated here:

2
i n, d = 4kTγ g d0 (4.32)

2 K 1 2
i n, 1 ⁄ f = ----------------- --- g m (4.33)
C ox WL f
Chapter 4 RF CMOS Technology Aspects 75

CGD
G vn,g RG D
+ gmvgs
vgs
rds
in,leak CGS in,d
in,ig- in,1/f

Fig. 4.11. A simplified MOSFET noise model.

2
v n, g = 4kT R g (4.34)

2
i n, leak = 2qI G (4.35)
2 2
2 ω C GS
i n, ig ≈ 4kT ----------------- (4.36)
3g m

The flicker noise can be modeled as a voltage source in series with the gate (see
previous section), but is more often modeled as a current noise source from drain to
source. To indicate the power of the flicker noise relative to the thermal noise, a
flicker noise corner frequency is defined as the crossing point of the spectral density
curves, see Fig. 4.12. Using Eq. 4.32 and Eq. 4.33, this corner frequency fc can be
expressed as:
2
K gm
fc = --------------------------------------
- (4.37)
4kTγC ox WLg d0

From Eq. 4.32, Eq. 4.33 and Eq. 4.6 it can be seen that MOSFET design param-
eters W and L may be used to decrease the 1/f noise while keeping the channel ther-
mal noise constant, by increasing the product WL and keeping the ratio W/L
constant. The reduced 1/f noise will, however, come at the cost of increased parasitic
capacitance (Eq. 4.18).

in2/∆f
[log]

fc f [log]
Fig. 4.12. The flicker noise corner frequency.
76 Part I. General Introduction

4.4. MONOLITHIC INDUCTORS IN CMOS TECHNOLOGY

Monolithic inductors are crucial elements in RF integrated circuits, where they typi-
cally are used in frequency selective circuits such as tuned LNAs, VCOs, PAs, and
possibly mixers. High quality factors (Q) are hard to achieve in a standard CMOS
technology. In this section the physical background will be discussed as well as basic
inductor modeling.

4.4.1. MONOLITHIC INDUCTOR PHYSICS

Inductors may be realized in integrated circuits by a simple metal wire on a more or
less insulating layer. The main problems of integrated inductors are the limited qual-
ity factor (Q) that may be achieved in CMOS technologies, limited inductance val-
ues, as well as the relatively large area they consume. Moreover, modeling of
inductors is not straightforward, as will be shown in the next paragraph.
The inductance and Q depend on various factors such as frequency, geometry of
the metal wire, properties of the metal and the insulating layer, and properties of the
substrate. In a CMOS VLSI technology the Si substrate generally is heavily doped,
i.e. lossy compared to a more lightly doped Si bipolar substrate [81]. This typically
limits the Q to be less than 10, while discrete inductors can reach a Q of 100 and
bondwires between 25 and 50.
The most common geometry for an integrated inductor is depicted in Fig. 4.13
[81], [30]. Between closely positioned segments with a current flow in the same
direction, e.g. no. 1 and 5 in Fig. 4.13a, positive mutual inductance exists, which
adds to the total inductance, while between segments with opposite current flow, e.g.
no. 1 and 3 in Fig. 4.13a, negative mutual inductance exists which decreases the total
inductance [82]. However, since segment 1 and 3 are quite far apart, the negative
mutual inductance will be quite small. The inner turns of a planar inductor hardly
S
4 W=width
S=spacing

3 5 1
2r windings (top metal)

oxide
substrate
underpass
(metal)

2 W
(through-cut)
a. b.
Fig. 4.13. A typical inductor layout, a). top view, b). through-cut view.
Chapter 4 RF CMOS Technology Aspects 77

contribute to the total inductance, while they add to the parasitics. Therefore, so-
called hollow spiral inductors are generally used [84].
The most important non-idealities are loss resistance in the metal wire, capaci-
tance between the metal wire and the substrate, and finite substrate resistance which
may cause ohmic losses in the substrate. Moreover, so-called eddy currents may
counteract the magnetic field and cause more losses, thus reducing the inductance
and the Q. The skin effect, i.e. concentration of current in the outer region of the con-
ductor, causes an increasing resistance at high frequencies approximately propor-
tional to f .
Several techniques have been used to increase the Q of integrated inductors:
• Etching the substrate [83] - the capacitance and the substrate losses are reduced;
• Placing a patterned grounded shield underneath [85] - substrate losses and the
image current are reduced;
• Using copper wires instead of aluminum [81] - the series resistance of the wire is
reduced;
• Using shunted multilayer inductors [86] - the series resistance is reduced; How-
ever, the capacitances increase.
• Using stacked (series) multi-layer inductors [89], [87] - the mutual inductance is
increased and the area for a certain inductance value is decreased; However, the
capacitances increase.
• Using an extra thick top metal layer - the series resistance is reduced;
• Adding a BCB (Benzocyclobutene) layer [88] - substrate losses are reduced.
Some of these techniques require extra processing steps, which is undesirable if at all
feasible.
In recent years, CMOS processes have developed in order to provide better RF
performance, for instance by having an extra thick top metal layer and a more lightly
doped substrate. Inductors with Q factors as high as 15 may then be designed.

4.4.2. MONOLITHIC INDUCTOR MODELING

For the circuit designer it is desirable to have a simple and accurate lumped-element
inductor model, so that circuit simulations will not become too time-consuming.
Moreover, a scalable model would give the designer flexibility in inductance value
and other properties. However, as it is now, for each technology models are typically
only available for a few inductor structures. These models are provided by the IC
foundry, not chosen by the designer.
78 Part I. General Introduction

A suitable lumped-element inductor model is shown in Fig. 4.14. Several meth-

ods may be used to arrive at this model from the structure shown in Fig. 4.15. Firstly,
electromagnetic field solvers may be used to simulate properties of wires or more
complicated structures. Simulation time and memory requirements limit the accu-
racy of the simulation and the complexity of the structures that may be simulated.
The parameters of a lumped-element model may then be fitted to the field solver
result, or alternatively to measurement results. Secondly, the properties and dimen-
sions of the metal wire, insulating layer and substrate may be used to estimate the
model parameters. This will be discussed below.
For the planar rectangular inductor shown in Fig. 4.13, one way to estimate the
total inductance Ls is to add the inductances of all segments
Z
LS = ∑ Li + ∑ M + – ∑ M - (4.38)
i=1

where Li is the inductance of segment i, Z is the total number of segments, and ∑ M +

and ∑ M - are the total positive and negative mutual inductance between all seg-
ments, respectively [82]. Li (in nH) is given by
2l i (W + d )
L i = 0.2 ⋅ l i ln  -------------- + 0.50049 + ------------------- (4.39)
 W + d 3l i

where li is the length of segment i in mm. This is the self-inductance of a metal wire
at low frequency, and a relative magnetic permeability µr of 1. For the mutual induc-
tance equations can be found in [82]. Other equations to calculate the total induc-
tance have been presented as well (see [30], [82]). The inductance value is dependent
on the total wire length l, the spacing s between the windings, the width W of the
wire, the thickness d of the metal layer, the number of turns N and the radius r of the
inductor.

Cp

Rs
LS
Cox1 Cox2
R12

Csub,1 Rsub,1 Rsub,2 Csub,2

Fig. 4.14. A standard lumped-element inductor model.

Chapter 4 RF CMOS Technology Aspects 79

Some simple equations will now be given to complete the model in Fig. 4.14.
These equations do not take into account all aspects, but give an idea of how material
properties and inductor dimensions influence the parasitic elements. For more elabo-
rate inductor modeling see [90], [91], [92] and [93].
The series resistance Rs is the physical resistance of the wire, and is thus depen-
dent on the width W, the length l, the metal thickness d, and the type of metal:
l
R S, 0 = ------------ (4.40)
σWd
where σ is the conductivity of the metal. If the skin effect is included, this resistance
can be expressed as
l
R S = ------------------------------ (4.41)
2σδ ( W + d )
where the (frequency dependent) skin depth δ is

1
δ = ------------- (4.42)
πfµσ
and µ is the magnetic permeability. In Eq. 4.41 it is assumed that δ « d and δ « W .
The capacitance CP from port 1 to port 2 is related to the physical capacitance
between the two ports, i.e. the underpass to take out the signal at the inner node (see
Fig. 4.13):
ε ox
C p = ( N – 1 )W 2 ⋅ --------- (4.43)
t ox1

where tox1 is the oxide thickness between the two metal layers (see Fig. 4.15). The
parasitic fringe capacitance [70], which often is larger than the capacitance of the
underpass, is neglected here.
The two parasitic capacitances Cox1 and Cox2 are mainly due to the oxide capac-
itance between metal and substrate, which may be approximated by

d
W S

tox oxide tox1

tox2

tsub
substrate

Fig. 4.15. Detailed through-cut view of a planar rectangular inductor.

80 Part I. General Introduction

ε ox
C ox, tot = ------- ⋅ A spiral (4.44)
t ox

and
ε ox
C underpass = --------- ⋅ A underpass (4.45)
t ox2

where Aspiral is the area of the top metal wire, tox is the oxide thickness between the
top metal and the substrate, Aunderpass is the area of the underpass and tox2 is the
oxide thickness between the underpass and the substrate. Thus
1 1
C ox1 = --- C ox, tot + C underpass and C ox2 = --- C ox, tot . (4.46)
2 2
The substrate is modeled as:
ε sub 1
C sub ( 1, 2 ) = --------- ⋅ --- ⋅ A spiral (4.47)
t sub 2

2t sub
R sub ( 1, 2 ) = ρ sub ⋅ ---------------- (4.48)
A spiral

where εsub and tsub are the permittivity and the thickness, respectively, of the sub-
strate, and ρsub is the resistivity of the substrate. If an epitaxial layer is present the
substrate parameters should be replaced by the parameters of the epitaxial layer.
The losses due to eddy currents are not part of the model. They can be included
by adding a mutual inductance coupled to a resistor, with a value dependent on the
inductor geometry and substrate conductivity.

Quality Factor and Self-Resonance

The inductor Q (see for example [85]) is determined by the metal losses and by the
substrate losses. The plot of Qind versus frequency shows a peak at a frequency f0,
which can be tuned to the desired operating frequency, if the inductor is designed
with care.
The self-resonance frequency fSR is determined by the total capacitance at the
inductor nodes and LS. Often fSR must be a factor 2 to 3 higher than the operating fre-
quency of the circuit, in order to allow for other parasitic capacitances, or in case of a
VCO, to allow for a certain tuning range. This requirement may contradict the desire
to have maximum inductor Q at the operating frequency. For applications in the low-
GHz range, such as GSM, Bluetooth, UMTS, et cetera, it is hard to get high Q values
for inductors larger than 10 nH.
CHAPTER 5

CONCLUSIONS

As a result of the rapid development of mobile communication systems in the low

GHz range and the high-frequency capabilities of modern CMOS technology, inter-
est in CMOS transceiver front-ends is increasing, and building blocks that previously
were made in other technologies are now more and more realized in CMOS. The
level of integration is increasing, and the move towards true systems-on-chip (SoC)
is clear. This brings about disturbance issues, as building blocks on the same chip
may influence each other. Moreover, the use of high-quality external filters is
avoided, which may lead to increased interference both from other transceiver build-
ing blocks and from external signals. In this work a brief overview was given of
receiver and transmitter architectures, and the impact of system specifications and
choice of architecture on building blocks was analyzed.
One of the most challenging building blocks in a CMOS transceiver is the power
amplifier. A brief overview of PA issues such as efficiency and linearity was given.
Transistor modeling is a critical aspect of RF CMOS design. The drive towards ever
smaller devices complicates this, especially for analog, high-frequency and large-
signal design. Also, in inductor modeling a more designer-friendly model is desir-
able.

The papers included in this work relate to many of the above aspects. Paper I, II and
III are focused on receiver front-ends. Paper I describes the design of a DCS receiver
with LNA, mixer and VCO integrated on the same chip. Paper II addresses the
design, implementation and measurement of a low-IF GSM receiver front-end. In
paper III an analysis is presented of spurious signals in a receiver and the effect on
choice of intermediate frequency (IF).
Paper IV and V both deal with transmitter aspects. In paper IV the design of a
class AB power amplifier with power control is presented, and in paper V the design

81
82 Part I. General Introduction

and measurement of a class C power amplifier with internal frequency doubling and
on-chip VCO is described.

FUTURE WORK
The development of mobile communication systems is towards higher frequencies,
as well as more broadband systems. On the other hand, old and new communication
systems will coexist for quite some time. For CMOS transceiver design this implies a
targeting of higher frequencies, facilitated by technology development, and imple-
mentation of flexible transceivers so that a user may have one device to communicate
in various systems.
The decreasing supply voltage will demand new solutions for well-known prob-
lems. This process is, of course, on-going, and includes technology developments,
new system specifications, and new design solutions for architectures and building
blocks.
Transistor and inductor modeling remain challenging; good and reliable models
are a necessity for the RF designer, even though architecture solutions such as feed-
back loops and control signals may alleviate some problems. However, this increase
in complexity does not always come for free.
 83

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 Part II

Included Papers
94 Part II. Included Papers
Included Papers 95

SUMMARY OF INCLUDED PAPERS

In this section a short summary will be given of each paper, and the author’s contri-
bution to each paper is listed.

I. In this paper the design of a CMOS receiver front-end is presented that meets the
DCS requirements. It includes a low-noise amplifier, a mixer and a fully inte-
grated voltage controlled oscillator.

Contribution: Design, manuscript.

II. This paper addresses the design and measurement of a fully integrated GSM
receiver front-end, which performs image rejection, channel selection, and
resists GSM blocking signals. a controllable gain of more than 100 dB is
achieved.

Contribution: Design of some blocks (PGA, 2nd downconversion mixer), some

analysis (interfering signals).

III. An analysis is made of the impact of spurious signals in a receiver. It leads to an

optimal choice of intermediate frequency for a fully integrated receiver, and is
supported by measurement results on a GSM receiver front-end.

Contribution: Analysis, most of the manuscript.

IV. The design of a fully integrated CMOS power amplifier is described. The ampli-
fier uses parallel output stages in order to optimize the efficiency for both high
and low output power levels.

Contribution: Design, manuscript.

V. In this paper the design and measurement results are presented of a fully inte-
grated CMOS power amplifier, suitable for direct-conversion transmitters or
low-IF upconversion. The amplifier uses internal frequency doubling.

Contribution: Design, measurements, manuscript.

96 Part II. Included Papers
PAPER I
PAPER I

A 0.35 µm CMOS DCS Front-end with Fully Integrated

VCO

Abstract
The design of a 0.35 µm CMOS front-end is presented which meets the DCS
requirements. The front-end consists of a low-noise amplifier operating at 1.85 GHz,
a mixer downconverting the RF signal to an IF of up to 250 MHz, and a fully inte-
grated voltage controlled oscillator with a tuning range of 460 MHz. The total power
consumption is 34 mW with a 2.5V supply, and the simulated maximum RF to IF
gain is 26.6 dB.

Based on: E. Cijvat, “A 0.35 µm CMOS DCS Front-end with Fully Integrated
VCO”. © 2004 IEEE. Reprinted, with permission, from Proceedings of the 8th
IEEE International Conference on Electronics, Circuits and Systems (ICECS)
2001, pp. 1595 - 1598. Malta, September 2001.

99
100 Part II. Included Papers
Paper I A 0.35 mm CMOS DCS Front-end with Fully Integrated VCO 101

1. Introduction
Recently the market for wireless applications has shown tremendous growth, result-
ing in an increase in research and development of low-cost RF integrated circuits. It
has been shown previously [1 - 4] that CMOS has the potential to be used for low-
GHz cellular communication applications. The advantage of CMOS compared to
other technologies, such as for instance silicon bipolar (Si BJT) or III - V based tech-
nologies, is that a higher level of integration can be achieved by having the radio fre-
quency (RF), intermediate frequency (IF) and baseband part of a transceiver on a
single chip.
An important aspect for a handset is battery lifetime. To extend this, overall
power consumption must be minimized. Since external components weigh heavily
on the costs of a handset, one of the goals of this design is to reduce the number of
external components.
In this paper a CMOS downconversion front-end is described that meets the
DCS-1800 specifications [5] for a handset receiver, which are to a large extent simi-
lar to the ones for GSM-900. Differences are for example the frequency band of
operation (1805 to 1880 MHz for a DCS handset receiver) and details in the blocking
specification.
The front-end comprises a low-noise amplifier (LNA), a downconversion mixer
and a fully integrated CMOS voltage controlled oscillator (VCO). An 1850 MHz
LNA with switchable gain is described, as well as a Gilbert-cell type mixer that
downconverts the RF (radio frequency) signal to an IF (intermediate frequency) of
up to 250 MHz. The third block described is a VCO with a tuning range of 460 MHz,
which provides the local oscillator (LO) signal to the mixer. According to simula-
tions this VCO meets the DCS phase noise requirements. A 0.35 µm BiCMOS tech-
nology, of which only CMOS transistors are used, is utilized for the design.
This paper is organized as follows: in Section 2 system aspects will be explained
briefly, as well as their implications for the front-end subcircuits. In Section 3 the
design of the LNA, mixer and VCO will be discussed. Simulation results will be pre-
sented in Section 4, and Section 5 contains the conclusions.

2. System Aspects
The channel bandwidth for the DCS system is 200 kHz. With direct downconver-
sion, the 1/f noise of the mixer would impair the signal-to-noise ratio (SNR). With
dual downconversion, more gain can be implemented before downconversion to
baseband, alleviating this problem. A second advantage of dual downconversion is
102 Part II. Included Papers

IF
BPF Poly-
baseband
phase
RF LNA LOI

VCO

This front-end
LOQ

Fig. 1. Receiver architecture

that it facilitates gain distribution over the full receiver chain [6], so that noise and
linearity can be better optimized and stability problems can be reduced.
To reduce the number of external components, no filter is used between the LNA
and mixer. This implies that neither the output impedance of the LNA or the input
impedance of the mixer needs to be matched to the impedance of a discrete filter. A
discrete band pass filter (BPF) following the antenna is assumed to be present.
To achieve sufficient image rejection a quadrature mixer in combination with a
polyphase filter can be used [1], as indicated in Fig. 1. The VCO quadrature signal
can be generated by using a polyphase network [2, 3] as well.
Since the DCS noise requirements are stringent, high gain in the RF part of the
receiver is important. This includes the mixer, which therefore should be active.
However, a high gain in the RF part can compromise the total linearity of the
receiver. System simulations have shown that a switchable LNA gain (5 or 20 dB
gain) and a limited mixer gain (5 dB) are sufficient for the receiver to meet the DCS
noise and linearity requirements, assuming reasonable noise and linearity perfor-
mance of subsequent blocks.
High-side injection is chosen for the downconversion, so that the VCO must be
tunable from roughly 1.95 to 2.15 GHz, leaving some flexibility to choose the IF.
The choice for high-side injection is based on two arguments. Firstly, if a GSM/
DCS dual-mode receiver is designed, the VCO can be used for the downconversion
of the GSM signal as well by increasing the tuning range beyond 2.15 GHz and
using a divide-by-2 circuit. An advantage of this strategy is that the phase noise per-
formance of the divided signal will improve with approximately 6 dB [6]. Secondly,
since no filter is present between the LNA and mixer, interferers will not be sup-
pressed except by the discrete BPF and the roll-off of the LNA. Thus the interferers
may be downconverted with harmonics of the LO, possibly distorting the desired
signal. High-side injection moves these LO harmonics to higher frequencies.
The front-end was modeled to analyse the effect of interferers and harmonic
downconversion [7], taking into account the DCS interferer (blocker) spectrum, BPF
Paper I A 0.35 mm CMOS DCS Front-end with Fully Integrated VCO 103

and LNA roll-off, building block linearity, LO harmonics etc. It was found that for an
IF of 235 - 250 MHz, using high-side injection, the desired signal will not be dis-
torted significantly, i.e. the required bit error rate (BER) for DCS will be met.

3. Circuit Design
3.1. The LNA
The LNA consists of a single-ended, cascoded, inductively degenerated common-
source stage, with an off-chip input tuning network to achieve a 50 Ω input imped-
ance [3, 4]. Parasitics at the input node (originating from bonding wire, pad, pin etc.)
are included in this network. Assuming certain boundary conditions a trade-off exists
between the noise figure and linearity of the LNA with respect to the quality factor Q
of this network, since a high Q yields a better noise figure but decreases the IIP3
assuming equal biasing conditions.
The LNA is loaded with an integrated inductor, tuning the maximum gain to
1.85 GHz. The parallel capacitor in Fig. 2 is formed by parasitic capacitances at the
output node. A voltage gain of around 20 dB is pursued. A resistor, controlled by a
switch, can be used to change the gain to a lower setting of about 5 dB (see Fig. 2).

7.4nH

out
Vb
M2
23nH
in M1

1.5nH

Fig. 2. Schematic of the 1.85 GHz LNA

Two parallel bondwires at the source of M1 provide inductive source degeneration.

3.2. The mixer

Two mixers have been compared: a single-balanced and a double-balanced Gilbert-
cell type mixer. The main advantage of a double-balanced mixer is a first-order can-
cellation of LO feedthrough. Depending on the sensitivity of the IF building blocks
for an undesired signal at fLO, a double-balanced mixer - with one input AC
grounded - may be preferable over a single-balanced mixer.
The main advantage of the single-balanced mixer is that a lower power con-
sumption is needed to achieve similar gain, linearity and noise performance.
104 Part II. Included Papers

RL RL
- IF IF +

LO-
LO+ M3 M4 M5 M6 LO+

P Q
RF+ RF-
+ M1 M2
vRF
-

Fig. 3. Schematic of the double-balanced mixer

However, since no filter is present after the mixer, a double-balanced mixer is

utilized in this front-end (see Fig. 3).

3.3. The VCO

The VCO consists of a differential switching NMOS pair with a tail current source
(see Fig. 4). Issues of 1/f noise vs. thermal noise, while considering the DCS phase
noise requirements, have guided the choice for this architecture. The VCO is AC
coupled to a buffer, which drives the LO ports of the mixer and provides some isola-
tion between the VCO core and the mixer.
The inductive load is a differential octagonal inductor with a polysilicon
grounded shield used to prevent the occurrence of image currents in the substrate [8].
With the available technology and careful layout a quality factor as high as 10 can be
achieved.
Tuning is achieved partly by a varactor, partly by switch-controlled capacitors,
the latter for discrete steps in carrier frequency. Thus the relative amount of varactor
capacitance is kept small, so that the degradation in phase noise performance, due to
degradation in quality factor of the total capacitance, will be small as well. The total
tuning range is 460 MHz utilizing 4 discrete steps.

5 nH
varactor LO-
LO+

LO+ M1 M2 LO-

vvarac
Vbias

Fig. 4. Schematic of the VCO

Paper I A 0.35 mm CMOS DCS Front-end with Fully Integrated VCO 105

4. Simulation Results
Both the complete front-end and the individual building blocks have been simulated
using SpectreRF. With a mixer IIP3 of 10 dBm (see Fig. 5), an LNA IIP3 of 0 dBm
and 21 dB of voltage gain preceding the mixer, the front-end IIP3 is expected to be
somewhat below -11 dBm. This was confirmed in front-end simulations.

20

0
Pout (@IF) [dBm]
Fundamental @ 175MHz
-20

-40

-60

-80

-100
3rd harm. @ 150MHz
-120

-140
-50 -40 -30 -20 -10 0 10
Pin (@RF) [dBm]

Fig. 5. Simulated IIP3 of double-balanced mixer

Assuming the BPF has an insertion loss of 2.5 dB, this will result in a total front-
end IIP3 of -6.3 dBm. Using the low-gain LNA setting will result in a higher total
IIP3.
The VCO meets the phase noise requirements for the DCS system, as is illus-
trated in Fig. 6.

Fig. 6. VCO phase noise, with markers indicating

the critical 3MHz frequency offset points

The maximum gain for the total front-end is 26.6 dB. Some loss occurs due to
the capacitive coupling between the LNA and mixer. The total power consumption is
34 mW. The results for the front-end building blocks are summarized in table 1.
A layout of the front-end (see Fig. 7) will be sent to fabrication. For the purpose
of measurements an open-drain buffer is added at the output of the mixer.
106 Part II. Included Papers

TABLE 1. FRONT-END SIMULATION RESULTS

LNA gain (voltage) 22/8 dB

NF 1.8 dB (high gain)
IIP3 0 dBm (high gain)
S11 < -12.7dB
power cons. 8.8 mW

mixer gain (voltage) 5.6 dB

NF (SSB) 14 dB
IIP3 9.9 dBm
power cons. 10.5 mW

VCO tuning range 460 MHz (1940-2400)

phase noise -138.6 dBc/Hz @3MHz
power cons. 14.8 mW (incl. buffer)

5. Conclusion
A 0.35 µm CMOS front-end has been described, meeting the requirements for a
DCS receiver according to simulations. The front-end consists of a low-noise ampli-
fier operating at 1.85 GHz, a mixer that downconverts the RF signal to an intermedi-
ate frequency of up to 250 MHz, and a voltage controlled oscillator with a tuning
range of 460 MHz. Moreover, the VCO is fully integrated and meets the DCS phase
noise requirements.

mixer
LNA

VCO
buffer

Fig. 7. Layout of the front-end

Paper I A 0.35 mm CMOS DCS Front-end with Fully Integrated VCO 107

This front-end does not entail a - generally discrete - filter between LNA and
mixer. Thus, the number of external components is reduced while dual downconver-
sion is utilized.

ACKNOWLEDGEMENTS
The help of Shahrzad Tadjpour, Emad Hegazi and Jaesup Lee (University of Califor-
nia, Los Angeles, USA) and Henrik Sjöland (Lund University, Sweden) is greatly
appreciated. The author is indebted to the Dept. of Microelectronics and Information
Technology, Royal Institute of Technology (Stockholm, Sweden) for their financial
support.

REFERENCES
[1]. F. Behbahani, Y. Kishigami, J. Leete and A.A. Abidi, “CMOS 10 MHz-IF
downconverter with on-chip broadband circuit for large image-suppression”, in
Digest of Technical Papers of the 1999 Symposium on VLSI Circuits, Kyoto,
Japan, June 1999, pp. 83-6.
[2]. M. Steyaert, J. Janssen, B. De Muer, M. Borremans and N. Itoh, “A 2V CMOS
Cellular Transceiver Front-End”, IEEE Journal of Solid State Circuits, Vol. 35,
No. 12, December 2000, pp. 1895-1907.
[3]. S. Tadjpour, E. Cijvat, E. Hegazi and A.A Abidi, “A 900 MHz Dual Conversion,
Low-IF GSM Receiver in 0.35-µm CMOS”, in Technical Digest of the 2001
IEEE Solid State Circuits Conference (ISSCC), San Francisco, CA, February
2001, pp. 292-3.
[4]. P. Orsatti, F. Piazza, and Q. Huang, “A 20-mA-Receive, 55-mA-Transmit, Sin-
gle-Chip GSM Transceiver in 0.25-µm CMOS”, IEEE Journal of Solid State
Circuits, Vol. 34, No. 12, December 1999, pp. 1869-80.
[5]. GSM Technical Specification 05.05, European Telecommunications Standards
Institute, Sophia Antipolis, France, 1992.
[6]. B. Razavi, RF Microelectronics, Prentice Hall PTR, Upper Saddle River, NJ,
1998.
[7]. R.C. Sagers, “Intercept Point and Undesired Responses”, IEEE Transactions on
Vehicular Technology, Vol. VT-32, No. 1, February 1983, pp. 121-33.
[8]. C.P. Yue and S. Wong, “On-Chip Spiral Inductors with Patterned Ground
Shields for Si-Based RF IC’s”, IEEE Journal of Solid State Circuits, Vol. 33,
No. 5, May 1998, pp. 743-52.
108 Part II. Included Papers
PAPER II
PAPER II

A 900 MHz Dual Conversion, Low-IF GSM Receiver in

0.35 um CMOS

Abstract
A low-power fully integrated GSM receiver is developed in 0.35-um CMOS. This
receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the
impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals.
The receiver includes all of circuits for analog channel selection, image rejection,
and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a
2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single fre-
quency synthesizer generates both LO frequencies. The integrated VCO with on-
chip resonator and buffers consume another 8 mA, and meet GSM phase-noise spec-
ifications.

Based on: S. Tadjpour, E. Cijvat, E. Hegazi and A. Abidi, “A 900 MHz Dual Con-
version, Low-IF GSM Receiver in 0.35 µm CMOS”. © 2004 IEEE. Reprinted,
with permission, from IEEE Journal of Solid-State Circuits, Vol. 36, No.12, pp.
1992 - 2002, Dec. 2001.

111
112 Part II. Included Papers
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 113

1. Introduction
Mobile wireless transceivers face relentless pressure for low cost, low power, and
small size. A highly integrated CMOS realization is therefore of interest. It is gener-
ally ac–cepted that RF-CMOS circuits are good for short-range communicators such
as DECT or Bluetooth, but whether CMOS can ever deliver a fully integrated
receiver with competitive performance for a challenging cellular standard such as
GSM continues to be debated. Previous bipolar or CMOS GSM transceivers use off-
chip components to reject the image and large blocking signals [1]-[3], or defer these
tasks to the baseband sections [4].
This paper describes a fully integrated CMOS GSM receiver, which we believe
is the more challenging half of the transceiver. The circuit includes on-chip image
rejection and channel selection filter. It meets the requirements of GSM, yet con-
sumes a power comparable to the lowest numbers reported in prior art. Section II
describes the GSM system requirements and briefly discusses three different receiver
architectures. Section III explains the proposed architecture and the rationale behind
it. The circuit design is covered in detail in Section IV, and finally, the experimental
results and the layout issues are presented in Section V.

2. System Description
The 900-MHz GSM standard [5] requires receive sensitivity of 102 dBm for a
GMSK modulated signal that occupies a 200-kHz-wide bandwidth. To obtain a sig-
nal-to-noise ratio (SNR) of 9 dB at the demodulator at the target bit-error rate (BER),
the noise figure (NF) at the antenna output must be at most 10 dB. Assuming 3-dB
insertion loss, and therefore NF, for the RF bandpass filter prior to the receiver input,
this yields an upper limit of 7 dB for NF of the receiver itself.
What distinguishes GSM from other well-known cellular standards is the
required receiver immunity to very large in-band signals, called blockers. Fig. 1
shows the blocking profile for the GSM standard. The receiver must function at the
target BER when the wanted channel is 3 dB above sensitivity level, and is accompa-
nied by blockers as strong as 100 dB larger. Receiver LO phase noise, image rejec-
tion, and 1-dB compression point all may be deduced from the blocking profile. To
pass the intermodulation test, a GSM signal 3 dB above the sensitivity level must be
detected by the receiver in the simultaneous presence of two blockers: a static sine-
wave, and a GMSK modulated signal at -49 dBm. With 9-dB SNR and a 3-dB mar-
gin, this means that receiver IIP3 must be at least -21 dBm. At the preselect filter
input, this corresponds to an IIP3 of about -18 dBm.
114 Part II. Included Papers

0
-10
-20
-30
-40
dBm

-50
-60
-70
-80 Wanted Channel
(minimum level)
-90
-100

900 910 920 930 940 950 960 970 980 990 1000
Frequency, MHz
Fig. 1. GSM blocker template.

Any assessment of candidate architectures for integrated receivers should begin

with direct conversion to zero IF. The direct conversion receiver eliminates image
reject and off-chip IF filters. Instead, two integrated active low-pass filters in I and Q
paths select the wanted channel. However, the narrow 200-kHz GMSK-modulated
GSM channel at zero IF contains significant energy at very low frequency, and there-
fore cannot tolerate LO leakage, dc offset or second-order distortion products [6]
without elaborate means to sense and remove these artifacts prior to demodulation.
Alternatively, downconversion to some low IF, such as 140 kHz, positions the
signal above dc, obviating most of the aforementioned problems [4]. DC offset can
be simply removed by a high-pass filter, and second-order distortion is not important
since blockers only generate components near dc, which will fall below the down-
converted signal spectrum. As in direct conversion, low-power active bandpass filters
can still select the wanted channel. However, unlike direct conversion, the image of
the downconverted adjacent or alternate channels can now dominate the channel of
interest (Fig. 2). GSM limits the adjacent channel to be 9 dB larger than the desired
signal, and the alternate channel to be 41 dB larger. The spectral tail of the GMSK
modulated alternate channel dominates the image at this low IF, requiring an image
rejection of 26 dB. Fortunately, this can be easily realized on-chip.
If low IF is attractive for a GSM receiver, what is the best frequency plan for
downconversion? Single conversion from RF to low IF is certainly the simplest [4].
However, an important though not well-appreciated limitation of this plan arises
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 115

frequency

Fig. 2. Downconverted GSM channel, images of adjacent and alternate channels,

and flicker noise.

from noise in the downconversion mixer. When translating a signal from a very high
to a very low frequency, a current-commutating CMOS mixer always suffers from
large flicker noise at its output [7]. This can submerge the weak received signal,
which lies at low IF at the mixer output. Flicker noise at the output is inversely pro-
portional to the product S x T, where S is the slope of the LO waveform at the instant
of commutation, and T is the LO period. Therefore, to lower flicker noise, the LO
period should be large and its waveform square-wave-like [7].
This favors a dual-conversion receiver. The entire GSM band is first downcon-
verted to a first IF of, say, about 100 MHz. In a conventional receiver, an off-chip IF
filter would partly suppress the in-band blocking signals to relax the required linear-
ity in the following stages. On a single-chip receiver, this is not a viable option. Now
strong blockers, only mildly suppressed by the antenna preselect filter, propagate
through the receiver circuits until finally attenuated in a baseband channel-select fil-
ter. This poses some problems previously unknown to superheterodyne receivers,
and ignored in previous work.
Consider, for example, dual conversion to zero IF. This suffers from second-
order distortion products at dc due to the blockers. For the GSM receiver, where the
in-band blocker 3 MHz away from the desired signal is 76 dB larger than the refer-
ence channel, this requires an IIP2 of at least 82 dBm in the baseband circuits [8].
Blockers may also translate to the IF through circuit nonlinearity and mixing
with LO harmonics [9]. This is important in GSM, which allows large blockers. For
example, a blocker lying at ( nω LO + ω IF ) ⁄ k , subject to kth-order nonlinearity in the
front end mixes with the nth LO overtone and downconverts to IF. Front-end linear-
ity, antenna filter selectivity, and the tuned load of the low-noise amplifier (LNA) all
determine how important this effect will be (Fig. 3). Depending on n and k the choice
of IF, the troublesome blockers might lie very close to the GSM band, in which case,
116 Part II. Included Papers

Fig. 3. Harmonic mixing and front-end nonlinearity translate the blocker (ωint) to
the same frequency as the desired signal.

preselect filtering before the receiver does not help. On the other hand, the correct IF
guarantees that all troublesome blockers lie far away from the GSM band. The typi-
cal preselect filter and the dominant second- or third-order distortion in the front-end
blocks imply that the combinations k = 2, n = 3 and k = 3, n = 5 are most problematic
with low-side LO injection, and k = 3, n = 2 for high-side LO injection. It follows
that with high-side LO injection, IF in the range 260-370 MHz is unsafe [10].
Incidentally, if the receiver front-end were perfectly linear, blockers at
nω LO −+ ω IF could still mix with LO overtones and downconvert to IF. The case of n
= 1 arises when the blocker lies at the image frequency. Nonlinearity in baseband cir-
cuit blocks prior to channel selection is also important. A blocker at ω LO + ω IF ⁄ m
downconverts to the IF subharmonic, and after suffering mth-order circuit nonlinear-
ity appears at IF. At low IF, this set of blockers may lie within the GSM band and
pass through the antenna preselect filter unattenuated. This enforces a minimum lin-
earity on the IF circuit blocks. For high-side LO injection, an IF higher than 170
MHz prevents this from occurring, and for low-side injection an IF higher than 260
MHz.
Based on these various considerations, with high-side LO injection the IF should
lie between 170-260 MHz to best suppress spurious downconversion of blockers.
There is no such safe region for low-side LO injection [10].

3. Receiver Architecture
Fig. 4 shows the proposed receiver, a dual conversion to low-IF architecture. The sig-
nal after low-noise amplification downconverts to a first IF (IF1). There, a program-
mable gain amplifier (PGA) boosts the wanted signal and close-in blockers, which
downconvert to a second, low IF (IF2) for most of the amplification and filtering in
the receiver.
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 117

The receiver is considerably simplified if the two LO frequencies driving mixers

at the first and second IF are derived from a single frequency synthesizer. With IF2
chosen at 140 kHz, this consideration narrows down IF1 to 190 MHz if it is to lie in
the safe region described above. Then, according to Fig. 1, the first image 380 MHz
away from the desired signal must be attenuated by 110 dB. A typical antenna prefil-
ter for GSM will suppress this image by about 55 dB in its stopband, which means
that an IF1 polyphase filter and the tuned load of the LNA must suppress it by
another 55 dB.
The gain of the single path (not quadrature) IF1 PGA is chosen so that blockers
do not overload the subsequent circuits and desensitize the receiver. Next, I and Q
mixers downconvert the GSM channel to IF2. Dual conversion improves receiver
NF, first by providing larger gain before the high-noise baseband section, and second
by driving the second mixers at a lower frequency, which reduces their output flicker
noise. An active polyphase filter at the IF2 serves the dual purpose of selection of the
desired channel, and rejection of the adjacent and image signals. This filter delivers
the wanted channel alone at its output in differential quadrature format. Variable gain
in the filter adjusts the signal level to lower dynamic range of the following simple
A/D converter. Analog channel selection as described here contrasts with most other
published GSM receiver ICs, which defer this task to a digital filter.
A high IF2 will lessen the impact of flicker noise in the baseband circuits, but
the image signal will be very large. Also, the channel-select filter at high IF2 will
consume more power. The second IF of 140 kHz is chosen as the best compromise
between image rejection, flicker noise, and power dissipation.
The two LO frequencies are ganged. A divide-by-6 circuit generates the LO2
frequency from the RF VCO. As the receiver tunes across the GSM band, IF 1 varies

Fig. 4. Architecture of this GSM receiver prototype.

118 Part II. Included Papers

by ±2.5 MHz in order for the wanted channel at IF2 to fall into the fixed passband of
the channel-select filter. This varying IF is only possible when the receiver does not
depend on a fixed off-chip filter. To tune across the 25-MHz-wide GSM band, the
first LO frequency varies by 30 MHz.
In this frequency plan, it is possible for the fifth overtone of LO2 to couple to the
receiver input through wirebond inductors, the substrate, or otherwise poor reverse
isolation. This overtone lies next to the desired signal, and comprises another strong
blocker at the input. As long as it is not so large as to desensitize the receiver, this
overtone downconverts to dc and along with other dc offset is rejected by the channel
select filter.
Gain is distributed between the various blocks to maintain the cascade NF below
6 dB at minimum detectable signal, and the cascade input IP3 below -15 dBm. A
large blocking signal at the input can potentially drive the receiver into compression,
lowering average gain, and raising receiver NF. On detecting a blocker, the receiver
gain is lowered to improve linearity. The circuits are designed so that cascade NF
degrades by no more than 2.5 dB at low gain, which is better than the 3-dB degrada–
tion allowed by the GSM standard.

4. CIRCUIT DESIGN
All circuits described here operate from a 2.5-V power supply.

A. Low-Noise Amplifier
The low noise amplifier is a single-ended inductively degenerated common-source
stage (Fig. 5). A large voltage gain in the reactive input matching network overcomes
FET noise, enabling low NF at low currents. The input impedance is sensitive to the
package and parasitic capacitors to ground. Stray capacitance at the gate of the LNA
transforms down the input resistance as follows:
2
C gs 2
Re [ Z in ] ≈ ----------------------------------------------------------------
2 2 2 2
-⋅R
2
R C gs C p ω + ( C gs + C p )
where R is the real part of the LNA input impedance to the right of the parasitic, and
Cgs is the gate-source capacitance. The larger the Cgs, the less the sensitivity to Cp.
Therefore, the input FET W/L is chosen to be a large 350/0.35 um, whose Cgs is
about 350 fF. With a wire-bond inductance of 2 nH, the real part of at the gate is 148
Ω. The estimated total parasitic capacitance to ground is about 1 pF, which lowers
the input re–sistance to 17 Ω. An off-chip LC matching circuit serving as a narrow-
band transformer restores this to 50 Ω. The large FET must be biased at low (Vgs -
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 119

Fig. 5. Common-source LNA circuit.

Vt) to limit the LNA current, but too low a value will lead to small fT and IP3. A bias
current of 4.5 mA gives a satisfactory compromise between these quantities.
An on-chip single layer metal-4 spiral inductor tunes the FET drain load to 1
GHz. Inductor Q at this frequency is about 6. Three switch-selectable resistors
placed across the inductor can vary the gain from 12 to 24 dB. The pMOS FET
switches of 160/0.35 um give low ON resistance and also improve load linearity.
This high-Q load inductor and the high-input matching network partly suppress the
image 380 MHz away.
The cascode FET M2 lowers Miller multiplication of the input FETs Cgd and
improves LNA reverse isolation. At high frequencies, junction capacitor Cdb of M1
raises the high frequency output noise due to M2. This capacitance is lowered by
merging the drain of the input device and the source of the cascode transistor, and
deleting metal contacts which are not required [11]. To lower noise due to spreading
resistance, the substrate is contacted close to the FET source junction.
The minimum LNA noise figure of 1.4 dB in the GSM band is obtained at a gain
of 25 dB. It rises to 1.6 dB when gain is lowered to 20 dB. Measured LNA IIP3 is +2
dBm.

B. RF Mixers
The RF mixers downconvert the input signal to 190 MHz. It is most straightforward
to drive a single-balanced mixer with the single-ended output of the LNA. A single-
balanced mixer realized by a standard differential pair suffers from LO feedthrough
120 Part II. Included Papers

Fig. 6. Double-balanced mixer circuit.

at the output. The feedthrough tone is larger than the downcon–verted RF signal in
the ratio ( V gs – V t ) ⁄ 2v RF , where vRF is the RF input to the mixer (tens of microvolts)
and Vgs - Vt is the gate overdrive on the mixer input FET (hundreds of millivolts). A
low-order on-chip filter cannot adequately suppress large LO feedthrough at 1.14
GHz while passing the desired signal at 190 MHz. One possibility is to use current
boosting [12], which lowers, although does not eliminate, LO feedthrough by steer-
ing bias current away from the switching differential pair; however, this is at the
expense of linearity.
A double-balanced mixer does not suffer from LO feedthrough, but needs a dif-
ferential input. A differential LNA was not considered because it requires a balun
prior to the receiver, whose insertion loss directly adds to the RX noise figure. Alter-
natively, two RF phase splitting buffers can follow the LNA, but they consume
power and degrade linearity. Instead, we chose to ac couple the single ended output
of the LNA to one input each of two double-balanced mixers, whose other inputs are
at ac ground (Fig. 6). Although each mixer’s single-ended noise figure is 3 dB higher
and the bias current is twice that of a single-ended mixer, this arrangement nulls LO
feedthrough and additive noise on the LO signal lines. Long-channel grounded-
source FETs at the mixer input improve linearity. Each mixer consumes 4 mA, and
its double-side-band (DSB) noise figure is 10 dB with respect to the noise in 50 Ω.
The subsequent polyphase filter rejects image noise in the mixer.

C. Polyphase Filter
Following the quadrature mixers, a passive RC polyphase filter passes the desired
signal with an insertion loss of 9 dB, and rejects the image by more than 40 dB rela-
tive to the de–sired signal. Three stagger-tuned stages (Fig. 7) are required to guaran-
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 121

Fig. 7. Three-stage passive RC polyphase filter.

tee this image rejection across the GSM band, with a safety margin of ±30% to cover
process spreads. The resistors in this filter are unsalicided polysilicon with the typi-
cal sheet resistance of 133 Ω/❏ and ±20% process variation, and capacitors are MIM
with 30-nm-thick oxide, which gives a density of 1 fF/um. The capacitor value varies
by about ±15% due to process spreads.
Passband loss in the polyphase filter is lowered by tapering up the resistance in
the last stages [13]. Resistance of 2 kΩ in the last stage trades off noise and signal
loss. The first stage uses a 2-kΩ resistor to prevent loading of the first mixer.
To reject the image by 40 dB, the components in the four branches of the filter
must match to 1%. Capacitors of 200 fF or larger, and resistors occupying an area of
at least 70 um2 will match to this accuracy.
The LO commutates the RF signal current with a square wave. While the main
harmonic of LOQ lags LOI in phase, the third harmonic of LOQ leads LOI. Certain
out-of-band blockers will mix with LO harmonics and downconvert on top of the
desired signal. The polyphase filter passes those mixer products possessing the same
sequence [17] as the desired signal, but rejects mixer products with the opposite
sequence, of which the image signal is the most obvious one. Specifically, with high-
side LO injection, the polyphase filter rejects the image at ω LO + ω IF and also block-
ers at 3ω LO – ω IF , 5ω LO + ω IF … . The additional suppression of this subset of block-
ers is a welcome bonus.

D. Programmable Gain Amplifier

A programmable gain amplifier (PGA) at IF1 adjusts receiver gain to limit the signal
level driving the second mixers. The PGA must be a wideband amplifier at the high
IF of 190 MHz, which as a practical matter can provide a few coarse steps of gain.
Fig. 8 shows the PGA circuit. The input FETs are sized as 120/0.35 um to lighten the
capacitive loading on the polyphase filter. The PGA should be very linear at the
122 Part II. Included Papers

Fig. 8. Programmable gain amplifier circuit.

intermediate nominal gain of 10 dB. At this gain, the input differential pair is degen-
erated with linear resistors. Resistor loads further improve linearity and lower noise.
To step up gain to 20 dB, nMOS switches bypass the degeneration resistors. Bias
current is steered away from the loads to improve headroom. A pMOS switch in par-
allel with the 400-Ω load resistor steps down gain to 10 dB. For 0-dB gain, switches
short the differential input to the differential output, while another switch opens the
connection to VDD. The input switch FET size of 12/0.35 um limits capacitor loading
on the polyphase filter, yet gives an acceptably low ON resistance of 180 Ω. The
PGA NF is 6 dB at maximum gain of 20 dB. For 8-dB gain, the PGA NF is 9 dB and
IIP3 is +19 dBm. The circuit drains 3 mA. The outputs of the PGA are ac coupled to
the next stage by two picofarad capacitors.

E. Second Mixers
Quadrature double-balanced second mixers downconvert the wanted GSM channel
to the IF2 of 140 kHz (Fig. 9). The 12-pF capacitor at each mixer’s output removes
high-frequency blockers as well as the signals upconverting to 380 MHz. The input
FETs are biased at a gate overdrive of 450 mV to handle amplified blocking signals
without gain compression. The outputs directly couple into the subsequent active fil-
ter.
A square-wave LO waveform switches the mixers to lower their output flicker
noise. The mixer is laid out to minimize parasitic capacitance at the tail of each dif-
ferential pair, which also helps to lower flicker noise [7]. The DSB noise figure is 11
dB relative to noise in a differential 100-Ω resistor, and flicker noise corner is below
40 kHz. The following active polyphase filter cancels image noise. Long-channel
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 123

Fig. 9. Second mixer circuit.

grounded source input FETs improve input IIP3 of the mixer to +15 dBm. Each
mixer drains 1.5 mA, and gives a conversion gain of 6 dB.

F. Active Polyphase Filter

At IF2, the image signal is only 280 kHz away from the wanted signal. After quadra-
ture downconversion, both lie at the second IF of 140 kHz but in opposite sequences.
The image consists of the lower adjacent and alternate channels, folded over and off-
set in frequency relative to the desired signal. Based on the modulated spectrum, the
image must be rejected by 26 dB (Fig. 10).
A single passive polyphase filter stage can notch the image by 20 dB or more
across a bandwidth as wide as 30% of the null frequency. Therefore, image rejection
from 20 to 260 kHz which spans one GSM channel centered at 140 kHz and 30%

Fig. 10. GSM reference channel downconverted to IF of 140 kHz, and images of the
left adjacent and left alternate channels that overlap it.
124 Part II. Included Papers

safety margin requires more than seven or eight stagger-tuned stages in cascade. This
raises the passband insertion loss to more than 10 dB, which is unacceptable.
An alternative is the active polyphase filter [14]. This filter’s frequency response
is defined by a linear shift of a low-pass characteristic along the frequency axis,
resulting in a bandpass filter with an arithmetically symmetric passband. A shift by
ω0 is obtained by transforming the Laplace variable s to (s - jω0). At the circuit level,
this means that each capacitor in a low-pass active RC prototype is replaced by the
composite structure shown in Fig. 11 to realize an admittance (s - jω0)C. This
requires quadrature signal paths.
In practice, component mismatch in the filter branches, or phase and amplitude
mismatch at the input of the filter, will limit image rejection. Any signal at the input
of the filter can be decomposed into two set of quadrature signals with opposite
sequences. The filterpasses one sequence and rejects the opposite sequence. The fre-
quency response to the wanted sequence is the shape of the filter passband on the
positive frequency axis, while to the unwanted sequence, it is the transition band and
stopband on the negative frequency axis. In case of quadrature errors in the input sig-
nals, the image signal can be decomposed into the unwanted sequence and a small
wanted sequence. The frequency response to the image is now a linear superposition
of the original filter response on the positive and negative frequency axes, weighted
by the ratio of the two sequences.
Active RC and switched-capacitor filters are realized with high-gain opamps and
linear resistors and capacitors, which makes them more linear than gm-C filters. The
active RC realization is chosen here to avoid an antialiasing filter. The sharper the fil-
ter transition band, the greater the image rejection 280 kHz away. Actual image
rejection will also be limited by imbalance in the quadrature mixers, and component

Fig. 11. Method to synthesize active bandpass polyphase filter from conventional
low-pass prototype.
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 125

mismatch in the two branches. The fifth-order Chebychev type-I filter constellation
gives 1-dB passband ripple, rejects the adjacent channel by 30 dB, and adequately
suppresses image frequencies falling in its transition band. The filter is realized by
cascading five stages of the type shown in Fig. 11.
Two-stage opamps drive the resistor loads (Fig. 12). Large FETs in the input
stage lower flicker noise. A Miller capacitor and series resistor compensate the
opamp to a unity-gain frequency of 33 MHz. The common-mode feedback (CMFB)
cir–cuit is also shown in Fig. 12. The two nMOS transistors sense the output voltage,
and the mirror forces equal current in the two pMOS transistors and drives the com-
mon-mode of the output nodes to the reference voltage. Long-channel pMOSFETs
give high gain. Each branch drains a current of 15 uA. The 1.2-pF capacitors com-
pensate the feedback loop consisting of the main opamp and CMFB amplifier.
The filter is tuned by a 5-bit array of switchable capacitors in parallel with a
fixed capacitor, which gives ±50% tuning range with 3% accuracy. Interleaving gain
and filtering in the cascade give the best results for the dynamic range. The adjust-
able gain before each stage can trade off filter noise and signal-induced overload. A
switch-selectable array of resistors at the input of each stage scales filter gain. This
prototype does not include an AGC loop, but makes available three pins for external
gain control. The resistors are weighted to produce linear-in-dB gain. Total filter
gain, determined by process-independent resistor ratios, varies by 60 dB. The filter
has a minimum noise figure of 26 dB at maximum gain. At intermediate gain, its
input IP3 to out-of-band tones which produce in-band intermodulation is +25 dBm.

Fig. 12. Two-stage opamp used in filter, and accompanying common-mode feedback
circuit.
126 Part II. Included Papers

G. Voltage Controlled Oscillator

A single voltage-controlled oscillator (VCO) generates both LO frequencies, and
complies with GSM phase noise requirements. The VCO is a tail-biased differential
LC oscillator (Fig. 13). MOS varactors tune the VCO frequency by 10%. The varac-
tors are laid out as 160 fingers of 2/0.35-um nMOSFETs. The inductors are octago-
nal spirals with patterned polysilicon shields, giving a Q of 8 at 1140 MHz. The
inductor is designed with a fast simulator that accurately captures all metal and sub-
strate losses [15]. The oscillator circuit is optimized for best phase noise at least
power consumption using an understanding of the physical mechanisms of phase
noise [16]. To lower flicker noise, the tail current source W x L is scaled up while
keeping W/L constant. FET Vgs-Vt is large for low transconductance, which lowers
thermal noise in the drain current. The FET is laid out as an array of nine annular
transistors in parallel to reduce the capacitance at the tail, which lowers flicker noise
upconversion gain [15]. The circuit consumes 3.4 mA from 2.5 V, and its phase noise
as simulated on Spectre-RF is -142 dBc/Hz at 3-MHz offset from 1.1 GHz.
Quadrature differential phases are needed to drive I and Q mixers. A quadrature
VCO [19] automatically creates all these phases. For the same phase noise, though,
the quadrature VCO must be biased at 12 mA. In this receiver, a passive polyphase
filter follows the VCO to split the differential output into differ–ential quadrature
phases. Unlike VCOs biased at high currents [4], here, the polyphase filter resistance
significantly loads the oscillator, and its 1-pF input capacitance strongly pulls oscil–
lation frequency. Lowering resonator inductance to restore the frequency raises
power consumption.
Two grounded source FETs with inductive loads buffer the differential VCO
output. A narrowband T-section capacitive transformer boosts the filter’s input

Fig. 13. 1.1-GHz VCO.

Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 127

Fig. 14. VCO buffer with capacitive impedance transformer.

impedance (Fig. 14). The inductor load of the buffer resonates with the capacitive
input of the passive polyphase filter (PPF) at 1.14 GHz to give a gain of 6 dB. The
buffer drains 2.7 mA. The polyphase filter attenuates the LO amplitude by about 10
dB. Two sets of buffers, consisting of inductively loaded differential pairs with 46-
nH series stacked inductors, boost the differential quadrature outputs of the
polyphase filter to drive the mixers. The inductors yield 1 kΩ impedance at 1140
MHz to lower bias current to 0.9 mA. The entire LO generator consumes 7.9 mA.

5. Experimental Results
Fig. 15 shows SPECTRE-RF simulations of the entire receiver. The receiver gain
from single-ended input to differential output is as high as 100 dB, and the cascade
noise figure is below 5 dB. Flicker noise was simulated throughout the design evolu-
tion using the following expression for gate-referred noise voltage:

2 K 1
v nf = ---- -----------------
f WLC ox

Fig. 15. Simulated frequency response and noise figure of receiver.

128 Part II. Included Papers

Fig. 16. Chip photograph.

In this technology, for nMOS is 8.2E -24 V2F, and for pMOS is 1.9E-24 V2F, and is
assumed constant at all bias voltages [18].
A receiver prototype is fabricated in 0.35-um CMOS in the STMicroelectronics
BiCMOS6M process. The chip (Fig. 16) consumes an area of 2.2 x 4 mm, the chan-
nel-select polyphase filter consuming almost half of this. Separate supply lines lower
interaction between the LNA and the rest of the receiver. Several ground pads are
down bonded to the package to lower stray inductance. Electrostatic discharge
(ESD) protection comprises two reverse-biased diodes connected to each pin of the
chip. The small diodes add little capacitance to the sensitive RF nodes, and are sepa-
rated by ground and rings to reduce the possibility of latchup. Symmetric layout
throughout the receiver guarantees required matching between and paths. Serpen–
tine metal lines of variable pitch equalize interconnect capacitance between mixer

Fig. 17. Measured input reflection coefficient versus frequency.

Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 129

Fig. 18. Measured on-chip image rejection at first IF.

outputs and filter inputs, and inside the LO circuits. The back side of the chip is
attached with conductive epoxy to a 40-pin surface-mount alumina/glass package.
The measured input return loss is 12 dB in the GSM band (Fig. 17). The front
end comprising the LNA, first mixers, and the polyphase filter is first evaluated sepa-
rately through test points. Front-end insertion gain is 20 dB in the GSM band, and it
rejects the image on-chip by more than 55 dB (Fig. 18).
Next, receiver noise is measured up to the channel-select filter input using the
HP8870B noise-figure meter. This instrument only operates at IF of 10 MHz and
higher, but is the most accurate way to measure noise. It is used to calibrate a spec-
trum analyzer for noise measurement at IF of 140 kHz and below. In the white-noise
region, measured receiver NF is 3.8 dB up to the second mixers. The channel-select
filter degrades cascade NF by less than 0.5 dB. Due to onset of flicker noise, receiver
NF at 240 kHz IF is 4 dB, rising to 5.7 dB at 40 kHz. The extrapolated 3-dB flicker
corner frequency is below 20 kHz, where the spectral density of the wanted channel
is down by more than 10 dB and the higher noise no longer matters (Fig. 19).
To test the immunity of the receiver to blockers, a single tone at each frequency
listed in Table I is applied to the receiver input, and the output at IF2 is measured.
The receiver gain to a -99 dBm tone in the wanted channel is also measured. The dif-
ference between the two is the blocking rejection. All major blockers, including the
image at the first IF, are rejected by more than 110 dB. As explained earlier, the
polyphase filter additionally attenuates a subset of blockers.
The channel-select filter gives the main amplification in the receiver. Its gain
may be swept from about -2 dB to 58 dB, as shown in Fig. 20. The filter maintains its
shape at all gain settings. The passband ripple is within 1 dB, and it rejects the adja-
cent channel 100 kHz away by more than 35 dB. The measured frequency response
of the entire receiver at IF2, shown in Fig. 21, plots gain to the image at the second
130 Part II. Included Papers

Fig. 19. Measured receiver cascode Fig. 20. Measured frequency response and
noise figure. gain range of channel select filter.

IF. At frequencies up to 70 kHz, the image response follows the folded-over filter
transition band. At midchannel, quadrature inaccuracy in the second mixers limits
TABLE I. MEASURED REJECTION OF LIKELY BLOCKING SIGNALS
Physical Effect RF Input Frequency On-chip Rejection
(MHz) Rejection (dB) Incl. Prefilter

1st Image (fLO+fIF1) 1328 56 111

Half IF (2fLO+fIF1)/2 1233 81.5 131

(2fLO-fIF1)/2 1043 72 114

(3fLO+fIF1)/2 1802 >91 141

(3fLO-fIF1)/2 1612 >109 159

Half IF (4fLO+fIF1)/2 2371 >93 148

(4fLO-fIF1)/2 2181 >93 148

HD3 in balanced (2fLO+fIF1)/3 822 97 142

IF1 circuits (2fLO-fIF1)/3 695 71 126

(3fLO+fIF1)/3 1201 76 126

(3fLO-fIF1)/3 1075 56 106

(5fLO+fIF1)/3 1960 >116 171

(5fLO-fIF1)/3 1833 >116 171

(3fLO+fIF1) 3604 106 161

(3fLO-fIF1) 3224 >103 158

Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 131

Fig. 21. Measured cascade frequency response of receiver to desired signal and sec-
ond image.

image rejection; as explained earlier, the image response now resembles a scaled-
down version of the passband. At 40 kHz, the image at IF2 is suppressed by 27 dB,
and at 70 kHz by 37 dB. This is good enough.
The measured VCO phase noise at 1140 MHz is shown in Fig. 22. The VCO
meets the GSM phase-noise requirements at all offset frequencies by some margin.
At 3-MHz offset, the measured phase noise is -142 dBc/Hz and the flicker corner of
the VCO is about 150 kHz. The measured results matches well with Spectre-RF sim-
ulations. The VCO tuning range is about 10%. The phase noise changes by less than
2 dB across the tuning range.

Fig. 22. Measured VCO phase noise.

132 Part II. Included Papers

TABLE II. RECEIVER PERFORMANCE SUMMARY

NF 5 dB
IIP3 - 16 dBm
On Chip Image Rejection >55 dB @ 1st IF
>35 dB @ 2nd IF
Input Return Loss >12 dB (GSM band)
AGC > 80 dB
Current Consumption @ 22mA (RX only)
2.5 V 8 mA (LO Generator
Area 2.2 x 4 mm

6. Conclusion
A fully integrated dual-conversion to low-IF RX is implemented in 0.35-um CMOS
process. Dual conversion to low-IF lowers the impact of baseband noise. The right
choice of IF for first downconversion substantially lowers the impact of the blockers.
This IF also allows use of a single VCO to synthesize both LOs. A multifunction
active polyphase filter selects the desired GSM channel and rejects the image signal
by more than 27 dB across the filter passband. Table II summarizes receiver perfor-
mance. The image signal at first IF is rejected by the LNA and three-stage polyphase
filter by more than 40 dB. The minimum cascade noise figure is 5 dB and the cascade
input IP3 is -16 dBm. The receiver consumes 22 mA from a 2.5-V power supply. The
VCO and buffers drain another 8 mA.
This work illustrates the power of evolving a radio architecture with cognizance
of the strengths and limitations of circuits. This design approach has enabled a
highly integrated all-CMOS solution to the difficult GSM receiver problem with a
power consumption among the lowest to date.

REFERENCES
[1]. T. Stetzler, I. Post, J. Havens, and M. Koyama, "A 2.7-4.5 V single chip GSM
transceiver RF integrated circuit," IEEE J. Solid-State Circuits, vol. 30, pp.
1421-1429, Dec. 1995.
[2]. T. Yamawaki, M. Kokubo, K. Irie, H. Matsui, T. Endou, H. Hagisawa, T. Furuya,
Y. Shimizu, M. Katagishi, and J. Hildersley, "A 2.7-V GSM RF transceiver IC,"
IEEE J. Solid-State Circuits, vol. 32, pp. 2089-2096, Dec. 1997.
[3]. P. Orsatti, F. Piazza, and Q. Huang, "A 20-mA-receive, 55-m A-transmit, single-
Paper II A 900 MHz Dual Conversion, Low-IF GSM Receiver in 0.35 um CMOS 133

chip GSM transceiver in 0.25-um CMOS," IEEE J. Solid-State Circuits, vol. 34,
pp. 232-233, Dec. 1999.
[4]. M. S. J. Steyaert, J. Janssens, B. de Muer, M. Borremans, and N. Itoh, "A 2-V
CMOS cellular transceiver front-end," IEEE J. Solid-State Circuits, vol. 35, pp.
1895-1907, Dec. 2000.
[5]. "Digital cellular telecommunication system: Radio transmission and reception
(GSM 5.05)," European Telecommunication Standards Inst. (ETSI), Sophia
Antipolis, France.
[6]. A. A. Abidi, "Direct conversion radio transceivers for digital communications,"
IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995.
[7]. H. Darabi and A. Abidi, "Noise in CMOS mixers: A simple physical model,"
IEEE J. Solid-State Circuits, vol. 35, pp. 15-25, Jan. 2000.
[8]. J. Rudell, J. Weldon, J. Ou, L. Lin, and P. Gray, "An integrated GSM/DECT
receiver: Design specification," UCB Electronics Laboratory Memo., Berkeley,
CA, 1998.
[9]. S. Fitz, "Receiver architectures for GSM handsets," in IEE Coll. Design of Digi-
tal Cellular Handsets, London, U.K., 1998, pp. 3/1-3/10.
[10].E. Cijvat, "A study of CMOS receiver architectures in mobile commu–nication
handsets for GSM," Ph.D. dissertation, KTH, Kista, Sweden, 2000.
[11].F. Stubbe, S. V. Kishore, C. Hull, and V. Della Torre, "A CMOS RF-receiver
front-end for 1 GHz applications," in Proc. Symp. VLSI Circuits, Honolulu, HI,
1998, pp. 80-83.
[12].W. H. Sansen and R. G. Meyer, "Distortion in bipolar transistor variable gain
amplifiers," IEEE J. Solid-State Circuits, vol. 8, pp. 275-282, Aug. 1973.
[13].F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, "CMOS 10 MHz-IF
downconverter with on-chip broadband circuit for large image-suppression," in
Proc. Symp. VLSI Circuits, Kyoto, Japan, 1999, pp. 83-86.
[14].J. Crols and M. Steyaert, CMOS Wireless Transceiver Design. Boston, MA:
Kluwer, 1997.
[15].J. Lee, A. A. Abidi, and N. G. Alexopoulos, "Design ofspiral inductors on sili-
con substrates with a fast simulator," in Proc. Eur. Solid-State Circuits Conf.,
The Hague, The Netherlands, 1998, pp. 328-331.
[16].J. J. Rael and A. A. Abidi, "Physical processes of phase noise in differential LC
oscillators," in Proc. IEEE Custom IC Conf., Orlando, FL, 2000, pp. 569-572.
[17].M. J. Gingell, "Single sideband modulation using sequence asymmetric
polyphase networks," Electric. Commun., vol. 48, no. 1-2, pp. 21-25, 1973.
[18].A. A. Abidi, C. R. Viswanathan, J. J.-M. Wu, and J. A. Wikstrom, "Flicker noise
in CMOS: A unified model," in Proc. Symp. VLSI Technology, Karuizawa,
Japan, 1987, pp. 85-86.
[19].A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J.
Chang, M. Djafari, M. K. Ku, E. Roth, A. A. Abidi, and H. Samueli, "A single-
chip 900-MHz spread-spectrum wireless transceiver in 1-um CMOS-Part I:
134 Part II. Included Papers

Architecture and transmitter design," IEEE J. Solid-State Circuits, vol. 33, pp.
515-534, Apr. 1998.
PAPER III
PAPER III

Spurious Mixing of Off-Channel Signals in a Wireless

Receiver and the Choice of IF

Abstract
Circuit nonlinearity and LO harmonics can cause large interferers to translate on to
the same intermediate frequency as the desired channel. The mechanisms responsi-
ble for spurious mixing, which are distinct from intermodulation distortion, are an–
alyzed and catalogued. The analysis leads to an optimal choice of IF for a fully inte-
grated 900 MHz GSM receiver that resists all blockers.

Based on: E. Cijvat, S. Tadjpour and A.A. Abidi, “Spurious mixing of off-channel
signals in a wireless receiver and the choice of IF”. © 2004 IEEE. Reprinted, with
permission, from IEEE Trans. on Circuits and Systems II: Analog and Digital Sig-
nal Processing, Vol. 49, No. 8, pp. 539 - 544, August 2002.

137
138 Part II. Included Papers
Paper III Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the Choice of IF 139

1. Introduction
It is clear that today’s wireless transceivers for mobile communication, especially
those operating in the range of 1 to 5 GHz, increasingly must be more integrated.
A higher level of integration requires the circuit designer to eliminate off-chip
filters: for instance, the passive image-reject filter after the low-noise amplifier
(LNA), and the intermediate frequency (IF) filter used to suppress adjacent and out-
of-band signals [1]-[3]. Now much stronger adjacent channels, variously called
interferers or blockers, will traverse the receiver after only mild attenuation in the
antenna preselect filter, eventually to be suppressed at IF or baseband. The blockers
disturb the receiver in a number of well-known ways, through reciprocal mixing,
gain desensitization and intermodulation distortion. These problems are lessened
with low phase noise oscillators and more linear amplifiers, and are roughly indepen-
dent of the numerical choice of IF. Unfortunately this is not all. Due to circuit nonlin-
earity and harmonic mixing, blockers may translate to exactly the same IF as the
desired channel. This problem of spurious mixing is known only qualitatively to
receiver experts [4]-[6]. The object of this paper is to clearly delineate all the impor-
tant mechanisms of spurious mixing, and to relate them to circuit design and receiver
architecture.
Investigating these mechanisms, we find that for a given profile of allowable
blockers the problems of spurious mixing go away at certain intermediate frequen-
cies. At these IFs it becomes possible to remove the customary off-chip filterbetween

0
-10
-20
-30
-40
dBm

-50
-60
-70
-80 Wanted Channel
(minimum level)
-90
-100

900 910 920 930 940 950 960 970 980 990 1000
Frequency, MHz

Fig. 1. GSM blocking signal template.

140 Part II. Included Papers

the LNA and mixer. This enables the complete integration of receivers for cellular
systems such as GSM that allow very strong blockers. Fig. 1 shows the blocker tem-
plate [7] for the 900-MHz GSM receive band. In a certified GSM receiver, the ratio
of signal-to-noise and interference with the wanted channel 3 dB above the sensitiv-
ity level accompanied by a blocker up to 100 dB larger should be the same as with
the wanted channel alone at the sensitivity level.
In Section II, we model the front-end and how it generates harmonics. Then in
Section III different mechanisms of spurious mixing are described, and the results
are applied to the GSM standard to find a good range for IF. Finally, Section IV pre-
sents the measured blocking tolerance of a fully integrated GSM receiver whose
architecture evolved out of this analysis.

2. Modeling Receiver Front-End

Fig. 2 shows a generic front-end for a superheterodyne receiver. The RF preselect fil-
ter connected to the antenna passes the band of interest, but suppresses out-of-band
blocking signals. Together with the LNAs tuned input matching network, it sup-
presses blocking signals by some amount AttBPF(∆f), where ∆f is the frequency off-
set from the desired channel. Signals in the preselect filter’s passband inevitably
suffer a small insertion loss LBPF. The term AttLNA(∆f) refers to how much the tuned
load of the LNA and any image reject filter that follows attenuate blocking signals.
Ln signifies how much lower the nth LO harmonic is when compared to the funda-
mental.
There are three important nonidealities in a receiver front–end.
1. LNA nonlinearity: This creates harmonics of an incoming RF signal and blockers,
as well as intermodulation products.
2. Mixing with LO harmonics: For highest conversion gain, the mixer must com-
pletely commutate the RF signal with a square wave at the LO frequency. There-
fore, the strong odd harmonics of a 50% duty cycle square-wave LO, given by

LO (Ln)
LNA IFblock
BPF IRF

Mixer
GLNA Gmixer IIPm,IF
LBPF IIPk,LNA

Fig. 2. Generic superheterodyne receiver front end.

Paper III Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the Choice of IF 141

sq ( ω LO t ) = ---  sin ω LO t + --- sin 3ω LO t + …

4 1
(1)
π 3 

mix with the full span of the RF input spectrum, which in–cludes in addition to the
channel of interest, various strong blocking signals.
3. Nonlinearity in IF circuits: This shifts interferers lying at subharmonics of IF onto
the wanted channel.
Therefore, an input interferer at this frequency
f interf = ( nf LO ± f IF ⁄ m ) ⁄ k (2)

where k, m, n are integers, after being subject to these three possible imperfections in
the receiver, will coincide in frequency at IF with the desired signal. Here k refers to
the kth-order nonlinearity of the LNA, n is the nth LO harmonic, and m represents
the mth-order nonlinearity of the IF circuits after the mixer.
In any circuit with kth-order nonlinearity, the difference ∆P between the funda-
mental output signal and the kth-order intermodulated signal in decibels is [5]
∆P = ( k – 1 ) ( II P k – P in ) = P fund, out – P k, out (3)

where IIPk is the kth-order input intercept point and Pin is the input power. For a
wide-band receiver, the kth-order harmonic generated by a single-tone can be
deduced using a similar definition
∆P h = ( k – 1 ) ( P k, oi – P in ) = P fund, out – P k, out (4)

where the fundamental is located at f1 and the kth-order harmonic at kf1. The rela-
tionship between IIPk and Pk,oi is
P k, oi = II P k + 10 log k (5)

Since it is customary to characterize nonlinearity in RF circuits in terms of inter-

cept point IIPk, from here on we use this to also represent distortion in single-tone
blocking signals.

3. Mechanisms of Disturbance by Spurious Signals

Different mechanisms are distinguished by combinations of n, k and m. Three sepa-
rate mechanisms may be identified as follows.
Mechanism 1: Harmonic Mixing, m = 1, n & k >1: An interferer lying at subject
to kth-order nonlinearity in the RF frontend, mixes with the nth LO harmonic and
downconverts to IF (Fig. 3). It overlays the desired signal, which has appeared at IF
through the intended undistorted am–plification in the LNA, followed by downcon-
version by the fundamental frequency of the LO. For the receiver to function prop–
142 Part II. Included Papers

P
fLO 3fLO 5fLO

fIF
fIF

finterf kfinterf f

Fig. 3. Harmonic mixing with mechanism 1.

erly, an unintentionally downconverted interferer must lie below the desired signal
by some specified carrier-to-interference ratio C/I
C
P inter f , IF < P des, IF – ---- (6)
I
The wanted channel is amplified in the LNA and mixer by power gains of GLNA and
Gmxr, respectively. At IF, the desired signal’s power is then
P des, IF = P des – L bpf + G LNA + G mxr (7)

On the other hand, the interferer is subject to a different set of gains and losses. An
interfering signal ∆f away from the RF band is first suppressed in the RF preselect
filter. Then its kth harmonic at kfinterf, calculated using (4), is additionally sup–
pressed in the tuned load of the LNA. The interferer downconverts to IF by mixing
with the nth LO harmonic. Finally at the mixer output, its strength in dB is
P inter f , IF = k ( P int erf – L BPF – Att BPF ( ∆f ) ) + G LNA – ( k – 1 ) ( II P k + 10 log k )
(8)
– Att LNA ( ∆f k ) – L n + G mxr

where
Pdes Minimum power of desired signal
Pinterf power of interfering signal (from the antenna) according to the block-
ing profile
LBPF insertion loss of the band pass filter in the RF band
AttBPF(∆f) attenuation of the antenna pre-select filter and the LNA input match-
ing network at an offset frequency ∆f
∆f distance of interferer to the RF receive band
AttLNA(∆f) attenuation by the tuned load of the LNA and/or the image reject fil-
ter at an offset frequency ∆f
∆fk distance of kth order harmonic of blocker at LNA output to the RF
receive band
Paper III Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the Choice of IF 143

Ln loss of nth LO harmonic relative to the LO fundamental.

By inserting (7) and (8) into (6), we arrive at the minimum of the LNA that leads
to the required carrier-to-interfer–ence ratio for a certain BER [7]
k k 1
II P k, LNA > -----------P interf – L BPF – ----------- Att BPF ( ∆f ) – ----------- ⋅ ( Att LNA ( ∆ f k ) + L n )
k–1 k–1 k–1
(9)
1  C
– 10 log ( k ) – ----------- P des – ----
k – 1 I
If the circuit properties are known but unalterable, the equation may be rearranged to
determine the required selectivity of the RF preselect filter

k–1 1
Att BPF ( ∆f ) > P interf – -----------L – --- ( Att LNA ( ∆ f k ) + L n ) (10)
k BPF k
– ----------- ( II P k + 10 log k ) – ---  P des – ----
k–1 1 C
k k I
Next, let us find the values of IF which satisfy this inequality for a GSM
receiver. To start with, we must know the characteristics of the prefilter. Fig. 4 shows
the frequency response of a typical commercially available 947-MHz SAW filter
intended for the GSM receive band. Then, based on previous experience with RF
CMOS circuits, we assume that in a well-designed LNA the IIP3 is 0 dBm, and IIP2
is +12 dBm. As defined by the relationship kf interf = n f LO ± f IF , the most trouble-
some interferers susceptible to third-order nonlinearity (k = 3, n = 3) lie in the fre-
quency range 890 MHz < finterf < 1025 MHz, and due to second-order nonlinearity (k
= 2, n = 2) lie in the range 890 MHz < finterf < 1020 MHz. After downconversion by
the mechanisms described above, if the interferer is to not coincide at IF with the

Fig. 4. Typical RF prefilter.

144 Part II. Included Papers

desired signal, the following must hold, respectively, for low-side LO injection
where fLO = fRF - fIF, and for high-side LO injection where fLO = fRF + fIF:
n f RF – k f interf k f interf – n f RF
f IF ≠ ------------------------------------- or f IF ≠ ------------------------------------
−1 - (11)
n ±1 n+
By stepping through all GSM channels in the range 935 MHz MHz, this leads to
undesired ranges of fIF shown in Table I for various n and k.
TABLE I. UNDESIRED FIF REGIONS (MEGAHERTZ) DUE TO MECHANISM 1

Low-Side Injection High-Side Injection

k=2 k=3 k=2 k=3

n=2 13 - 47 - 13 - 57 265 - 292

40 - 140 40 - 170 340 - 377
n=3 171 - 285 15 - 53 - 15 - 68
30 - 105 30 - 135
n=4 340 - 376 148 - 180 - -
382 - 412 199 - 225
247 - 300
332 - 375
n=5 - 269 - 310 - -
322 - 355

The undesired responses invoked by the special case of n – k = 1 have been

called "Able-Baker spurs" [6].
Mechanism 2: Mixing of Interferer With LO Harmonic, m = k = 1, n > 1: Even
if the RF front-end is perfectly linear, LO harmonics in the mixer will downconvert
interferers lying at f interf = n f LO + f IF to IF (Fig. 5). For the receiver to function
normally in the presence of these interferers, the following inequality must hold:
C
P interf – Att BPF ( ∆f ) – Att LNA ( ∆f ) – L n < P des – ---- (12)
I
interferer

nfLO
P

fIF fIF

f
fLO fRF

Fig. 5. Harmonic Mixing m=k=1, n>1 (mechanism 2).

Paper III Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the Choice of IF 145

In this case, since the interferers of concern lie far away from the frequency
band to which the receiver is tuned, they are subject to the full stopband loss of the
RF prefilter and then further attenuation in the LNAs tuned load. GSM allows out-of
band interferers to be as large as 0 dBm at the antenna; that is, 102 dB larger than the
minimum detectable desired signal. Assuming that a practical preselect filter (Fig. 4)
offers a stopband loss of 55 dB at best, the interferers must be suppressed roughly by
another 55 dB on chip. The tuned input matching network and LNA load will each
be partly responsible for this attenuation. For example, for n = 3 and an LO of 1 GHz
with a reasonable IF of, say, 100 MHz, an LNA tuned by an on-chip inductor of
moderate Q and impedance-matched at its input suppresses the interferer in question
by more than 20 dB relative to the wanted signal. Then the interferer mixes with the
third LO harmonic, which is one third the amplitude of the LO fundamental, and this
translates the interferer to IF with one third (-10 dB) the conversion gain seen by the
desired signal. Another 25 dB of attenuation is still needed. If this is not forthcom-
ing, the interferer will jam the desired signal, and then can only be tolerated as one of
the exceptions granted by GSM [7]. However, more than a few such interferers will
soon exhaust the quota of exceptions.
With high-side LO injection, the interferers in question will lie yet further out in
frequency. However, the filters described above will attenuate them by almost the
same amount because, in practice, far away stopband loss tends to flattens out at
some maximum value. In a superheterodyne receiver which uses off-chip filters, this
problem is solved by placing an image reject filter, which is identical to the preselect
filter, after the LNA. Now the cascaded stopband loss of the two filters pushes down
all out-of-band interferers by more than 100 dB relative to pass-band signals.
It is clear that unless the IF is exceptionally high, mechanism 2 is largely inde-
pendent of IF. Also that the classic image in wireless reception is a special case of
this mechanism, when n = m = k = 1.
Mechanism 3: Subharmonics of IF, k = n = 1, m > 1: Interferers may be shifted
onto the desired signal because of nonlinearity in the IF circuits. An interferer at
f LO + f IF ⁄ m mixes with the LO and downconverts to fIF/m. Then, subject to IF cir-
cuit nonlinearity, its mth harmonic appears at fIF (Fig. 6).
Depending on m, if the interferers in question initially lie in the RF filter’s tran-
sition band they are only slightly attenuated before entering the receiver. For normal
operation, the minimum linearity in the receiver’s IF section, as characterized by
intercept point, is
146 Part II. Included Papers

interferer
P

2nd 3rd fIF

fLO f
fIF fRF

Fig. 6. Downconverted interferer appears at a subharmonic of IF (mechanism 3).

m m m
II P m, IF > ------------- P interf – L BPF – ------------- Att BPF ( ∆f ) – ------------- ⋅ Att LNA ( ∆f )
m–1 m–1 m–1
(13)
1  C
– 10 log ( m ) – ------------- P des – ---- + G mxr + G LNA
m – 1 I
This expression imposes lower bounds on the IF. Once again, let us see how this
mechanism works with GSM blocking signals. The IF circuits are usually fully dif-
ferential; as a result they will largely suppress even-order harmonics. Based on cir-
cuit simulations, we assume an IIP3 of +10 dBm at the IF input to the receiver, and
supposing a 3% FET mismatch an IIP2 of +40 dBm in the IF differential circuits.
Then with 935 MHz < fRF < 960 MHz, Table II presents the lower bounds on where
the receiver is immune to this mechanism.
TABLE II. UNDESIRED FIF REGIONS (MEGAHERTZ) DUE TO MECHANISM 3

Low-Side Injection High-Side Injection

m=2 0 - 150 0 - 160

m=3 0 - 113 0 - 105

Note that a blocker at f LO ± f IF ⁄ m can be subject to spurious mixing by the first

mechanism with n = k, that is when m (mechanism 3) replaces k (mechanism 1).
However, in the two cases the blocker appears at IF by entirely different processes.
In the first mechanism, RF circuit nonlinearity shifts the interferer to a higher fre-
quency, where it is attenuated by the tuned LNA load. In mechanism 3, however, the
interferer is close to the RF band, and downconverts to a subharmonic of the IF.
The well-known half-IF interferer [3], f LO ± f IF ⁄ 2 , is a special case of mecha-
nisms 1 and 3.
With this background, let us study some previously published GSM receivers to
understand their vulnerability to the spurious mixing of large interferers. It should be
noted that the authors of these works make no mention of what steps they took, if
any, to lessen their receivers’ exposure to these vulnerabilities.
Paper III Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the Choice of IF 147

A. Example: GSM Receiver With IF of 71 MHz

This receiver [1] uses a passive RF filter before and after the LNA to cascade the
stopband losses, and therefore strongly suppress out-of-band blockers from entering
the mixer. Suppose that in the interest of higher integration, we remove the filter after
the LNA. First consider mechanism 1. Assume the desired signal lies at 935 MHz,
and that the LO is high-side injected at 1006 MHz. With n = 3, k = 3, IIP3,LNA = -7.5
dBm, L3 = 10 dB, Pdes = -99 dBm, Pinterf = 0 dBm, LBPF = 3 dB, C/I = 12 dB, and
an approximate attenuation of 15 dB at 3finterf due to the LNA load, it follows from
(10) that the RF prefilter must attenuate an interferer at 983 MHz ( f LO + f IF ⁄ ( 3 ) ) by
at least 28 dB. This is not possible with today’s prefilters (Fig. 4).
Next consider mechanism 3 with m = 3. An interferer at 997 MHz suffers almost
no attenuation through the LNA. Using (13) with AttBPF = 26 dB, AttLNA = 0 dB,
GLNA = 15.3 dB and Gmxr = 10 dB, the required IIP3,IF > +34 dBm. This is too high
for a practical on-chip IF circuit, which means that the receiver is also vulnerable to
blocking by this interferer.
These calculations show that with a 71 MHz IF a post-LNA filter is mandatory,
and a GSM receiver using this IF cannot be fully integrated.

B. Example: GSM Receiver With Low IF of 100 kHz

Suppose the low-IF receiver for DCS-1800 [9] is re-tuned to 900 MHz GSM. The
blocking templates for both standards are very similar. With the desired signal at 950
MHz, and assuming high-side injection fLO = 950.100 MHz, mechanism 3 exposes
the receiver to an interferer at f LO + f IF ⁄ m , for example, with m = 2, at 950.150
MHz or 950.050 MHz. However GSM limits the strength of interferers within 600
kHz of the desired signal to less than -43 dBm. The resulting downconverted blocker
on to the desired channel is inconsequential.
If mechanism 1 is at work, and assuming n = k, the candidate interferer lies at
f LO ± f IF ⁄ k . This amounts to merely replacing m above by k, and again the perti-
nent interferers pose no threat. For example, assuming comparable IIPk of the LNA
as the one used in the receiver described in [8], the ranges of undesired IF are similar
to the ones in Table I, and therefore the low IF is safe.
However, for mechanism 2 and with n = 3, an interferer 0 dBm strong at roughly
2850 MHz + 100 kHz ( f interf = n f LO + f IF ) might overwhelm the desired signal.
As it propagates through the receiver, this interferer is attenuated in the preselect fil-
ter by, say, AttBPF = 60 dB. It is further attenuated in the tuned load of the LNA. If
this load is a parallel LCR circuit with quality factor Q and assuming that fIF << fLO,
148 Part II. Included Papers

it follows that its gain to an interferer close to nfLO compared to its gain to the
wanted signal close to fLO is in the ratio 1 : nQ. With a Q of, say, five this amounts to
AttLNA = 23 dB. In mixing with the third LO harmonic whose L3 = 10 dB, the left-
hand side of (12) amounts to -93 dBm while the right-hand side may add up to -111
dBm. This violates the inequality in (12), exposing a vulnerability.

4. Experimental Validation on a Receiver with Optimal IF

The results of the analysis above were used to develop the frequency plan of a fully
integrated 900-MHz CMOS GSM receiver [8]. The prototype receiver was fabri-
cated in 0.35-um CMOS. Considerations of flicker noise at the output of the first
mixer lead to the choice of dual conversion to low-IF. Given the GSM template of
allowed channel strengths, it is relatively easy to choose the second IF close to 100
kHz because now the image need only be rejected by about 20 dB. However, what of
the first IF? This is where the analysis above gives guidance.
According to the analysis, with high-side LO injection a first IF in the range of
170-265 MHz is immune to interference caused by mechanisms 1 and 3 (Tables I
and II). It turns out that for lowside LO injection there is no "good" IF. Interest–
ingly, Rohde and Bucher in their textbook [4] have come to the same conclusion. On
page 112, they note that generally "the difference mixer with high-side oscillator
provides fewer spurious responses."
Mechanism 2 remains a problem. The responsible interferers cannot be ade-
quately rejected by the prefilter alone, and must be additionally suppressed by the
frequency-dependent gain in the LNA. As was explained earlier in the example of
the low IF receiver, the antenna prefilter and the LCR tuned load of the LNA do not
adequately suppress the interferers that GSM allows at 3 x the frequency of the
receive band (3420 x 190 MHz in this case). Therefore, a notch in the LNA fre-
quency response must be realized at these frequencies. The most convenient way to
do so is by resonating a capacitor in parallel with the LNA FETs source degeneration
inductor at the desired notch frequency (Fig. 7). This inductor is realized with a
bondwire [8], which resonates at around 3 GHz with the capacitance of the bondpad
and PN junction present at the source terminal. Simulations suggest that with the
high Q of the bondwire inductance, the notch may be as much as 100 dB below the
gain peak.
The receiver uses a high-side LO and a first IF of about 190 MHz [8]. The sec-
ond IF is selected to be 120 kHz. This choice of IFs gives a simple integer ratio of 6
x between the required LO frequencies at the two stages of downconversion, and
allows both to be synthesized with a single VCO and a simple divider.
Paper III Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the Choice of IF 149

Fig. 7. LNA circuit with notch filter to suppress third harmonic, and associated
frequency response.

The prototype receiver circuit was subjected to a comprehensive range of GSM

blockers. The test consists of applying a tone at each of the frequencies listed in
Table III, accompanied by a reference signal 3 dB above the sensitivity level in the
middle of the GSM receive band. The amplitude of the interferer tone is raised until
TABLE III. MEASURED BLOCKING SIGNAL REJECTION FOR A GSM RECEIVER [8]
Physical Effect RF Input Frequency On-chip Rejection
(MHz) Rejection (dB) Incl. Prefilter

1st Image (fLO+fIF1) 1328 56 111

Half IF (2fLO+fIF1)/2 1233 81.5 131

(2fLO-fIF1)/2 1043 72 114

(3fLO+fIF1)/2 1802 >91 141

(3fLO-fIF1)/2 1612 >109 159

Half IF (4fLO+fIF1)/2 2371 >93 148

(4fLO-fIF1)/2 2181 >93 148

HD3 in balanced (2fLO+fIF1)/3 822 97 142

IF1 circuits (2fLO-fIF1)/3 695 71 126

(3fLO+fIF1)/3 1201 76 126

(3fLO-fIF1)/3 1075 56 106

(5fLO+fIF1)/3 1960 >116 171

(5fLO-fIF1)/3 1833 >116 171

(3fLO+fIF1) 3604 106 161

(3fLO-fIF1) 3224 >103 158

150 Part II. Included Papers

its in-band spurious response overtakes the reference signal. Measurements show
that the receiver rejects all potential interferers, including the image signal, by more
than 105 dB. An on-chip circuit in this receiver attenuates the image channel,
f LO + f IF , at the first IF. It also suppresses image channels downconverted by the
LO harmonics, of which the principal one is 3 f LO – f IF - the sign reversal is due to
the fact that the quadrature sequence is reversed for the third harmonic of the LO.
These results show the practical outcome of the analysis in the design of an inte-
grated receiver robust to interferers.

5. Conclusion
This paper presents a systematic and comprehensive analysis of how circuit imper-
fections cause adjacent and out-of-band signals incident on a wireless receiver to
translate to the same frequency as the desired signal. The comprehensive analysis
reveals mechanisms in wireless receivers other than the well–understood intermodu-
lation distortion, whereby adjacent and out-of-band signals become "interferers."
Some of these signals, although initially distant from the wanted channel but nu–
merically related in frequency, mix via spurious mechanisms on to it at IF and inter-
fere with its detection.
Knowing the profile of adjacent channel strengths, characteristics of the antenna
filter, and the typical nonlinearity in the RF circuits, we can predict the strength of
spurious mixing products. In some cases, such as mechanism 1 and 3, the only way
to counter the resulting problems is by proper choice of intermediate frequency, IF.
Mechanism 2 is often most important, since here, blocker suppression depends
exclusively on filter attenuation and LO harmonics.
In a fully integrated receiver which dispenses with fixed external filters to save
power and physical volume, the problems of spurious mixing are particularly press-
ing. Based on this analysis, a fully integrated GSM receiver with a unique frequency
plan was developed. Measurements on the prototype, which uses only one off-chip
filter for RF preselection, verify that it suppresses all blockers by more than 105 dB.
We expect that an awareness of spurious mixing will add yet another criterion
that guides the choice of receiver architectures in the future.

REFERENCES
[1]. P. Orsatti, F. Piazza, and Q. Huang, "A 20-mA-receive, 55-mA-transmit, single-
chip GSM transceiver in 0.25-um CMOS," IEEE J. Solid State Circuits, vol. 34,
pp. 1869-1880, Dec. 1999.
[2]. T. Yamawaki, M. Kokubo, K. Irie, H. Matsui, K. Hori, T. Furuya, H. Shimizu,
M. Katagishi, T. Endou, B. Henshaw, and J. R. Hildersley, "A dual-band trans-
Paper III Spurious Mixing of Off-Channel Signals in a Wireless Receiver and the Choice of IF 151

ceiver for GSM and DCS1800 applications," Proc. Eur. Solid-State Circuits
Conf. (ESSCIRC), pp. 84-87, 1998.
[3]. T. D. Stetzler, I. G. Post, J. H. Havens, and M. Koyama, "A 2.7-4.5 V single chip
GSM transceiver RF integrated circuit," IEEE J. Solid State Circuits, vol. 30, pp.
1421-1429, Dec. 1995.
[4]. U. Rohde and T. Bucher, Communications Receivers: Principles and Design.
New York: McGraw-Hill, 1988.
[5]. R. C. Sagers, "Intercept Point and Undesired Responses," IEEE Trans. Veh.
Technol., vol. VT-32, pp. 121-133, Feb. 1983.
[6]. K. Hansen and A. Nougeras, "Receiver RF design considerations for wireless
communications systems," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS),
pp. 93-96, 1996.
[7]. GSM Technical Specification 05.05, European Telecommunications Standards
Institute, 1992.
[8]. S. Tadjpour, E. Cijvat, E. Hegazi, and A. Abidi, "A 900 MHz dual con–version,
low-IF GSM receiver in 0.35-um CMOS," IEEE J. Solid State Circuits, vol. 36,
pp. 1992-2002, Dec. 2001.
[9]. M. S. J. Steyaert, J. Janssens, B. de Muer, M. Borremans, and N. Itoh, "A 2-V
CMOS cellular transceiver front-end," IEEE J. Solid State Circuits, vol. 35, pp.
1895-1907, Dec. 2000.
152 Part II. Included Papers
PAPER IV
PAPER IV

A Fully Integrated 2.45 GHz 0.25 um CMOS Power

Amplifier

Abstract
A fully integrated differential class-AB power amplifier has been designed in a
0.25um CMOS technology. It is intended for medium output power ranges such as
Bluetooth class I, and has an operating frequency of 2.45GHz. By using two parallel
output stages that can be switched on or off, a high efficiency can be achieved for
both high and low output power levels. The simulated maximum output power is
22.7 dBm, while the maximum power-added efficiency is 22%.

Based on: E. Cijvat and H. Sjöland, “A Fully Integrated 2.45 GHz 0.25 µm CMOS
Power Amplifier”. © 2004 IEEE. Reprinted, with permission, from Proceedings
of the 10th IEEE International Conference on Electronics, Circuits and Systems
(ICECS) 2003, pp. 1094-1097. Sharjah, United Arab Emirates, December 2003.

155
156 Part II. Included Papers
Paper IV A Fully Integrated 2.45 GHz 0.25 um CMOS Power Amplifier 157

1. Introduction
With the recent emergence of short-range communication standards such as Blue-
tooth, the research interest for highly integrated power amplifiers (PAs) has
increased [1-13]. For frequencies up to several GHz and low to medium output
power, CMOS may be an alternative to stand-alone power amplifiers, offering a
higher level of integration in a relatively cheap technology, in exchange for less effi-
ciency and a lower maximum output power.
In most communication systems transmitter output power control is required. In
order to increase the battery lifetime, it is important to have a relatively high effi-
ciency over the whole PA output power range, i.e. for both lower and higher output
power, since the PA is more likely to operate at lower than higher output power.
For the Bluetooth standard the highest output power is 20 dBm (class I, [14])
which is feasible for CMOS implementation (see [1-13]). Moreover, a constant enve-
lope modulation scheme is used, implying that linearity of the PA is not a critical
issue for this standard.
In this work a class-AB power amplifier is described that consists of two stages,
with the output stage comprising two parallel blocks that may be switched on or off
(see fig. 2). In this way the efficiency may be optimized for different output power
settings. The output impedance transformation network is fully integrated.
The paper is structured as follows: First some PA theory is described, then the
design itself is presented. Simulation results are shown in Section 4, and finally con-
clusions are presented.

2. Analysis
In fig. 1 a current source with impedance transformation network T is shown. This
serves as a model for an ideal output stage, where the transistor operates as a con-
trolled current source driving Ropt, the transformed load impedance RL. The maxi-
mum signal amplitude is VDD, and the ideal maximum output power is given by
2
V DD
P out, max, ideal = ------------
- (1)
2R opt

VDD out

T
RL
Ropt

Figure 1. Principle of impedance transformation.

158 Part II. Included Papers

Thus, for a given VDD, Ropt determines Pout,max assuming a maximum voltage swing.
For Pout,max = 22 dBm and VDD = 3.3 V, the optimum load resistance Ropt is equal to
34 Ω.
The power added efficiency (PAE) is defined as

P out – P in
PAE = ----------------------- (2)
P DC

where PDC is the power supplied by the battery, which is signal-dependent for most
types of PAs. The PAE typically is maximum for an output power close to Pout,max
and decreasing fast for lower output powers [5]. Therefore, for a high average effi-
ciency, the PA may be designed to have different Pout,max by changing Ropt or VDD.
In this work the former strategy is used.

Non-idealities
For high voltage swings the transistor will enter the linear region, and no longer
behave as an ideal current source. This is commonly modeled with the knee voltage
Vknee [15]. The output voltage swing is reduced to VDD - Vknee, and the maximum
output power may be written as
2
( V DD – V knee )
P out, max = ------------------------------------- (3)
2R opt

Assuming an output stage with an integrated current-supplying inductor and a

switch at VDD, allowing the whole stage to be turned on or off, other non-idealities
may be identified such as the series resistance of the inductor and the on-resistance
of the supply switch, both reducing the bias voltage at the drain. Moreover, the finite
output impedance of the transistor and the finite quality factor Q of the passives in
the matching network will cause power loss. To compensate for these losses, a PA is
generally designed for a higher Pout,max by reducing Ropt in Eq. 3.

3. Design
A fully integrated 2.45 GHz PA was implemented in a 0.25um CMOS technology. In
order to implement different output power settings and increase the average effi-
ciency, two parallel output blocks were used (see fig. 2). Due to die size consider-
ations the number of parallel blocks was limited to two.
The matching network was chosen so that a maximum output power of 22 dBm
was achieved with both blocks on. When one stage is off, the matching network pro-
vides a higher Ropt and thus a lower Pout,max. In this way a relatively high average
efficiency over the total PA output power range can be achieved.
Paper IV A Fully Integrated 2.45 GHz 0.25 um CMOS Power Amplifier 159

VDD
LD
C2 L2 C1
Vb M2 out
in Ma Lbw
M1 RL
Rs LG C3
L1
+
Vs
- LS
VDD

Mb

Figure 2. Simplified single-ended schematic of the PA with two parallel output

stages.
For the output stage no cascode transistors are used, since this would increase
the knee voltage and thus decrease Pout,max. A switch in the signal path at the output
would also have a negative impact on the output power and thus on the efficiency,
and was therefore avoided as well.
The input capacitance of the output stage forms a large part of the total capaci-
tance at the drain of M2 which is parallel to LD, see fig. 2. When switching off one
stage (by changing the gate bias to VDD and opening the VDD switch), the input
capacitance will change significantly. In order to decrease the impact on input stage
tuning, a rather small AC coupling capacitance is used between the input- and output
stage.
By connecting the two output nodes as shown in fig. 2, the two parallel stages
share L1, C3 and Lbw. Only C1, L2 and C2 are available to separately design Ropt for
each stage. Moreover, due to numerous parasitic capacitances and size restrictions of
integrated passives, the impedance transformation ratio cannot be varied over a wide
range.
Generally when parallel output stages are used, power combining is imple-
mented either through a transformer [3] or transmission lines [5]. In this design,
however, the two stages are not isolated, meaning that the network of one stage has
an impact on the impedance transformation of the other.
The matching network for one output stage may be drawn as shown in fig. 3.
The two output stages are connected at point P.
When for example the lower stage in fig. 2 is switched off, FET Mb is brought
into the linear region, thus providing a low impedance. Assuming this to be a short,
one can see from fig. 2 that the equivalent capacitance parallel to C3 will be larger.
160 Part II. Included Papers

C2
L2
C1 P out

Lbw
RL
Ropt L1 C3

Figure 3. The matching network for one stage, with the FET represented as an ideal cur-
rent source.

This decreases the transformation ratio for the upper stage, thus increasing Ropt,
which is desirable when only one stage is on.
The two stages are unequal, having different FET widths and different capaci-
tance and inductance values, and thus different transformation ratios and gains.
Comparing fig. 2 with fig. 3 one can see that the matching network includes par-
asitic capacitance at the drain of the FET (incorporated in C2), as well as the on-chip
output node (in C3).
The 5M1P 0.25um CMOS technology offers thick-metal inductors with quality
factors ranging from approximately 5 to 15. For L2 and LS inductors provided by the
manufacturer were used. LD and L1 were designed using Fast Henry [16] and
ASITIC [17]. For the integrated matching network, MOM (metal-oxide-metal)
capacitors with highest quality (Q) factor available in this technology were used. The
FETs Ma and Mb in fig. 2 do not have minimum gate length, but 0.32µm, and have a
higher breakdown voltage.

Figure 4. Plot of the PA layout.

Paper IV A Fully Integrated 2.45 GHz 0.25 um CMOS Power Amplifier 161

stage 1+2
stage 1+2

stage 1

stage 1

a. b.

Figure 5. Simulation results, a). Frequency response, b). Pout as a function of Pin.

4. Simulation Results
The above described design was simulated using SpectreRF, with BSIM3v3 models.
Post-layout parasitics were taken into account. The layout is shown in fig. 4. A large
area is occupied by the integrated passives, and a substantial area saving may be
achieved by using differential inductors [18].
In fig. 5 some simulation results are shown. The maximum PAE (22 %) is
achieved for Pout slightly below Pout,max (which is about 23 dBm, see fig. 5.b). The
center frequency for both cases (stage 1+2 and stage 1 only) is approximately
2.45GHz. The simulation results are summarized in table 1.
TABLE I. SIMULATION RESULTS, SUMMARY
PAEmax 22%

Pout (differential) 22.7 dBm @2.45GHz

@PAEmax

power gain 28 dB @PAEmax

total die area 6.25 mm2 including pads

Pout (stage1 only) 17.2 dBm PAE=15.8%

Pout (stage 2 only) 12.4 dBm PAE=6.1%

From table 2 a comparison can be made between this PA and previously pub-
lished work. It can be seen that the PA presented in this work performs quite well,
given the limitations of an on-chip matching network and class-AB. Moreover, the
PA includes measures to improve the average efficiency.
 162
TABLE II. COMPARISON OF MEDIUM POWER PAS

frequency output power

Pout (dBm) efficiency (max) technology class
(GHz) matching control

[1] 15 (@P-1dB) 0.9 <30% (η) 1um CMOS off-chip steps, 5dB C

[2] 23.5 (max) 1.9 35% (PAE) 0.35 um (Bi)CMOS off-chip - AB

[3] 33.4 (@max PAE) 2.4 31% (PAE) 0.35um (Bi)CMOS on-chip - E/F3

[4] 28.2 1.9 30% (PAE) 30GHz BiCMOS off-chip - AB

[5] 24.8 (max) 1.4 49% (PAE) 0.25um CMOS off-chip 3 parallel F
(transm. lines) stages

[6] 31.8 (max) 0.9 43% (PAE) 0.2um CMOS off-chip - F

[7] 30 (@max. PAE) 1.8 45% (PAE) 0.35um CMOS off-chip - AB

[8] 20 (max) 1.9 16% (η) 0.8um CMOS on-chip - F?

[8] 22 (max) 2.4 44% (η) 0.25um CMOS off-chip - F?

[9] 17.5 (max) 2.4 16.4% (PAE) 0.35um CMOS partly on-chip - A

[10] 23 (max) 2.4 42% (PAE) 0.18um CMOS off-chip - AB

[11] 30 (max) 0.7 62% (PAE max) 0.35um CMOS partly on-chip - E

[12] 9 (@P-5dB) 2.4 16% (P-5dB) 0.18um CMOS partly on-chip - AB?

Part II. Included Papers

[13] 18.6 (@max PAE) 0.9 30% (PAE max) 0.6um CMOS on-chip - C

this 22.7 (@max PAE) 2.45 22% (PAE max) 0.25um CMOS on-chip 2 settings AB
work
Paper IV A Fully Integrated 2.45 GHz 0.25 um CMOS Power Amplifier 163

5. Conclusions
A 2.45 GHz power amplifier has been designed in a 0.25um CMOS technology. The
PA is fully integrated, including output matching network. Simulations show that an
output power of 22.7 dBm may be achieved with a maximum PAE of 22%. The aver-
age efficiency has been improved by using two parallel output stages.

ACKNOWLEDGEMENTS
The authors are grateful to Niklas Troedsson, MSc (Dept. of Electroscience,
Lund University) for help with integrated inductor design and modeling.

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1800with 45% PAE”, 2001 International Solid-State Circuits Conference
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IEEE Radio and Wireless Conference (RAWCON), pp. 29-32, August 2001.
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164 Part II. Included Papers

11. K. Mertens and M.S.J. Steyaert, “A 700MHz 1-W Fully Differential CMOS
Class-E Power Amplifier”, IEEE Journal of Solid-State Circuits, Vol. 37, no. 2,
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Vol. 1, version 1.1. www.bluetooth.com, 2001.
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16. M. Kamon, M.J. Tsuk, and J. White, “FastHenry: A Multipole-Accelerated 3-D
Inductance Extraction Program”, Proc. of the 30th ASM/IEEE Design Automa-
tion Conference (DAC), pp. 678-683, 1993.
17. A.M. Niknejad, “Modeling of Passive Elements with ASITIC”, Proc. of the 2002
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 303-306,
May 2002.
18. M. Danesh and J.R. Long, “Differentially Driven Symmetric Microstrip Induc-
tors”, IEEE Trans. on Microwave Theory and Techniques, Vol. 50, no. 1, January
2002.
PAPER V
PAPER V

A Fully Integrated CMOS RF Power Amplifier with

Internal Frequency Doubling

Abstract
The design and measurement results of a fully integrated 0.18µm 1P6M CMOS
power amplifier with internal frequency doubling are presented. Two designs were
measured, one stand-alone PA and one PA with a VCO on the same chip. Since the
PA and VCO operate at different frequencies, this configuration is suitable for direct-
conversion transmitters or low-IF upconversion as oscillator pulling will be reduced.
The maximum output power is 15 dBm, and the maximum drain efficiency is 10.7%
at an output operating frequency of 2.4 GHz. An analysis of the efficiency is given.

Based on: E. Cijvat, N. Troedsson and H. Sjöland, "A Fully Integrated CMOS RF
Power Amplifier with Internal Frequency Doubling". Submitted to Analog Inte-
grated Circuits and Signal Processing.

167
168 Part II. Included Papers
Paper V A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling 169

1. Introduction
In recent years, the wireless communications market has grown significantly. Sys-
tems such as GSM have matured, and new systems such as UMTS, Bluetooth and
IEEE802.11 are now commercially available. In handsets the level of integration has
increased, in order to reduce the number of chips per handset as well as the number
of external components. In many cases CMOS is the technology of choice for all
parts except the power amplifier.
However, for frequencies up to several GHz and low to medium output power,
the research interest for highly integrated CMOS power amplifiers (PAs) has
increased [1-7]. They may be an alternative to stand-alone power amplifiers, offering
a higher level of integration in a relatively cheap technology, generally in exchange
for less efficiency and a lower maximum output power.
When having the PA on the same chip as a VCO (voltage controlled oscillator),
one of the problems occurring is oscillator pulling, i. e. the VCO oscillation fre-
quency changes due to the PA output signal. This is a problem if the PA and VCO are
operating at nearly equal frequencies. for instance in a direct-conversion or low-IF
transmitter. Several strategies can be used to alleviate this problem, such as compos-
ing the LO signal from two VCOs in a direct conversion transmitter or by upconver-
sion in several steps [8]. The approach used in this work is to have a built-in
upconverter in the power amplifier by cancelling the fundamental signal and utilizing
the second harmonic, thus making sure that the VCO and PA are operating at differ-
ent frequencies.
In mixers, so-called even-harmonic conversion has been widely used [9-10],
especially for millimeter-wave or receiver applications. With regard to power ampli-
fiers the technique has been described and used previously [11-13], but has to the
authors’ knowledge not been used in CMOS integrated PAs.
For fully integrated power amplifiers, which include the output impedance trans-
formation network, the limited quality factor of the integrated passives diminishes
the efficiency. An efficiency analysis of the PA with transformation network as pre-
sented in this work will be given.
Since many wireless communication systems operate with an output power in
the 10 - 20 dBm range for the handset, this PA was designed for an output power in
that range, aiming at a high efficiency. Moreover, linearity was not considered to be a
critical issue since many wireless systems use a constant envelope modulation
scheme. Therefore the PA was biased in class C.
170 Part II. Included Papers

2. Power Amplifier Analysis

One of the frequency components automatically generated in a PA biased in non-
class A is the second-order harmonic. Thus, internal frequency doubling may be
achieved if this harmonic is large enough compared to other output harmonics. When
the drains of two stages are tied together to the same load, as shown in Fig. 1a, the
odd harmonics are cancelled if the inputs are driven with a differential signal. This
may be referred to as a push-push configuration [11].
An important issue when using frequency doubling in the PA is signal contents.
A narrowband FM input signal can be written as
x ( t ) = A cos ω c t – Am sin ( ω c t ) ∫ x BB ( t ) dt , where m ∫ x BB ( t ) dt « 1 . The second order
output signal is given by:

1
x ( t ) ≈ A DC + --- cos ( 2ω c t ) – m sin ( 2ω c t ) ∫ x BB ( t ) dt
2 2
(1)
2
As can be seen, the 2nd order harmonic carries the same signal information as the
fundamental. This approximation is valid for most current commercial mobile com-
munication systems such as for instance GSM, DECT and Bluetooth. From the
above equation it can also be seen that a phase shift in the input signal will result in a
double phase shift in the output signal. Thus, if a quasi-differential amplifier is used
in order to get a differential output signal, the second stage must be driven with a 90°
phase shift relative to the first stage, as shown in Fig. 1b. The PA is thus driven with
quadrature signals.

Ideal PA response
Assuming that the output stage of the PA can be modeled as an ideal current source
with a maximum voltage swing of 2VDD at the drain node, the DC, fundamental and

Vout Vout+ Vout-

Vin+ Vin- Vin∠0° Vin∠180° Vin∠90° Vin∠270°

a. b.
Fig. 1. a). A single-ended PA stage with cancelled odd harmonics, b). differential ver-
sion.
Paper V A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling 171

2nd order response of the PA depend on the conduction angle or class in which the
PA is biased [14]. The DC current is given by
I max 2 sin α ⁄ 2 – α cos α ⁄ 2
I DC = ---------- ⋅ ---------------------------------------------------- (2)
2π 1 – cos α ⁄ 2
where Imax is the maximum output current and α is the conduction angle (in radians).
The magnitude of the second order harmonic may be written as
α⁄2
1 I max
I 2 = ---
π ∫ - [ cos θ – cos α ⁄ 2 ] cos 2θ dθ
---------------------------
1 – cos α ⁄ 2
(3)
–α ⁄ 2
I max α
= ---------- ⋅ ----------------------------  – --- sin ------- + sin ---
1 1 3α
2π 1 – cos α ⁄ 2  3 2 2

This results in a maximum efficiency for the second order harmonic of

 sin α --- – --- sin -------

1 3α
P2 V DD I 2 1  2 3 2
η 2 = --------- - = --- --------------------------------------------------------
- = ----------------------- (4)
P DC 2V DD I DC 2 ( 2 sin α ⁄ 2 – α cos α ⁄ 2 )

For this ideal PA both the fundamental and second order responses (output cur-
rents normalized to the maximum output current Imax), as well as the efficiencies η1
[14] and η2 are depicted in Fig. 2, as a function of the conduction angle α.
From Fig. 2 it can be seen that the 2nd order response is approaching the funda-
mental for small conduction angles, i.e. for a PA biased deep in class C. Moreover,
the efficiency is high in that region, also for the 2nd order output signal. A disadvan-
tage of deep class C is, however, that the maximum output power is relatively low.

0.7 100

90
0.6

80
I1
η1
0.5 70
efficiency [%]

60
Io/Imax

0.4
Idc
50

0.3
40

0.2 30

I2 20 η2
0.1
10

0 0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
alfa alfa

a. b.
Fig. 2. a). Ideal normalized DC, fundamental and second order output current as function of
the conduction angle, b). drain efficiency for the fundamental and second-order output.
172 Part II. Included Papers

In this deduction it is assumed that the PA does not have a so-called knee voltage
Vknee [14], that only the relevant harmonic is seen at the output, and that the load
resistance Ropt is always optimized for maximum voltage swing (2VDD) with maxi-
mum current swing Imax.

Maximum output power

The maximum linear output power for an ideal PA, modeled as a current source with
a certain drain bias voltage VDD, is given by

2
V DD
P out, max = -------------
- (5)
2R opt

where Ropt, the impedance seen at the drain, is the load resistance transformed by a
transformation network (see Fig. 3) designed to achieve maximum current and volt-
age swing simultaneously.
The MOSFET DC current is supplied through L1. The section formed by Lbw
(the output bondwire inductance) and C3 can be seen as a low-pass up-transforma-
tion L-section, and the section C1 and C2 as a down-transformation stage. In theory
this provides us with enough degrees of freedom to ensure sufficient bandwidth
while being able to freely choose the transformation ratio. However, both parasitics
and size limitations for integrated passive components limit the impedance transfor-
mation ratio. Parasitic capacitances from the pad may be included in C3, while para-
sitic capacitances at the drain are included in C1. For the PA with internal frequency
doubling the network must be tuned so that the desired impedance transformation is
achieved at twice the PA input frequency.
Assuming all passive components are ideal, the output power will be the same as
the power at the drain. For a linear output power of around 15 dBm (32 mW) and a
supply voltage of 3.3V, Ropt becomes 172 Ω, implying an upward impedance trans-

L1
C1
VDD out
Lbw
C2 T
RL
Ropt

C3

a. b.
Fig. 3. a). A PA with transformation network (shaded area), b). an ideal model.
Paper V A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling 173

formation with respect to the standard 50 Ω load. However, this is highly dependent
on both the desired output power and the supply voltage. Due to non-idealities in the
PA and transformation network, Ropt must be chosen with some margin for power
loss, i.e. a lower Ropt is chosen. In the next session we will look more into non-ideal-
ities of the transformation network.

3. Implementation
The quasi-differential PA as described in the previous section was implemented in a
0.18µm 1P6M CMOS technology with the option of 3.3V supply. Since we aimed at
output powers of 15 - 20 dBm, this supply voltage was chosen, and thus non-mini-
mum length MOSFETs were used in the final stage. One test chip included a passive
polyphase filter, a pre-amplifier and the PA, as shown in Fig. 4, while a second test
chip included both a quadrature VCO and the PA (consisting only of a final stage), as
shown in Fig. 5.
The motivation for the circuit in Fig. 4 was to test the concept of internal fre-
quency doubling, as well as the output power and efficiency of the final PA stage.
The polyphase filter provides the driving stage with I- and Q- signals, but has a sig-
nificant signal loss. The driving stage then amplifies the signal again.
For the VCO core in the circuit of Fig. 5 PMOSFETs were used, so that the
VCO output voltage swings around ground, the desired bias voltage of the PA input.
The two blocks can then be connected without buffers or coupling capacitors; a dis-
advantage is that this fixes the PA input bias voltage, while an advantage is that no

Vi+ Vo+
Vout+ Vout-
Vo-
Vi-

Vi+
Vo+
Vo-
Vi-

Vo+ Vo-
Vi+ Vi-

Fig. 4. Simplified schematic of the stand-alone PA including polyphase filter and driving stages.
174 Part II. Included Papers

Vout+ Vout-

Vctrl

vctrl
+ M1 M2 -

Vi+ Varactor Vi- Varactor

Vq- Vq+

Fig. 5. Schematic of the VCO and PA, including the varactor with continuous and discrete
tuning.

signal degradation will take place between the VCO and PA. The switched tuning of
the varactor as shown in Fig. 5 has been described earlier [15].

Non-idealities of the PA implementation

The equation for the maximum output power, Eq. 5, is valid under the assump-
tion that the transformation network is ideal (i.e. lossless), and that the PA transistor
does not have a knee voltage Vknee. First we will look into the non-idealities of the
final stage of the PA.
One of the most crucial non-idealities in any PA implementation is the knee
voltage, i.e. the minimum drain voltage necessary to have the PA operating as an
amplifier. Vknee will reduce the maximum voltage swing and thus the maximum out-
put power, according to
2
( V DD – V knee )
P out, max = ------------------------------------- (6)
2R opt
Paper V A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling 175

For deep submicron CMOS technologies Vknee may be up to 50% of VDD, using the
common definition for the knee voltage [14]. This may be considered too high; also
in the triode region the final stage may still operate as an amplifier. The knee voltage
reduces the efficiency with a factor of
V DD – V knee
η knee = -----------------------------
- (7)
V DD

Non-idealities of the transformation network

The integrated passives that make up the impedance transformation network, includ-
ing the “RF choke” inductor L1, all have a limited quality factor. In this design both
poly-insulator-silicon and metal-insulator-metal capacitors are used. The inductors
are differential, saving area and yielding a higher Q factor. One of the inductors is a
so-called stacked inductor with 3 metal layers, while for the other one only the top
layer is used. The inductor design and modeling was done in-house [16]. The trans-
formation network was designed to transform the 50 Ω antenna impedance to
approximately 90 Ω at the frequency of operation.
For the transformation network of Fig. 3 with suitable capacitor and inductor
values, including a Q factor of 12 for the inductor L1, MATLAB simulations show an
efficiency of the transformation network of 75%, i.e. the power loss from drain to
output will be about 1.2 dB. Moreover, in a real impedance transformation network
also capacitor non-idealities and interconnect parasitics will cause power losses.

Combined efficiency example

With a conduction angle α=2.1 (giving the maximum 2nd order output current, see
Fig. 2), Vknee/VDD=0.1 and a Q factor of 12 for inductor L1, the combined efficiency
following from Eqs. 4 and 7 becomes:
η tot = η 2 η knee η Q = 0.64 × 0.9 × 0.75 = 0.43 = 43% (8)

In the above analysis the impact of FET non-linearity (apart from the knee voltage)
and efficiency was not taken into account.

4. Results
In Fig. 6 the chip micrograph of the PA with VCO is shown. For the measurements
both the stand-alone PA and the PA with VCO were packaged in an LCC package
and attached to a PCB.
176 Part II. Included Papers

VCO

PA

Fig. 6. A chip micrograph of the PA with VCO.

The stand-alone PA
The purpose of this circuit was to verify that the internal frequency doubling worked,
and to characterize the final stage. Due to the on-chip polyphase network used to
generate the quadrature phases the gain is low. In the measurements the circuit was
therefore preceded by a Mini-Circuits amplifier.

In Fig. 7 measurement results for the stand-alone PA are shown,. compensated for
the power loss in output cables which added up to approximately 1.8 dB at 2.3 GHz.
Stand−alone PA; VddDR=3.3 Stand−alone PA; VddDR=3.3
15 12

Vdd,PA=3
10
10

5 Vdd,PA=3.3

8
0
efficiency [%]
Pout [dBm]

−5
= Vdd,PA=3
6

= Vdd,PA=3.3

−10
4

−15

2
−20

−25 0
−15 −10 −5 0 −15 −10 −5 0
Pin [dBm] Pin [dBm]

a. b.
Fig. 7. Measured results for the stand-alone PA for Vddpa=3.3 and 3 V, a). output power,
b). drain efficiency.
Paper V A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling 177

Stand−alone PA; VddPA=3.3, VddDR=3.3 Stand−alone PA; VddPA=3.3, VddDR=3.3

15 10
uncompensated
9 uncompensated
10
compensated
8
5 compensated
7

0
6

efficiency [%]
Pout [dBm]

−5 5

4
−10

3
−15
2

−20
1

−25 0
−15 −10 −5 0 −15 −10 −5 0
Pin [dBm] Pin [dBm]

a. b.
Fig. 8. Results for uncompensated and compensated outputs, a). output power, b). drain
efficiency.

Parasitics related to the bondwires, package and board were estimated and taken into
account in the design. S22 measurements showed a phase difference between the sig-
nals at Vout+ and Vout-, caused by inequality in bondwire parasitics for the symmetri-
cal differential output. This problem was more prominent when the PA was
operating with large signals. The mismatch in S22 was largely corrected by adding
discrete components at the outputs Vout+ and Vout-. The measurement results are
shown in Fig. 8.
The correction resulted in a slight decrease in maximum output power and drain
efficiency.

The PA with VCO

The differential outputs of this circuit were corrected in order to have approximately
equal S22 and suitable Ropt at the frequency of operation. The matching was worse
than for the stand-alone PA, mainly due to the discrete values of the external compo-
nents.
In Fig. 9 the output power and efficiency as function of Vdd,vco is shown.
Increasing Vdd,vco is equivalent to increasing the input power of the PA stage. The
maximum output frequency was 3.27 GHz. The VCO used in this circuit was not
optimized for the purpose. Therefore, it could not drive the PA sufficiently which had
a negative impact on the efficiency and output power. Moreover, the oscillation fre-
quency was not in agreement with the optimum PA operating frequency. Therefore,
passive off-chip components were used to tune the PA output to the desired fre-
quency.
178 Part II. Included Papers

PA + VCO; VddPA=3.3 PA + VCO; VddPA=3.3

10 5

4.5
5

0
3.5

efficiency [%]
Pout [dBm]

−5

2.5

−10
2

−15 1.5

1
−20
0.5

−25 0
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD,vco [V] VDD,vco [V]

a. b.
Fig. 9. Measured results for the PA with VCO as a function of Vdd,vco, a). output power, b).
drain efficiency.

In Fig. 10 the output frequency vs. control voltage is shown, as well as the out-
put power and drain efficiency.
The output frequency was measured for a VCO control word of (1111). Maxi-
mum VCO oscillation frequency was 1.637 GHz, the minimum oscillation frequency
1.522 GHz, resulting in a VCO tuning range of 115 MHz or 7.3% for one control
word setting.
Fig. 10b shows that the output power and thus drain efficiency is varying with
Vctrl. This is partly due to the PA frequency response, as shown in Fig. 11, and partly
to the dependence of the VCO tank quality factor on Vctrl. The output power is
almost constant in the frequency range 3.05-3.23 GHz with a variation of 0.7 dB,
while decaying for higher frequencies. For this measurement the VCO drive was not

PA + VCO; Vdd,vco=3.3, Vdd,PA=3.3 PA + VCO; Vdd,vco=3.3, Vdd,PA=3.3

3.3 10
10
9

3.25
8
fout=2*fosc [GHz]

efficiency [%]

7
3.2
Pout [dBm]

3.15 5
5
4

3.1
3

2
3.05

3 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Vctrl [V] Vctrl [V]

a. b.
Fig. 10. Measurements for varying Vctrl, a). output frequency, b). output power and drain
efficiency.
Paper V A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling 179

PA + VCO; Vdd,PA=3.3
8

Pout [dBm]
4

0
3 3.05 3.1 3.15 3.2 3.25 3.3
fout [GHz]

Fig. 11. Frequency response of the PA output stage.

maximum, thus the output power is lower than for the measurements shown in Fig.
9.
Fig. 12 shows the output power as function of Vdd,PA, illustrating the knee
effect, and the drain efficiency. The maximum efficiency occurs for relatively low
supply voltages; this illustrates the fact that for equal driving power, the PA with low
supply voltage has a clipped output voltage waveform, which may be beneficial for
the efficiency [14]. For even lower supply voltages (Vdd,PA < 0.6 V, see Fig. 12b) the
MOSFET will be in triode and thus have a lower gm, resulting in a decreasing effi-
ciency.
Measurements of both circuits showed that the gain in each block is less than
expected from simulations. This may be due to a lower transistor gm or lower induc-
tor Q value. This has a large impact on the total gain, but also on the efficiency of the

PA + VCO; Vdd,vco=3.3 PA + VCO; Vdd,vco=3.3

10 10

9
5
8

0 7

6
efficiency [%]

−5
Pout [dBm]

−10
4

3
−15

−20
1

−25 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Vdd,PA [V] Vdd,PA [V]

a. b.
Fig. 12. Results for varying Vdd,PA, a). output power, b). drain efficiency.
180 Part II. Included Papers

PA and power consumption of the VCO. In Table 1 the measurement results are sum-
marized.
TABLE I. SUMMARY OF MEASUREMENT RESULTS

maximum PA output power 15 dBm

maximum PA drain efficiency 10.7%
VCO frequency range 1.522-1.637GHz
active area: stand-alone PA 1.44 mm2
VCO + PA
2.25 mm2

In table 2 this work is compared to other fully integrated CMOS power amplifi-
ers. It must be noted that this is the only PA with internal frequency doubling. As
explained in Section II, the efficiency and the output power are degraded since the
2nd harmonic is taken instead of the fundamental.
TABLE II. COMPARISON OF FULLY INTEGRATED CMOS PAS

freq. output
Pout (dBm) η (max) technology other class
(GHz) matching

[2] 33.4 (@PAEmax) 2.4 31% (PAE) 0.35um (Bi)CMOS on-chip - E/F3

[3] 20 (max) 1.9 16% (η) 0.8um CMOS on-chip - F?

[4] 17.5 (max) 2.4 16.4% (PAE) 0.35um CMOS partly on-chip - A

[5] 9 (@P-5dB) 2.4 16% (P-5dB) 0.18um CMOS partly on-chip - AB?

[6] 18.6 (@PAEmax) 0.9 30% (PAEmax) 0.6um CMOS on-chip - C

this 15 (max) 2.4 10.7% (η) 0.18um CMOS on-chip freq. dou- C
work bling

5. CONCLUSIONS
A fully integrated class-C power amplifier with internal frequency doubler has been
designed and measured. A 0.18µm 1P6M CMOS technology was used. The circuit is
suitable for a direct-conversion or low-IF transmitter, since the PA and VCO do not
operate at the same frequency. Thus, VCO pulling will be reduced. The maximum
output power is 15 dBm, with a maximum drain efficiency of 10.7%. The concept of
internal frequency doubling was tested both in a stand-alone PA and a PA with VCO
on the same chip.
Paper V A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling 181

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