CHAPTER

1. INTRODUCTION
:1.1

BACKGROUND:
In today’s fast technologically developing world, the shift has been towards
construction of small and portable devices. As the number of these
battery operated, processor driven equipments increase and their performance
demand is expected to bemore, there is a need of increasing their processing
speed and reducing their powerdissipation. In such a consumer controlled
scenario, these demands mean a seriouslook into the construction of the
devices. These Processors used for such purposes butalso, in these processors,
major operations such as FIR filter design, DCT, etc aredone through
multipliers. As multipliers are the major components of DSP,optimization in
multiplier design will surely lead to a better operating DSP.1.2

IMPORTANCE OF MULTIPLIER :

Computational performance of a DSP system is limited by its

multiplication performance and since, multiplication dominates the execution ti
me of most DSPalgorithms therefore high-speed multiplier is much desired .
Currently, multiplicationtime is still the dominant factor in determining the
instruction cycle time of a DSPchip. With an ever-increasing quest for greater
computing power on battery-operatedmobile devices, design emphasis has
shifted from optimizing conventional delay timearea size to minimizing power
dissipation while still maintaining the
high performance . Traditionally shift and add algorithm
has been implemented to designhowever this is not suitable for VLSI
implementation and also from delay point ofview. Some of the important
algorithm proposed in literature for VLSI implementablefast multiplication is
array multiplier and Wallace tree multiplier This paper presentsthe
fundamental technical aspects behind these approaches. The low power and
highspeed VLSI can be implemented with different logic style. The three
importantconsiderations for VLSI design are power, area and delay. There are
many proposed

logics (or) low power dissipation and high speed and each logic style has its
ownadvantages in terms of speed and power.
1.3 MULTIPLIER SCHEMES:

There are two basic schemes in the multiplication process.

They are serialmultiplication and parallel multiplication.

Serial Multiplication (Shift-Add)

It Computing a set of partial products, and then summing the partial
productstogether. The implementations are primitive with simple architectures
(used whenthere is a lack of a dedicated hardware multiplier)

Parallel Multiplication
Partial products are generated simultaneously Parallel implementations
areused for high performance machines, where computation latency needs to
beminimized.Comparing these two types parallel multiplication has more
advantage than theserial multiplication. Because the parallel type has lesser
steps comparing to the serialmultiplication. So it performs faster than the serial
multiplication.

1.4 MULTIPLIER FEATURES:

The features of the multiplier are

1.4.1 PIPELINING:

Pipelining allows this multiplier to accept and start the partial processof
multiplication of a set of data, eventhough a part of another multiplication is
taking place.

1.4.2 MIXED ARCHITECTURE:

The mixed type architecture has been considered, consisting of Wallace

treemultiplier. This allows taking the advantage of low delay of
Wallace multiplier.

1.4.3 CLOCKING:

Clocking has been so done as to allow the multiplier to work at its

highest clockfrequency without compromising with the perfect flow of partial
products in thestructure.
1.4.4 DATA RANGE:

The data range has been extended from initial 4x4 bit to 16x16 bit,which
isactually the required working data range for many of the DSP processors.
1.4.5 STRUCTURAL MODELLING:

This makes sure the best implementation of the multiplier, beit on ASIC or
inFPGA, and removes any chance of redundant hardware that may be
generated
CHAPTER 2

2.1 ADDER
In electronics, an adder is a digital circuit that performs addition of numbers. Inmodern computers
adders reside in the arithmetic logic unit (ALU) where otheroperations are performed. Although
adders can be constructed for many numericalrepresentations, such as Binary-coded decimal or
excess-3, the most common addersoperate on binary numbers. In cases where two's complement is
being used torepresent negative numbers it is trivial to modify an adder into an adder-subtracter.
2.2 TYPES OF ADDERS
For single bit adders, there are two general types. A half adder has two inputs,generally labeled
AandB, and two outputs, the sumSand carryC .Sis the two-bitXOR ofAandB, andCis the AND ofAandB
. Essentially the output of a half adderis the sum of two one-bit numbers, with C
being the most significant of these twooutputs.The second type of single bit adder is the full adder.
The full adder takes intoaccount a carry input such that multiple adders can be used to add larger
numbers. Toremoveambiguity between the input and output carry lines, the carry in is labeled Cior
Cin while the carry out is labeled Co or Cout . Half adder

Fig 1: Half adder circuit diagram

A half adder is a logical circuit that performs an addition operation on two binary digits. The half
adder produces a sum
and a carry value
which are
both binarydigits.

Following is the logic

table for a half adder:
A full adder is a logical circuit that performs an addition operation on three binary
digits. The full adder produces a sum and carries value, which are both binarydigits. It can be
combined with other full adders (see below) or work on its own.

Note that the final OR gate before the carry-out output may be replaced by anXOR gate without
altering the resulting logic. This is because the only discrepancy
between OR and XOR gates occurs when both inputs are 1; for the adder shown here,one can check
this is never possible. Using only two types of gates is convenient ifone desires to implement the
adder directly using common IC chips. A full adder
can be constructed from two half adders by connecting AandB to the input of one halfadder,
connecting the sum from that to an input to the second adder, connecting Ci tothe other input and
or the two carry outputs. Equivalently, S could be made the three- bit xor of A, B, and Ci and Co could
be made the three-bit majority function of A ,B ,and Ci. The output of the full adder is the two-bit
arithmetic sum of three one-bit numbers

CHAPTER 3
11
LITRETURE SURVEY3.1 BASIC MULTIPLIER ARCHITECTURES:
3.1.1
INTRODUCTION:
Basic multiplier consists ANDed terms (as shown in Fig 1) and array of fulladders and/or half adders
arranged so as to obtain partial products at each level.
These partial products are added along to obtain the final result. It is the differentarrangement and
the construction changes in these adders that lead to various type ofstructures of basic multipliers
.

Full Adder (FA)implementation is showing the two bits(A,B) and Carry In (Ci)as inputs and Sum (S)
and Carry Out (Cout) as outputs.

3.2 BINARY MULTIPLIER

 A Binary multiplier is an electronic hardware device used in digital electronicsor a computer or other
electronic device to perform rapid multiplication of twonumbers in binary representation. It is built
using binary adders.The rules for binary multiplication can be stated as follows1. If
the multiplier digit is a 1, the multiplicand is simply copied down andrepresents the product.2. If the
multiplier digit is a 0 the product is also 0.For designing a multiplier circuit we should have circuitry
to provide or do thefollowing three things:1. it should be capable identifying whether a bit is 0 or 1.2.
It should be capable of shifting left partial products.3. It should be able to add all the partial products
to give the products as sum of partial products.4. It should examine the sign bits. If they are alike, the
sign of the product will be a positive, if the sign bits are opposite product will be negative. The
sign bit of the product stored with above criteria should be displayed along with the product.From
the above discussion we observe that it is not necessary to wait until allthe partial products have
been formed before summing them. In fact the addition of partial product can be carried out as soon
as the partial product is formed. Notations:a – multiplicand b – multiplier p – product 13 Binary
multiplication ( eg n=4 )P = a×ban−1 an −2… a1a0

WALLACE TREE HARDWARE ARCHITECTURE: Fig 4: wallace tree hardware architech

Full Adder: