CHAPTER 1

Introduction
1.1

BACKGROUND:
In today’s fast technologically developing world, the shift has been towards
construction of small and portable devices. As the number of these battery operated, processor driven
equipments increase and their performance demand is expected to bemore, there is a need of
increasing their processing speed and reducing their powerdissipation. In such a consumer controlled
scenario, these demands mean a seriouslook into the construction of the devices. These
Processors used for such purposes butalso, in these processors, major operations such as FIR filter design, DCT, etc
aredone through multipliers. As multipliers are the major components of DSP,optimization in
multiplier design will surely lead to a better operating DSP.1.2

IMPORTANCE OF MULTIPLIER:
Computational performance of a DSP system is limited by its
multiplication performance and since, multiplication dominates the execution time of most DSPalgori
thms therefore high-speed multiplier is much desired . Currently, multiplicationtime is still the
dominant factor in determining the instruction cycle time of a DSPchip. With an ever-increasing
quest for greater computing power on battery-operatedmobile devices, design emphasis has shifted
from optimizing conventional delay timearea size to minimizing power dissipation while still
maintaining the high performance . Traditionally shift and add algorithm
has been implemented to designhowever this is not suitable for VLSI implementation and also from
delay point ofview. Some of the important algorithm proposed in literature for VLSI
implementablefast multiplication is array multiplier and Wallace tree multiplier This paper
presentsthe fundamental technical aspects behind these approaches. The low power and highspeed
VLSI can be implemented with different logic style. The three importantconsiderations for VLSI design
are power, area and delay. There are many proposed

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logics (or) low power dissipation and high speed and each logic style has its ownadvantages in terms
of speed and power.
1.3 MULTIPLIER SCHEMES:
There are two basic schemes in the multiplication process. They are serialmultiplication and parallel
multiplication.


Serial Multiplication (Shift-Add)

Parallel Multiplication
Partial products are generated simultaneously Parallel implementations areused for high performance
machines, where computation latency needs to beminimized. Comparing these two types parallel multiplication
has more advantage than theserial multiplication. Because the parallel type has lesser steps
comparing to the serialmultiplication. So it performs faster than the serial multiplication.
1.4 MULTIPLIER FEATURES:
The features of the multiplier are
1.4.1 PIPELINING:
Pipelining allows this multiplier to accept and start the partial processof multiplication of a set of
data, eventhough a part of another multiplication is taking place.

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1.4.2 MIXED ARCHITECTURE:
The mixed type architecture has been considered, consisting of Wallace treemultiplier. This allows taking the
advantage of low delay of Wallace multiplier.
1.4.3 CLOCKING:
Clocking has been so done as to allow the multiplier to work at its highest clockfrequency without
compromising with the perfect flow of partial products in thestructure.
1.4.4 DATA RANGE:
The data range has been extended from initial 4x4 bit to 16x16 bit,which isactually the required
working data range for many of the DSP processors.
1.4.5 STRUCTURAL MODELLING:
This makes sure the best implementation of the multiplier, beit on ASIC or inFPGA, and removes any
chance of redundant hardware that may be generated.

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CHAPTER 2

6
2.1 ADDER
In electronics, an adder is a digital circuit that performs addition of numbers. Inmodern computers
adders reside in the arithmetic logic unit (ALU) where otheroperations are performed. Although adders can
be constructed for many numericalrepresentations, such as Binary-coded decimal or excess-3, the most common
addersoperate on binary numbers. In cases where two's complement is being used torepresent negative numbers
it is trivial to modify an adder into an adder-subtracter.
2.2 TYPES OF ADDERS
For single bit adders, there are two general types. A half adder has two inputs,generallylabeled
Aand B, and two outputs, the sumS and carry C.S is the two-bitXOR ofA and B , and C is the AND of A and B.
Essentially the output of a half adder is the sum of two one - bit numbers , with C
being the most significant of these two outputs .The second type of single bit adder is the full
adder. The full adder takes into account a carry input such that multiple adders can be used to add larger
numbers. Toremoveambiguity between the input and output carry lines, the carry in is labeled
Ci
or
Cin
whilethecarryoutislabeled
Co
or
Cout
.
Half adder

Fig 1: Half adder circuit diagramA half adder is a logical circuit that performs an addition operation
on two binary digits. The half adder produces a sum and a carry value which are both binarydigits.

7
Following is the logic table for a half adder:
TABLE 1: HALFADDERA B C S
0000010110011110
Fig 2: Full adder circuit diagram
8
Schematic symbol for a 1-bit full adder
A full adder is a logical circuit that performs an addition operation on three binary
digits. The full adder produces a sum and carries value, which are both binarydigits. It can be combined
with other full adders (see below) or work on its own.
TABLE 2: FULL ADDERA B Ci C0 S
0000000101010010111010001101101101011111 Note that the final OR gate before the carry-out output may
be replaced by anXOR gate without altering the resulting logic. This is because the only discrepancy

9
between OR and XOR gates occurs when both inputs are 1; for the adder shown here,one can check
this is never possible. Using only two types of gates is convenient ifone desires to implement the
adder directly using common IC chips. A full adder
can be constructed from two half adders by connecting
A
and
B
to the input of one halfadder, connecting the sum from that to an input to the second adder, connecting
Ci
tothe other input and or the two carry outputs. Equivalently,
S
could be made the three- bit xor of
A
,
B
, and
Ci
and
Co
could be made the three-bit majority function of
A
,
B
,and
Ci
. The output of the full adder is the two-bit arithmetic sum of three one-bitnumbers.

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CHAPTER3