Experiment

Study of common emitter transistor amplifier circuit

1 Objectives
1. To design a common emitter transistor (NPN) amplifier circuit.
2. To obtain the frequency response curve of the amplifier and to determine the mid
frequency gain, Amid , lower and higher cut-off frequency of the amplifier circuit.

2 Theory
The most common circuit configuration for an NPN transistor is that of the common
emitter amplifier and that a family of curves known commonly as the output characteristic
curves, relates the collector current IC , to the output or collector voltage VCE , for different
values of base current IB . All types of transistor amplifiers operate using AC signal
inputs which alternate between a positive value and a negative value. Pre-setting the
amplifier circuit to operate between these two maximum or peak values is achieved
using a process known as “Biasing”. Biasing is very important in amplifier design as it
establishes the correct operating point of the transistor amplifier ready to receive signals,
thereby reducing any distortion to the output signal.
The single stage common emitter amplifier circuit shown below uses what is commonly
called “Voltage Divider Biasing”. The base voltage VB can be easily calculated using
the simple voltage divider formula below
VCC R2
VB =
R1 + R2

Thus, the base voltage is fixed by biasing and it is independent of base current as long as
the current in the divider circuit is large compared to the base current. Thus assuming
IB ≈ 0, one can do the approximate analysis of the voltage divider network without
using the transistor gain, β, in the calculation. Note that the approximate approach can
be applied with a high degree of accuracy when the following condition is satisfied:
βRE ≥ 10R2

Load line and Q-point

A static or DC load line can be drawn onto the output characteristics curves of the
transistor to show all the possible operating points of the transistor from fully “ON”

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 Figure 1: Typical transistor amplifier circuit in the CE mode.

(IC = VCC /(RC + RE )) to fully “OFF” (IC = 0). The quiescent operating point or Q-point
is a point on this load line which represents the values of IC and VCE that exist in the
circuit when no input signal is applied. Knowing VB, IC and VCE can be calculated to
locate the operating point of the circuit as follows:

VE = VB − VBE

So, the emitter current,

IE ≈ IC = VE /RE
and
VCE = VCC − IC (RC + RE )

It can be noted here that the sequence of calculation does not need the knowledge of β and
IB is not calculated. So, the Q-point is stable against any replacement of the transistor.
Since the aim of any small signal amplifier is to generate an amplified input signal at the
output with minimum distortion possible, the best position for this Q-point is as close
to the centre position of the load line as reasonably possible, thereby producing a Class
A type amplifier operation, i.e.,VCE = (1/2)VCC .

Coupling and bypass capacitors

In CE amplifier circuits, capacitors C1 and C2 are used as coupling capacitors to separate
the AC signals from the DC biasing voltage. The capacitors will only pass AC signals and
block any DC component. Thus, they allow coupling of the AC signal into an amplifier
stage without disturbing its Q point. The output AC signal is then superimposed on

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the biasing of the following stages. Also, a bypass capacitor, CE is included in the
Emitter leg circuit. This capacitor is an open circuit component for DC bias, meaning
that the biasing currents and voltages are not affected by the addition of the capacitor
maintaining a good Q-point stability. However, this bypass capacitor acts as a short
circuit path across the emitter resistor at high frequency signals increasing the voltage
gain to its maximum. Generally, the value of the bypass capacitor, CE is chosen to
provide a reactance of at most, 1/10th the value of RE at the lowest operating signal
frequency.

Amplifier Operation
Once the Q-point is fixed through DC bias, an AC signal is applied at the input using
coupling capacitor C1 . During positive half cycle of the signal VBE increases leading
to increased IB . Therefore, IC increases by β times leading to decrease in the output
voltage, VCE . Thus, the CE amplifier produces an amplified output with a phase reversal.
The voltage Gain of the common emitter amplifier is equal to the ratio of the change in
the output voltage to the change in the input voltage. Thus,

Vout ∆VCE
AV = =
Vin ∆VBE
The input (Zi ) and output (Zo ) impedances of the circuit can be computed for the case
when the emitter resistor RE is completely bypassed by the capacitor, CE :

Zi = Ri k R2 k βre and Zo = RC k ro

where re (26 mV/IE ) and ro are the emitter diode resistance and output dynamic resis-
tance (can be determined from output characteristics of transistor). Usually ro ≥ 10RC ,
thus the gain can be approximated as

Vout βIB (RC k ro ) RC

AV = = − .
Vin IB βre re

The negative sign accounts for the phase reversal at the output.

Note: In the circuit diagram provided below, the emitter resistor is split into two in
order to reduce the gain to avoid distortion. So the expression for gain is modified as
RC
AV 
(RE + re )

2.1 Frequency response curve

The performance of an amplifier is characterized by its frequency response curve that
shows output amplitude (or, more often, voltage gain) plotted versus frequency (often

3
in log scale). Typical plot of the voltage gain of an amplifier versus frequency is shown
in the figure below. The frequency response of an amplifier can be divided into three
frequency ranges.

Figure 2: Illustration of the frequency response of a CE amplifier.

The frequency response begins with the lower frequency range designated between 0
Hz and lower cut-off frequency. At lower cut-off frequency, fL , the gain is equal to
0.707Amid . Amid is a constant mid-band gain obtained from the mid-frequency range.
The third, the higher frequency range covers frequency between upper cut-off frequency
and above. Similarly, at higher cut-off frequency, fH , the gain is equal to 0.707Amid .
Beyond this the gain decreases with frequency increases and dies off eventually.

The lower frequency range

Since the impedance of coupling capacitors increases as frequency decreases, the voltage
gain of a BJT amplifier decreases as frequency decreases. At very low frequencies, the
capacitive reactance of the coupling capacitors may become large enough to drop some
of the input voltage or output voltage. Also, the emitter-bypass capacitor may become
large enough so that it no longer shorts the emitter resistor to ground.

The higher frequency range

The capacitive reactance of a capacitor decreases as frequency increases. This can lead
to problems for amplifiers used for high-frequency amplification. The ultimate high
cutoff frequency of an amplifier is determined by the physical capacitances associated
with every component and of the physical wiring. Transistors have internal capacitances
that shunt signal paths thus reducing the gain. The high cutoff frequency is related to a
shunt time constant formed by resistances and capacitances associated with a node.

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Design

Before designing the circuit, one needs to know the circuit requirement or specifications.
The circuit is normally biased for VCE at the mid-point of load line with a specified
collector current. Also, one needs to know the value of supply voltage VCC and the
range of β for the transistor being used (available in the datasheet of the transistor).
Here the following specifications are used to design the amplifier:

VCC = 12 V and IC = 1 mA

Start by making VE = 0.1VCC . Then RE = VE /IE (Use IE ≈ IC ).

Since VCE = 0.5VCC , Voltage across RC = 0.4VCC , i.e., RC = 4RE .
In order that the approximation analysis can be applied, R2 ≤ 0.1βRE . Here β is the
minimum rated value in the specified range provided by the datasheet (in this case
β = 50).
Based on these guidelines the components are estimated and the nearest commercially
available values are used.

3 Circuit components and equipment

1. Transistor: BC547 (or equivalent general purpose npn)
2. Resistors: R1 = 26(27) kΩ, R2 = 5(4.7 + 0.22) kΩ, RC = 4(3.9) kΩ, RE = 1 kΩ
(RE1 = 470 Ω, RE2 = 560 Ω)
3. Capacitors: C1 = C2 = 1 µF (2 Nos.), CE = 100 µF
4. Power Supply (VCC = 12 V)
5. Oscilloscope
6. Function Generator (∼ 100 − 200 mVpp , sinusoidal for input signal)
7. Breadboard
8. Connecting wires

4 Circuit diagram
The circuit diagram for the experiment is shown in Figure 3.

5 Procedure
1. Measure and record all the values of resistance and capacitance and β of the
transistor using a multimeter. Configure the circuit as per the diagram.

2. Apply supply voltage to the circuit. Measure and record all the DC parameters
listed in Table 1 in absence of the AC signal.

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 Figure 3: Circuit for studying common emitter amplifier circuit.

3. Next, set the function generator in 20 Hz “Frequency” range. Connect the output
to the oscilloscope and adjust the “Amplitude” knob till you get a sinusoidal input
signal, Vi ≈ 100 − 200 mV peak-to-peak value.
Note: Do not change this setting throughout the experiment.

4. Now apply this input signal to the circuit you have made keeping the connection
to oscilloscope intact. Feed the output of the circuit to the other channel of
oscilloscope. Take care to make all the ground pins common.

5. With input signal amplitude always constant, increase signal frequency slowly.
Observe, measure and record the output voltage, Vo . Scan the entire frequency in
the range 20 Hz – 2 MHz. You may have to measure Vi and take the ratio Vo /Vi
each time in case input fluctuation is too large to hold constant.

6. Calculate the voltage gain for each frequency. Observe the inverted output.

7. Plot the frequency response curve, i.e. voltage gain in dB versus frequency on a
semilog graphsheet.

8. Estimate the mid-frequency gain and also the lower and higher cut off frequencies
and hence the bandwidth.

6 Observations
β=
R1 = , R2 = , RC = , RE =
C1 = , C2 = , CE =

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 VCC = 12 V

Parameter Computed value Observed value

VB (V)
VE (V)
IC ≈ IE (mA)
VCE (V)

Q-point is at ( V, mA)
Table 1: DC analysis of the circuit.

VCC = 12 V
Vo(pp)
Sl. No. Frequency f (kHz) Vo(pp) V Gain AV = Gain (dB)
Vi(pp)
1
2
...

Table 2: Frequency response.

Calculations: re = , Zi = , Zo = )
Theoretical value of AV in mid-frequency range =

7 Graphs
Plot the frequency response curve (semi-log plot) and determine the cut-off frequencies,
bandwidth and mid- frequency gain.

8 Results

9 Precautions
1. Vary the input signal frequency slowly.

2. Connect electrolytic capacitors carefully.

3. Make sure before switching power supply on.

4. Switch off the power supply after experiment.