Lecture08 Ee326 Output Stages
Lecture08 Ee326 Output Stages
Spring 2022
Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• Homework 8 due Apr 28
• Exam 3 May 5
• 12:30 – 2:30
• Closed book w/ one standard note sheet
• 8.5”x11” front & back
• Bring your calculator
• Emphasis will be on Lectures 7-8
• Sample Exam3s posted on website
• Reading
• Razavi Chapter 14
2
Agenda
• General Output Stage Considerations
• Emitter Follower as a Power Amplifier
• Push-Pull Stage
• Improved Push-Pull Stage
• Large-Signal Considerations
• Heat Dissipation
• Efficiency and Power Amplifier Classes
3
Why Special Output Stages
or Power Amplifiers?
• Power amplifiers are necessary to efficiently drive
a load with high power
• Examples
• A cellphone may need 1W of power at the antenna
• Audio systems require tens to hundreds of Watts
4
Power Amplifier Characteristics
• Can drive a small “heavy”
load resistance
• Example: Speaker resistance Example : Delivering 1W to an 8 speaker
can be 4-16 2
V 1
Sinusoidal Pout P 1W
• Delivers large current levels 2 RL
This results in a peak voltage
• Often in the hundreds of mA VP 4V
and a peak current
• Requires large voltage swings IP
VP 4V
500mA
RL 8
• Draws a large amount of
power from the supplies
• Dissipates a large amount of
power, and thus can get hot
5
Power Amplifier Performance Metrics
• Linearity or Distortion
• Audio amplifiers must have low distortion to
reproduce music with high fidelity
• Power Efficiency
Power Delivered to Load
Power Drawn from Supply
However, for small Vin, there is a dead zone (both Q1 and Q2 are
off) in the I/O characteristic, resulting in gross nonlinearity
The dead zone is from -|VBE2| ≤ Vin ≤ VBE1
CH 13 Output Stages and Power Amplifiers 14
Small-Signal Gain of Push-Pull Stage
RL
Av
RL re
For large Vin, the output follows the input with a fixed DC
offset, however as Vin becomes small the output drops to zero
and causes “Crossover Distortion.”
CH 13 Output Stages and Power Amplifiers 16
Agenda
• General Output Stage Considerations
• Emitter Follower as a Power Amplifier
• Push-Pull Stage
• Improved Push-Pull Stage
• Large-Signal Considerations
• Heat Dissipation
• Efficiency and Power Amplifier Classes
17
Improved Push-Pull Stage
I out
Vout=0
VX=0
IC 3 I C1
VD1 VT ln
VBE1 VT ln
I S , D1 I S ,Q1
For bias point analysis, the circuit can
be simplified to the one on the right, I S ,Q1
I C1 IC 3
which resembles a current mirror I S , D1
For a well-defined IS ratio, D1 can be
realized as a diode-connected transistor
CH 13 Output Stages and Power Amplifiers 23
Small-Signal Analysis - I
In order to derive the gain of the circuit, we can treat it as a two - stage amplifier
vout vN vout
vin vin vN
Assuming VA and rD 0, the second stage can be viewed as 2 parallel emitter followers
vout RL RL
vN RL re1 re 2 R 1
L
g m1 g m 2
1 rO 3 || rO 4
Rout
g m1 g m 2 ( g m1 g m 2 )(r 1 || r 2 )
The picture can't be display ed.
Design Specs :
Common Emitter Av 5
Output Stage Av 0.8
with RL 8, npn 2 pnp 100
and assume I C1 I C 2
• Another output stage issue is that the Q2 PNP transistor typically have
low current gain () and low fT
• Using a composite transistor consisting of an emitter follower PNP (Q3)
and a common emitter NPN (Q2) allows for improved performance
Rin r 3 3 2 1RL
• The modified PNP emitter follower has a reduced input range by VBE2
CH 13 Output Stages and Power Amplifiers 35
HiFi Design
vout 1 1 R
vout 1 1
g m 4 r 1 r 2 g m1 g m 2 RL vin K R2 R2
vin R1 R2
• As gm1 and gm2 vary • Placing the output stage in a
dramatically during large negative feedback loop allows for
signal operation, the circuit a more constant gain, and thus
displays nonlinear distortion better linearity
CH 13 Output Stages and Power Amplifiers 36
Short-Circuit Protection
• Drawbacks
• r increases output resistance
• Voltage drop across r reduces
maximum output swing
1 T
Pav
T 0
I CVCE dt
1 T V sin t
Pav 0 I1 P VCC VP sin t dt
T RL
0
0 VCCVP sin t VP2 sin 2 t
1 T
0 I1VCC I1VP sin t dt
T RL RL
1 T VP2
0 I1VCC 1 cos 2t
V T 2 RL
Pav I1VCC P
2 V
I1 P
Pav ,max I1VCC VP2
RL V
I1VCC I1VCC P
2 RL 2
1 T 1 T
PI1 0
I V
1 out VEE dt 0
I1 VP sin t VEE dt
T T
1 T 0
I1VP sin t I1VEE dt
T 0
PI1 I1VEE
1 T2 1 T
VCC VP sin t VP sin t dt
2
T 0 T 0
Pav V I
CE C dt
RL
1 T 2 VCCVP VP2 2
0 sin t sin tdt
T RL RL
0
1 T 2 VCCVP 1 T 2 VP2
0 sin tdt 0 1 cos 2t dt
T RL T 2 RL
VCCVP VP2
RL 4 RL
VP VCC VP
Pav
RL 4
2VCC
Maximum power occurs with VP
2
VCC
Pav ,max 2
RL
CH 13 Output Stages and Power Amplifiers 42
Example: Push-Pull Pav
VP VCC VP
Pav If Vp = 4VCC/π → Pav=0
RL 4
Impossible since Vp cannot go
above supply (VCC)
CH 13 Output Stages and Power Amplifiers 43
Heat Sink
1 VP
PP
4 VCC VP
52
Class A Power Amplifiers
• Each transistor is on for the entire cycle
• Emitter follower is a Class A power amplifier
56