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Application Note AN4103

An Fairchild power Switch(FPS) Based Switched
Mode Power Supply for Monitor Use

1. Introduction 1-1. Functions of Each Pin

This application note describes a flyback converter using the 1.DRAIN: Connects to the output MOSFET
Fairchild Power Switch (FPS) in a switched mode power drain and is rated at up to 650V. It is designed
supply (SMPS) for a monitor. The Fairchild Power Switch to directly drive the converter transformer.
(FPS) integrates a MOSFET and its control IC into one
2.GND: Ground pin that connects to the
package, incorporating all of the required protection
output MOSFET source.
circuitry on chip. This simplifies the design of the SMPS,
which now requires fewer components, enhancing reliability 3.VCC : This is the control IC power (VCC) pin.
and increasing manufacturing productivity. Further, a The IC operates as soon as this pin reaches the
smaller component count increases reliability and therefore UVLO upper threshold voltage (15V). If VCC
decreases the cost of field maintenance. reaches 25V(typical) because of an output over
This application note reviews monitor SMPS design voltage, the over voltage protection circuit stops
considerations focusing on the features of the new KA5S the device switching.
range of devices. The KA5S0765C and KA5S09654QT
versions are of particular interest as they are available in the 4.Vfb: This pin accepts the output voltage error
smaller TO-220-5L and TO-220F-5L packages. The KA5S signal to control the output voltage. If Vfb reaches
range described in this application note was developed for 7.5V, latch shut down occurs.
applications requiring external frequency synchronization
such as in monitor power supplies. The KA5S range includes 5.VS/S : This pin connects to the soft
additional features that supplement and improve upon the start capacitor. It operates by charging to 5V
existing KA2S range.The KA5S is currently available in during normal operation and also synchronizes
650V versions supporting 7A, 9A and 12A switch currents. the internal oscillator to the sync signal.
Auto restart products are also available.
Table 1: Product Line-up (Monitor Application)
In display devices such as monitors and TVs, switching
Product Rating Package Pin
noise can effect the quality of the display. External
frequency synchronization moves the switching transitions KA5S0765C 7A/650V TO-220 (5Pin) 100
to the blanked part of the signal so that the noise does not KA5S0965 9A/650V TO-3P (5Pin) 135
appear on the screen. If there is no external synchronization
KA5S1265 12A/650V TO-3P (5Pin) 165
signal (DPMS), the power switch switches at an internally
set frequency of 20KHz to minimize switching losses. KA5S09654QT 9A/650V TO-220F (5Pin) 100

2. Internal Block and Important

Features
FSC 2-1. Internal Block and Features
FSC
5S0965
5S0765 • Current Mode Control Method
• Universal Voltage Power Supply Input
• Latch mode Shut Down
• Optimum Gate Driver Design
• Low Standby Power Consumption (Low Istart & Low
Iop)
1 234 5 1 2 3 4 5 • Various Internal Protection Circuits
TO-220-5L TO-3P-5L - Over Voltage Protection (OVP)
- Overload Protection (OLP)
Figure 1-1. Package Line-Up - Over Temperature Protection (TSD)

Rev. 1.0.1
©2001 Fairchild Semiconductor Corporation
AN4103 APPLICATION NOTE

- Over Current Protection (OCP) .(Additional Feature) • Reduction of secondary diode voltage stress at turn on
• Minimization of production defects through VCC surge and mode change by employing slope at sync Vth.
and internal diode reinforcement

+
+

VCC Drain
3 1

VZ VCC UVLO
32.5V + BIAS
- Vref +
15/9V
VREF SenseFET
2.5V UVLO
VS/S
+ 5 - CLK
Vth.sy OSC
+
VREF 7.2V VG
Vfb 5.8V S Q
4 -
2.5R R
0.9mA R +
VREF VS
4µA VCC
Voffset
S Rsense
OLP
(Vfb=7.5V) Q 2
R
TSD 1µS Window GND
(Tj=150°C) Open Circuit
OVP
(VCC=25V) OCP Power-on Reset
(VS=0.8V) (VCC=6.5V)

Figure 2-1. Block Diagram

2-2. Starting resistance design and UVLO

Input voltage range: 80 ~ 265V (AC) At Minimum input
1 2
voltage Va(ave), the starting resistance is Va ( rms ) = ------- ∫ ( Vp sin t – 15 ) dt
2π
π
Va ( rms ) ≅ 177V (Vp = 265 2 )
∫
1
Va ( ave ) = ------- ( Vp ⋅ sint – 15 ) dt
2π 2
o
P ( loss ) = Va ( rms ) = 0.3W
---------------------------
2Vp – 15π Rstart
= -----------------------------
2π
Select: Rstart = 100KΩ 0.5W
2 × 80 2 – 15π
= ----------------------------------------- = 28.5V
2π
Rstart = 28.5 ÷ 200µA = 142.5K A resistance smaller than the start up current (Max 170uA)
divided by the lowest Vdc voltage must be used. The VCC
capacitor of the Fairchild Power Switch (FPS) is charged
and, at Maximum input voltage Va(rms), the power loss through the current sourced through the start up resistor.
When the VCC voltage increases above the start up voltage
threshold (15V), the power switch begins to switch the inter-
nal MOSFET. Once it starts to operate, the current used in
the control IC

©2001 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4103

suddenly increases to 7mA. The start up resistor cannot than the pre set load, but not as high as the load seen by a
supply this current so the transformer auxiliary winding now short circuit. For example, in a 100W SMPS, the overload
supplies most of the power after start up. If the VCC power protection circuit could be set to stop the power switch when
capacitor is too large, the start time is too long, so a the SMPS output is above 110W. A problem associated with
reasonable sized capacitor should be used. Generally, a good this type of protection circuit is that the circuit can produce
choice for this capacitor size is somewhere between 22uF an undesired shutdown due to a transient overload. The
and 47uF. Too small a capacitor can lead to Vcc passing the power switch triggers the protection circuit after a specific
UVLO threshold (9V) before the system has fully started. time. This determines whether the condition is a transient or
This would cause the device to shut down. a true overload and avoids false triggering. The over load
protection works as follows.
This operation is described in Figure 2-3. VCC only needs to Because the Fairchild Power Switch (FPS) uses current
be maintained above 9V at start up but should be set so that mode control, current above the set maximum cannot flow
OVP (Min. VCC voltage above 23V) is not triggered. through the switch. This restricts the maximum input power
Approximately 17 ~ 20V is appropriate for the VCC voltage. at a specific voltage. Therefore, if the power consumed at the
output exceeds this maximum, VO shown in Figure 2-4 falls
below the set voltage. The KA431(LM431) can draw only
DC LINK
Rg + set minimum current. As a result, the photocoupler's
CCC secondary current becomes almost zero. Therefore the
VCC current from the internal 0.9mA source flows through the
3 internal resistor (2.5R + R = 3K). Vfb goes to approximately
3V, at which time the 4uA current source starts to charge
Internal Bias
Power On
Cfb. Because the photo coupler's secondary current is almost
Reset + zero, Vfb continues to increase, and, when it reaches 7.5V,
5V
15V/9V the power switch shuts down. The shutdown delay time can
Vref
Latch -
VZ UVLO be easily determined as the time required to charge Cfb to
Comparator
6V
Fairchild power Good Logic 4.5V using 4uA. When Cfb is 47nF, t2 is approximately
Switch(FPS) 15ms. If Cfb is 0.1uF, t2 is approximately 120ms. The power
switch would not shutdown for most transient conditions
Figure 2-2. UVLO Block with these times. Just making Cfb large when a longer delay
time is needed can become a problem, because Cfb is an
ICC important parameter in determining the SMPS dynamic
[mA]
response time.
20 A method of increasing the time delay is shown in Fig. 2.4.
One method of increasing shutdown time is to add a resistor
between the F/B pin and GND and to shunt some of the
7 Power On
Reset Range Idelay current. When a 3.9M resistor was used
experimentally with Cfb = 47nF, the time was delayed by
150~180ms. When Vfb voltage is 7.5V, the current flowing
0.1 to the 3.9M resistor is approximately 1.9uA. To obtain the
VCC
6V 9V 15V VZ [V] same results, a zener diode (approx. 3.9 ~ 4.7V) can be series
connected to the capacitor and then these parallel connected
Figure 2-3. Start Up Waveform to Cfb, as shown in Figure 2-3, to obtain the desired
shutdown delay time according to the capacitor size
2-3. Fairchild Power Switch(FPS)
Protection Circuits 2-5. Over Voltage Protection
The Fairchild Power Switch (FPS) has several on chip
protection circuits, which do not require external The Fairchild Power Switch (FPS) has on chip protection
components. This provides extra reliability with no increase features that function even when faults, such as an open or
in cost. The protection circuits can completely stop the short circuit, occur in the feedback circuit. When the
SMPS (Latch Mode Protection) until the input power is feedback terminal shorts as viewed from the primary side,
cycled, or restart it above UVLO (Auto-Restart Mode the feedback terminal voltage becomes zero, and switching
Protection) if the control voltage unlatches below UVLO. cannot not start. If it opens, the protection circuit acts as an
The user can either use the IC or control circuit constants to overload protection circuit. When there is an fault or a
select between these two protection modes. possibility of an open circuit due to improper soldering in the
secondary side feedback circuit, the primary side continues
2-4. Over Load Protection (OLP) to switch using the maximum set current until the protection
circuit starts to operate. In such instances, if a protection
An overload described here is different from a load short
circuit is not in place it is common for the secondary side
circuit. It describes a condition where a load becomes greater

©2001 Fairchild Semiconductor Corporation

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AN4103 APPLICATION NOTE

voltage to rise far above the rated voltage, which may lead to for a short time. Tens of amperes can flow for the minimum
a fuse blowing or, more seriously, a fire. Even if this were turn on time (600ns), which can destroy the power switch.
not the case, there is a good possibility that the ICs The OCP senses this instantaneous current and latches like
immediately connected to the secondary output without a the existing protection circuit.
regulator could be destroyed (especially digital ICs, TTL IC When the MOSFET gate is switched on, the OCP block
etc.) The over voltage protection circuit in the power switch senses Ipeak for 1us through the sense resistor. The OCP
operates in such a case, providing protection against latches if the comparator's high signal lasts for more than
feedback faults. The power switch Vcc voltage is 200nS during the 1uS sample time. Figure 2-5 shows the
proportional to the output over voltage. The IC triggers the waveform when the OCP latches. When a diode or load
protection circuit if VCC exceeds 24V. Therefore, VCC must shorts, the power switch remains on only for the minimum
be maintained appropriately less than 24V during normal turn on time, at which time the OCP block opens a 1us
operation. window if the instantaneous current has the waveform shown
in Figure 2-5. Then it compares the voltage proportional to
2-6. Over Current Protection (OCP) the current across the sense resistor with the reference
The Fairchild Power Switch (FPS) has various internal basic
voltage and then latches. The 100ns delay after the 200ns is
protection functions, such as the UVLO (Under Voltage
the MOSFET turn off delay time generated from comparing
Lock Out), OLP (Over Load Protection), and OCP (Over
the voltage across the sense resistor
Current Protection). However, additional external
components are often required in SMPS applications when
excess strain is placed on the device under such fault
conditions as a secondary diode or load short or excess input
voltage. By satisfying such requirements within the Fairchild
Power Switch (FPS), reliability and cost advantage are
obtained.
Although the existing concept of Ipeak control does not go
beyond limiting the current during normal operation, the
OCP prevents power switch destruction due to circuit faults,
such as a diode short or load short. When there is a diode
short or load short, large currents flow through the MOSFET

Fairchild Power Switch(FPS)

4µA 0.9mA
VO Vfb
#4
Idelay D1 D2
Cfb
Vfb*
VZ = 3.9V

KA431(LM431) 7.5V -

V
7.5V

3.9V
3V

0
t

t1 t2 t3
Time Constant 4µA = Cfb * 0.9/t2
= 3.5R * Cfb Shutdown
4µA = Cd * 3.6/t3

Figure 2-4. Fairchild Power Switch(FPS) Long Delayed Shutdown

©2001 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4103

threshold value, at which time it starts to charge again. The

oscillator output waveform VCK goes low when Ct charges
Figure of OCP Operation and high when it discharges. This output signal is sent to the
set terminal of the S/R latch. The inverse slope of the
oscillator voltage becomes the Vsync threshold value. High
threshold value is 7.0V and the low threshold value is 6.0V.
If there is no synchronization signal, the oscillator oscillates
at the basic frequency (20KHz), but, if there is a signal,
200ns 100nsdelay
which crosses the high threshold, and the set signal becomes
high. Ultimately, the set signal that determines the switching
frequency is synchronized to the frequency of the external
synchronization signal. Because the initial synchronization
Minimum Turn-on Time pulse, at this time, increases from a low voltage to high
voltage, the frequency is synchronized at the point when the
secondary current has sufficiently reduced with the
application of slope to the Vsync threshold voltage. So at
initial synchronization, this reduces the secondary voltage
S Q Latch Rsense
stress. If there is no sync signal, Ct oscillates at the basic
R
OCP timing
frequency(20KHz), but, if there is a signal, VO charges to the
+
high threshold voltage, in the manner shown in the figure,
R - according to the external sync signal, and the set signal goes
C
OCP high. Finally, the set signal that determines the switching
level
frequency becomes synchronized to the frequency of the
external sync signal.
The high duration of the set signal was restricted to within
5% of the entire cycle for the following reason. If the set
signal goes low, the gate turns on, at which time, the switch
turns on, and switching noise appears on the screen. In the
Figure 2-5. Over Current Protection (OCP)
power switch, the set signal becomes high as sync occurs
simultaneously with the horizontal scanning flyback time.
Because high duration is 5% of the entire cycle, the switch
3. External Frequency turns on as the set signal drops to low and simultaneously
Synchronization Method horizontal scanning on the screen begins.
Consequently, the switch turn on noise does not appear on
As mentioned, the Fairchild Power Switch (FPS) in a
the screen. The level of the sync signal as it enters the power
monitor SMPS operates within a wide frequency range when
switch must cross the Vsync threshold. Because the level is
synchronized to the horizontal deflection frequency.
clamped by the 9V voltage source at the sync comparator
Although it can operate with a fixed frequency,
terminal in the power switch, it should not exceed 9V for the
synchronization is the easiest route to obtaining best screen
purpose of safe frequency synchronization. Furthermore, the
resolution, and, therefore, this method is frequently used
sync signal is added to 5Vdc which enters pin 5 of the power
today. This section describes the frequency synchronization
switch as dictated by the soft start capacitor charge at turn
method, using the horizontal deflection frequency delivered
on. Therefore, the voltage level should be between 7.5V and
to pin 5 of the power switch. The sync function differentiates
8.5V (pure sync signal voltage level is 2.5 ~ 3.5V) for safe
the SMPS for the monitor from the conventional SMPS. The
frequency synchronization.
flyback signal during horizontal scanning of the monitor
screen is generally used as the external sync frequency. It
precisely synchronizes the switching and the horizontal
scanning in order to push the screen noise due to switching
to the far left of the monitor screen so that the noise does not
appear on the screen.
As the external sync signal passes through RS , diode Dsync
prevents its voltage from falling below -0.6V. After soft start,
Cs voltage remains at 5V until the external sync signal
appears, at which point its voltage is 5Vdc plus VRS .The
sync comparator generates the comparator output waveform
(Vcomp) as shown in Figures 3-1 and 3-2 by comparing VCS
with 6.0V to 7.0V. Once the timing capacitor Ct in the IC is
charged to the high threshold value, it discharges through the
oscillator's internal discharge path until it reaches the low

©2001 Fairchild Semiconductor Corporation

5
AN4103 APPLICATION NOTE

switching noise will be seen on the screen but not correlated

with the scan rate and therefore random in nature. However,
Fairchild Power Switch(FPS) additional devices, such as the sync transformer or photo
1mA coupler are not required, making this method not only highly
cost competitive but also advantageous in terms of power
5V PWM comp
loss. This is because zero voltage switching is possible.
-

VCS #5 +

CS+
External VRS VCOMP
Sync +
Input OSC
RS 6.3V - +
Dsync Sync
Signal
Sync comp + H_DRV

Figure 3-1. Synchronization Circuit

Figure 3-3. Sync Transformer Frequency

VRS 0V 2V Synchronization Method

VCS 5V
0V

VCOMP

0V
VTHH 1.2KΩ Sync
H_DRV
VCT
2KΩ
0V VTHL
+
VSYNC.TH sync
Limit PC817
VCK
3.8V
0V 470Ω
+

Figure 3-2. Synchronous Operation

3-1. Transformer Frequency Synchronization Figure 3-4. Photocoupler Method

Method
This is the most frequently used method for monitor Non-Sync Method
frequency synchronization. After the horizontal deflection
frequency passes through the sync transformer, Vsync is sent
to pin 5 on the primary side. In this method, the delay time is
short, and the switching noise, which is pushed to the left of
the monitor screen, does appear on the screen. resonance
CAP
Synchronization using the same method but without a
separate sync transformer can also be used by receiving one
turn from the SMPS transformer.

3-2. Photocoupler Method +

Unlike the transformer method, this method produces a slight

delay time but almost no noise on the screen. The Zener
diode can compensate the CTR (Current Transfer Ratio) of
Figure 3-5. Quasi Resonance Method
the photo coupler. Though this method is not frequently
used, it has a few advantages at self assembly or
manufacture. 4. DPMS Design Method
Recently, there has been much interest in power
3-3. Quasi Resonance Method management. There has been concentrated effort on the
With the quasi resonance method, the Fairchild Power DPMS mode, without the use of supplementary voltage but
Switch (FPS) frequency is not determined by an external having low power consumption. This section describes
sync signal. It is determined by the load through a feedback several methods of applying DPMS using the Fairchild
system. The resolution on the screen is slightly poorer since Power Switch (FPS). The DPMS mode for the monitor is

©2001 Fairchild Semiconductor Corporation

6
APPLICATION NOTE AN4103

divided into the suspend mode, which operates the screen power to the heater and vertical IC.
within a few seconds, and the off mode, which minimizes the Voltage is only supplied to the VCC of power switch. All ICs,
power consumption. with exception of the micro controller on the secondary side
are powered off, thereby consuming less power. To
4-1.Suspend Mode configure the off mode to function as described above, it is
common to ground the regulator VC voltage, which supplies
This mode is called the power saving mode. It saves the power to the IC, using the micro controller. Doing this, cuts
monitor power when the PC is not being used for a fixed off the power to the horizontal and vertical deflection ICs
time and returns power quickly within a short time when the and to the heater.
monitor is required again. The suspend mode is used to
uniformly reduce the load (although slight differences may 4-3. Output Voltage Variation Method
exist depending on the device type and input voltage) to the
secondary side. The micro controller signal shuts down the By lowering all the output voltages in DPMS Mode, all the
voltage delivered to the secondary side horizontal and voltages supplied to load of the IC can be lowered; this is
vertical deflection ICs (usually grounds regulator VC another way of reducing the load. The ratio of the resistances
voltage). In this mode, the micro controller performs all on the secondary side feedback terminal can be varied to
control. The secondary side micro controller and the heater lower all the voltages on the secondary side at DPMS mode.
operate normally so that the screen can return within a The high VCC line voltage at normal operation is also
specific short time. All remaining loads are powered off. lowered, so a regulator must be used to keep this voltage
uniform. The Fairchild Power Switch (FPS) OVP (Over
4-2. Off Mode Voltage Protection) function must be designed not to trip
erroneously.
Unlike the suspend mode, this mode does not need to return
power within a short time. The micro controller removes the
L1
T1 +
D3
+ + R6
EC4 EC5 R4
R7
+ -

R5

OPT1

C5
IC1

1Vin 2Vout +
4VC 3GND
+ +
1. Drain Suspend signal from
2. GND micro-controller
3. VCC -
4. Feedback
5. S/S Suspend Mode

+
EC3
L4
OPT1 +
+ External
C4 D6
R2 SyncSignal + + off signal from micro-controller
EC2
EC10 EC11

C -
C
Off-Mode

Figure 4-1 Micro Controller Method for DPMS Mode

©2001 Fairchild Semiconductor Corporation

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AN4103 APPLICATION NOTE

BD L1
T1 +
D3
C6 R8 + + R6
EC4 EC5 R4 Low: Off-Mode
R7
D8
EC1 + -

R5

OPT1

C5
D2 IC1
R1
L4
R3 D1 1Vin 2Vout +
D6 4VC 3GND
+ +
EC10
1. Drain EC11 Suspend signal from
2. GND micro-controller
-
3. VCC
4. Feedback
5. S/S Suspend Mode

+
EC3
L4
OPT +
+ External
C R2 D6
SyncSignal + + off signal from micro-controller
EC2
EC10 EC11

C7 -
C8
Off-Mode

Figure 4-2. Output Voltage Variation Method

©2001 Fairchild Semiconductor Corporation

8
APPLICATION NOTE AN4103

5. Primary Side Regulation using the 5.6V Zener diode does not compensate for the reduction in
Fairchild Power Switch(FPS) Vcc . Figure 5-3 shows that by reducing R2, Vcc and
secondary side voltages are more temperature stabilized
Primary side regulation is shown in Fig.5-1. It eliminates the firstly, because the smaller resistance reduces the
need for an opto isolator and is therefore lower cost. It does temperature dependent component of the voltage, and
however compromise load regulation performance. secondly, the relative contribution of the 15V zener diode's
Although the resistor in the temperature compensation positive temperature coefficient is higher.
circuit increases with temperature, the transistor’s base
emitter voltage decreases by 2mV/°C. The voltage across the
base emitter resistor is fixed by the transistor’s Vbe. The
zener diode’s voltage drop increases with temperature.
Temperature compensation is possible if the components are
well matched. Figure 5-2 shows the Primary Side Regulation
circuit. Vbe is applied across R1. So if the temperature
increases, Vbe decreases, the current through R1 Vz R2
decreases, and consequently Vcc decreases. Therefore, Vcc
and the secondary side voltage reduce with increasing tem-
perature. The temperature change rate of the relatively small

BD L1 +
LineFilter T1 D3
FUSE C6 R8 + +
LF1 EC4 EC5
C9 C1 C2 + D8
C10 EC1 -
C3
L2
+
D4 + +
D2 R1 EC6 EC7

L3 -
R3 D1
1. Drain +
2.GND D5 + +
3. VCC EC8 EC9
4. Feedback
5. S/S L4 -
+
D6 + +
+ EC10 EC11
EC3

L5 -
+
C4 External +
EC2 ZD R2 SyncSignal D7 + +
EC12 EC13
C7 C8 -

Figure 5-1. Primary Side Regulation Using the Fairchild Power Switch(FPS)

VCC(pin3) f/b(pin4) VCC(pin3) f/b(pin4)

R2: 18K R2: 2K

CAP(VCC) + 5.6VZD CAP(VCC) + 15VZD

10K CAP(f/b) 10K CAP(f/b)

R1: 900Ω R1: 900Ω

Figure 5-2. Primary Side Regulation Figure 5-3. Primary Side Regulation
(Temperature Compensation)

©2001 Fairchild Semiconductor Corporation

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AN4103 APPLICATION NOTE

6. Flyback Converter DEMO Circuit

for the Monitor
6-1. Fairchild Power Switch(FPS) Flyback
Converter DEMO BOARD for the Monitor

BD L1
T1 +
FUSE LineFilter C6 D3 R6
LF1 R8 + +
EC4 EC5 170V
C9 C1 C2 R7
+ D8
C10 -
EC1
C3 R5
OPT 1
R4 C5
L2
IC1
+
D4 + +
D2 R1 EC6 EC7 75V

L3 -
R3 D1
1. Drain +
2.GND D5 + +
3. VCC EC8 EC9 15V
4. Feedback
5. S/S -
L4
+
D6 + +
+ EC10 EC11
EC3 11V

L5 -
+ C4 External +
EC2 R2 SyncSignal D7 + +
EC12 EC13 6.5V
C7
-

C8

6-2. KA5S0765 Transformer Spec for

Monitor (80W)

1 16 (2)49T
(8)25T ϕ = 0.3mm
φ = 0.3mm 170V
(2ply-wire) Lm = 440µH
(3 ply-wire)
15
2
14 (6)40T
Vin 75V
φ = 0.3mm
(2ply-wire) Core: EER3542
3 GND2 13 Bobbin: EER3542
(1)25T
1: (4) → (3) 25T φ = 0.3mm (3 ply-wire)
φ = 0.3mm
2: (15) → (16) 48T φ = 0.3mm (2 ply-wire)
(3 ply-wire) 12 (5)8T
3: (10) → (9) 3.5T φ = 0.45mm
15V φ = 0.3mm
4 (3ply-wire) 4: (11) → (9) 6T φ = 0.2mm
5: (12) → (9) 8T φ = 0.3mm (3 ply-wire)
11 6: (14) → (13) 40T φ = 0.3mm (2 ply-wire)
(4)6T
11V 7: (6) → (7) 9T φ = 0.3mm
φ = 0.2mm
8: (2) → (1) 25T φ = 0.3mm (3 ply-wire)
10
6 6.3V (3)3.5T
(7)9T φ = 0.45mm
φ = 0.3mm Bias Winding GND1 9
7

©2001 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4103

6-3. Part List

Part Name Value Part Name Value
LF1 BSF-1925 EC1 220µF / 400V
IC1 TL431 EC2 47µF / 50V
OPT1 HC11A817A / QT EC3 1µF / 50V
RT1 NTC EC4 22µF / 350V
R1 150K, 0.5W EC5 22µF / 350V
R2 470, 1/4W EC6 47µF / 160V
R3 15, 1/4W EC7 47µF / 160V
R4 5K, 1/4W EC8 1000µF / 35V
R5 1K, 1/4W EC9 1000µF / 35V
R6 120K, 1/4W EC10 1000µF / 25V
R7 1.8K, 1/4W EC11 1000µF / 25V
R8 68K, 3W EC12 1000µF / 16V
C1 BOX CAP, 473 EC13 1000µF / 16V
C2, C3 EMI FILTER CAP, 473 D1 1N4937
C4 473, CERAMIC D2 1N4937
C5 103, CERAMIC D3 RC4C
C6 CAP, 473 D4 RC4C
C7, C8 EMI FILTER CAP, 473 D5 321DF4
C9 TNR D6 321DF4
C10 BOX CAP, 473 D7 321DF4
BD KBL407 D8 1N4937

6-4. KA5S0965 Transformer Spec for

Monitor (120W)

1 16 (2)33T
(8)17T φ = 0.3mm
φ = 0.3mm 170V
(2-ply) Lm = 330µH
(3-ply) 15
2
14 (6)27T
Vin 75V
φ = 0.3mm
3 GND2 13 (2-ply)
(1)18T Core: EER4044
φ = 0.3mm Bobbin: EER4044
(3-ply) 12 (5)9T 1: (4) → (3) 18T φ = 0.3mm (3 ply-wire)
4 15V φ = 0.3mm 2: (15) → (16) 33T φ = 0.3mm (2 ply-wire)
(3-ply) 3: (10) → (9) 3T φ = 0.45mm
11 4: (11) → (9) 6T φ = 0.2mm
(4)6T
11V 5: (12) → (9) 9T φ = 0.3mm (3 ply-wire)
φ = 0.2mm
6: (14) → (13) 27T φ = 0.3mm (2 ply-wire)
6 10 7: (6) → (7) 7T φ = 0.3mm
(7)7T 6.3V (3)3T 8: (2) → (1) 17T φ = 0.3mm (3 ply-wire)
φ = 0.3mm Bias Winding φ = 0.45mm
GND1 9
7

©2001 Fairchild Semiconductor Corporation

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AN4103 APPLICATION NOTE

6-5. KA5S1265 Transformer Spec for

Monitor (150W)

1 18
(8) 15T 190V
φ = 0.25mm
(2) 60T
(9-ply) 17 φ = 0.45mm Lm = 230µH
2
16
Vin 85V (6) 27T
φ = 0.45mm
3 GND2 15
Core: EER4445
(1) 16T
Bobbin: EER4445
φ = 0.25mm
1: (4) → (3) 16T φ = 0.25mm (9 ply-wire)
(9-ply) 14
(5) 8T 2: (18) → (15) 60T φ = 0.45mm
25V 3: (12) → (11) φ = 0.45mm
4 φ = 0.45mm 3T
4: (13) → (11) 5T φ = 0.3mm (3 ply-wire)
13 5: (14) → (11) 8T φ = 0.45mm
15V (4) 56T
φ = 0.3mm 6: (14) → (13) 27T φ = 0.45mm
(3-ply wire) 7: (6) → (7) 6T φ = 0.3mm
12 8: (2) → (1) 15T φ = 0.3mm (9 ply-wire)
6 6.5V (3) 3T
(7) 6T φ = 0.45mm
Bias Winding
φ = 0.3mm GND1 11

6-6. Comparison Between KA2S and KA5S

Item KA2S0765 KA5S0765 Improvements
Istart (max) 550µA 170µA Uses a large start resistance due to reduction in Istart (AC LINE start
Iop 12µA 7µA resistance, approx.150KΩ) Improved in DPMS MODE
1.1V
OCP Not applicable Improved for output terminal DIODE SHORT
(Vsense)
Set fixed latch time based on the F/B cap due to deletion of internal leakage
OLP 1.8µA 4µA
path
DIODE EB DIODE BC DIODE VCC(#3), F/B(#4), S/S(#5) DIODE improvements SURGE level improvement
Conversion of existing 6.4V variable sync threshold voltage → 5.8 ~ 7.2V
Vth 6.4V 5.8 ~ 7.2V Variable sync threshold voltage Advantageous when reducing the
secondary diode surge voltage at initial sync synchronization
Designed to have 6V hysteresis with 15V Turn-on 9V Turn off Voltage.
UVLO 10 ~ 15V 9 ~ 15V
Improvement in Vref Noise Immunity
Ton 148nS 163nS On, Off Transient Time is undergoing improvement with respect to
Toff 38.1nS 46.9nS temperature.

Note: Actual installation examination results of the 5S-series and 2S-series.

©2001 Fairchild Semiconductor Corporation

12
APPLICATION NOTE AN4103

7. Example Transformer Design for a C. For this charger:

Monitor SMPS Td = 6.78ms ( V min ,peak = 85 2, Vmin = 85 2 – 20 )

When designing the transformer for a monitor SMPS several Pout 72

Win = -------------- ⋅ Td = -------- × 6.78ms = 0.61 J
parameters should be taken into account. Input and output η 0.8
voltages will determine the windings.
Consideration should be given to the switching frequency D. Assume 20Vac of ripple, from which:
range, continuous and discontinuous current modes and core 2Win
size. A typical design sequence is as follows: Cin = ------------------------------------------------------------
-
2 2
V min, peak – V min
7-1. Determine system specifications: 2 × 0.61
- = 277µF
= ----------------------------------------------------------------------------
2 2
Output Power, PO = 72W (at 170,75,15,11and 6.3V)Vac ( 2 × 85 ) – ( 2 × 85 – 20 )
input range = 85 to 265Vac (universal input), 60Hz
Efficiency η ≥80%
However, 277µF is not a standard value of capacitor. Hence,
to calculate the true Vmin, select the nearest standard value
7-2. Determine minimum dc input voltage
for Cin (220µF) and substitute it above, solving for
(Vmin), primary peak current (Ipeak) and Vmin = 95V.
primary rms current (Irms).
E. Primary current reaches its Ipeak value at Vmin and
When the SMPS operates at the same output power for all ac maximum duty (Dmax). Also in most current mode
inputs, the maximum peak drain current occurs at the SMPSs, Dmax should be kept below 50% to eliminate
minimum input voltage (Vmin). Also, Vmin will exhibit the any possibility of sub harmonic instabilities.
largest ripple voltage (∆V) at that time. The dc link capacitor 2 × Po 2 × 72
- = ----------------------------------------- ≅ 4.2A
I peak = -----------------------------------------------
Cin is charged and discharged at 120Hz (Figure 7-1). η × V min × D max 0.8 × 95 × 0.45

Primary Irms can be derived from Ipeak :

Vmin,peak
D max 0.45
- = 4.2 × ------------ = 1.62A
I rms = I peak × ---------------
∆V 3 3

Vmin 7-3. Determine primary inductance, Lp :

Td
This is the primary inductance needed to transfer the
required power from primary to secondary.
D max × V min 0.45 × 95
- = -------------------------------------------- = 508 µH
L P = -------------------------------------
F= 120
T=1/120 I peak × f s 3
4.2 × 20 × 10
Figure 7-1. If power output stays constant as the ac input It is recommended to select the minimum synchronous
varies, peak current drain will occur at Vmin. Also, the frequency as the switching frequency, fs, of the monitor
largest ripple on Vmin occurs at this point; dc link application.
capacitor Cin charges/discharges at 120Hz. 7-4. Determine core size:
A. Calculate energy discharge time, Td: The core used must be able to store the required peak energy
 arc sin ---------------------------------
Vmin in a small gap without saturation and with acceptable core
1 1  Vmin , peak losses. The following equation is commonly used to ensure
Td = ----- × --- ×  1 + -----------------------------------------------------
fs 4  π  proper core size (area product) in a saturation-limited
---
 2  case.
8 1.31
L p ⋅ I p ⋅ Irms ⋅ 10 2
AP = A e ⋅ A w = ----------------------------------------------- cm
B. Calculate dc link capacitor, Cin: 420 ⋅ K ⋅ B m
Win = input energy during discharge
Win = Pin × T d  where, Aw = magnetic window area, cm2
 Pin = input power
Ae = magnetic cross section area, cm2
1 2 2
Win = --- ⋅ Cin ⋅ ( V min, peak – V min ) K = core utilization factor, 0.2
2 Bm = maximum flux density, Teasel; therefore,
1.31
 508 × 10 – 6 × 4.2 × 1.62 × 10 4 4
AP =  ------------------------------------------------------------------------------------ = 1.51cm
 420 × 0.2 × 0.3 

©2001 Fairchild Semiconductor Corporation

13
 AN4103 APPLICATION NOTE

From the catalog data, select the smallest ferrite core 7-8. Finally, calculate total air gap length, Lg:
available with an area product, AP, that exceeds the
calculated value. The specifications of the selected core, Calculate a total gap length using the following formula:
EER3542 are AP = 2.38 cm2 –2 2
4π × 10 × N p × A 4π × 10 × 66 × 1.07
–2 2
Aw = 2.23cm2, L
e
= ------------------------------------------------------ = -------------------------------------------------------------- = 1.15 mm
g Lp 508
Ae = 1.07cm2
7-5. Determine primary turns, NP:
Author: FAIRCHILD Keuneui Hong
1 Experience: Participated in the development of
Ton ( max ) = ----- × D max
fs Fairchild Power Switch(FPS) in 1995.
1 Presently, responsible for the development and application of
= ----------------------3- × 0.45
20 × 10 IC for the monitor.
= 22.5µS E-mail: [email protected]
Tel: 82-32-680-1834
From Faraday's law, the minimum number of primary turns Fax: 82-32-680-1317
can be expressed as
V ×T –6 KA5S12656, KA2S0680B, KA2S0880B, KA2S0765,
min on ( max ) 95 × 22.5 × 10
N P ( min ) = --------------------------------------------------- = ---------------------------------------------- = 66.25 [ turns KA2S0965, KA2S09655, KA2S1265
∆B × A –6
m e 0.3 × 107 × 10

where, Ton(max) is maximum turn on time, and ∆Bm is

maximum peak to peak flux density swing

7-6. Determine secondary turns, Ns:

Using the Volt-seconds equation, the turns ratio n = Np/Ns
can be calculated at maximum duty ratio, as
V min × D max 95 × 0.45
n = ----------------------------------------------------------------- = -------------------------------------------------------- = 0.45
( V + V ) × ( 1 – D max ) ( 170 + 1 ) × ( 1 – 0.45 )
o d

where, Vo = output voltage, and Vd = diode forward voltage

drop; hence,
Np 66
- = ------------ = 146 [ turns ]
N s = -------
n 0.45

7-7. Determine bias turns, Nb, and auxiliary

turns, Na:
Secondary side calculation in volts per turn units is
V 170
Secondary Volt/turn = -------s = ---------- = 1.16 [ V ⁄ turn ]
N s 146

The bias side must have same volts-per turn value as the
secondary side and so can be calculated as
Vb 18
- = ------------ = 15.5 [ turns ]
N b = ------------
V⁄N 1.16
Auxiliary turns are calculated using the same volts per unit.

©2001 Fairchild Semiconductor Corporation

14
APPLICATION NOTE AN4103

©2001 Fairchild Semiconductor Corporation

15
AN4103 APPLICATION NOTE

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

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