Namal University Mianwali

Department of Electrical Engineering

COURSE OUTLINE – Fall 2023

1. COURSE DETAILS
Title: Computer Architecture Lab
Code: EE-459L
Credit(s): 4 Credit Hours (3 Hrs Theory and 1 Hrs Lab/Project Work)
Pre-requisite(s): Digital Logic Design Lab EE-251L
Co-requisite(s): None

2. INSTRUCTOR DETAILS
Name: Engr. Naureen Shaukat, Engr. Maria Rehman
Lab Timings: Tuesday (9am-12pm)
Office Location: Faculty Offices, Namal University Mianwali
Office Telephone: +92-459236995
Office Hours: Students can visit during working hours.
E-mail: [email protected]

3. COURSE RELEVANT DETAILS

Course Description:
The objective of this lab is to introduce students with the basic architecture of modern
computers. The students will build various part of the CPU. Students will also use
Logisim to Simulate their design. Students will use iverilog software to design processor
in the Verilog. Students will use open source software Qflow to synthesizing digital
circuits. A verification tool will also be introduced to students.
Course Learning Outcomes (CLOs)
On successful completion of this course, the student will be able to:
Course
Learning CLO Statement Taxonomy Level
Outcome
CLO-1 Demonstrate basic assembly programming skill, digital P2
design using iverilog, and Logisim.
CLO-2 Assembles components of microprocessors using various P4
tools.
 CLO-3 Present concise yet comprehensive technical reports. A2
Program Learning Outcomes (PLO’s):
PLO-5
Modern Tool Usage: An ability to create, select and apply appropriate techniques,
resources, and modern engineering and IT tools, including prediction andmodelling, to
complex engineering activities, with an understanding of the limitations.
PLO-10
Communication: An ability to communicate effectively, orally as well as in writing, on
complex engineering activities with the engineering community and with society at large,
such as being able to comprehend and write effective reports and design documentation,
make effective presentations, and give and receive clear instructions.

MAPPING OF CLOs TO PROGRAM LEARNING OUTCOMES

CLOs/PLOs CLO:1 CLO:2 CLO:3

PLO: 05 ✓ ✓
PLO: 10 ✓

Lab Lab Title Reference Course Assessments

No in Book/ Assignment/Test/Project
Course /Lab Report/Quiz
Material
Introduction to Verilog HDL and its Implementation on
different logic Circuit
◆ Introduction - HDL
• Lab Report
Lab 1 ◆ Behavioral Level Modeling
Lab Manual • Oral Viva
◆ Gate Level Modeling
◆ Data Flow Modeling • Performance
◆ Basic Gate Implementation

Introduction to ALU and itsimplementation

• Lab Report
Lab 2 on iVerilog and Logisim
Lab Manual • Oral Viva
◆ 4-bit ALU implementation
◆ Use of case • Performance
Decision Making and Function Call inAssembly
◆ Implementation of loops • Lab Report
Lab 3 ◆ Implementation of Function call for branch and jump Lab Manual • Oral Viva
instruction Performance

Introduction to RISC V AssemblyProgramming • Lab Report

Lab 4 Lab Manual
• Oral Viva
 ◆ Introduction to RIPES simulator • Performance
◆ Check memory and register contentsin RIPES
Qflow Software • Lab Report
Lab Manual
Lab 5 • Oral Viva
User Guide
• Performance
Qflow Software for synthesis • Lab Report
Lab Manual
Lab 6 • Oral Viva
User Guide
• Performance
16-Bit ALU and its Implementation onVerilog and
Logisim • Lab Report
Lab 7 ◆ Addition through Full Adder Lab Manual • Oral Viva
◆ Function calling in Verilog through task command • Performance

Week 8 - Mid Term Exams

16-Bit Register File and its • Lab Report
implementation on Verilog Lab Manual • Oral Viva
Lab 9 ◆ Register File design for RISC-VDatapath • Performance
◆ Connection of Datapath withRegister File.
Implementation of Datapath - I
• Lab Report
◆Instruction Memory
Lab 10 Lab Manual • Oral Viva
◆ Data Memory
◆ 2x1 Multiplexer • Performance
Implementation of Datapath - II
• Lab Report
Lab 10 ◆ Immediate Generator
Lab Manual • Oral Viva
◆ 32-bit Adder
◆ Complete connections of all blocks • Performance
Designing Main Control Unit forSingle Cycle
• Lab Report
Lab 11 Datapath
Lab Manual • Oral Viva
◆ Main Control Unit
◆ ALU Control • Performance
• Lab Report
Lab 12 Functional Verification Tools Reference Book • Oral Viva
Lab Manual • Performance

Reference Book • Lab Report

Lab 13 Functional Verification of single cycle Processor
Lab Manual • Oral Viva
• Performance
• Lab Report
Lab
Design Project Lab Manual • Oral Viva
14, 15,
and 16 • Performance

5. TEACHING METHODOLOGY
Lab demonstration with discussion

6. TEACHING MATERIAL
Reference Books
1. Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition By Samir Palnitkar
2. Embedded system design: modeling, synthesis and verification / by Daniel D.
Gajski

7. ONLINE RESOURCES
Nil
 8. COURSE ASSESSMENT AND EVALUATION
The student's performance will be assessed through a number of assessment instruments.
The table below displays the appropriate distribution of grade weights and their
corresponding linkage with the stated CLOs.
Assessments Instruments Grade
No Weight
% 1 2 3
1 Continuous Lab Reports/ 55   
Assessments Oral viva /
Performance
2 Design Project 35   
3 Viva/ Lab Exam 10 

9. UNIVERSITY POLICIES
The students are required to fully understand and observe the following policies of the
university.

Eighty percent (80%) attendance is mandatory for the lectures/laboratory work

deliveredin the course.
For further details, please refer to university policies mentioned in student handbook and
undergraduate academic regulations of Namal University Mianwali.

10.VERIFICATION
(i) I verify that the content of this document are correct and up-to-date.

Engr. Naureen Shaukat

Instructor’s Name and Signature Date
(ii) I have reviewed course-outline and state that it complies with Namal Institute
policies and guidelines.

Dr. Sajjad Ur Rehman

Name and Signature of Head of Department Date