2023 International Conference on Nascent Technologies in Engineering (ICNTE 2023)

Design and Analysis of 8-bit Vedic Multiplier

Saylee Gharge, Shrutika Patel, Aditi Patil, Nidhi Mundhada, Vaishnavi Shetty
2023 5th Biennial International Conference on Nascent Technologies in Engineering (ICNTE) | 978-1-6654-6504-5/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICNTE56631.2023.10146701

Dept. of Electronics and Telecommunication Engineering

V.E.S.I.T., Mumbai University, Chembur, India
[email protected], [email protected], [email protected], [email protected],
[email protected]

Abstract—Multipliers are utilized in a wide range of DSP appli- mathematics’s calculation speed. The Yoga methods contain
cations nowadays, including vector product, filtering, convolution 16 main methods and 13 sub-methods. They can help in
operations, matrix multiplication, etc. The parameters which are measurement, arithmetic, algebra, geometry, calculus, and data
important to consider with precision are speed of operation,
chip space occupied, ease of design, power consumption, high commercial math. Shri Bharati Krishna Tirthaji presented the
noise immunity, and so on. In this paper comparison of the concept of Vedic mathematics after eight years of research
maximum combinational path latency, chip area consumption, on the Atharva Vedas. This branch of mathematics is based
and total on-chip power of an 8-bit Vedic multiplier using Urdhva on the sixteen methods. Vedic mathematics is an intriguing
Tiryagbhyam method, an 8-bit Wallace tree multiplier, and 8- subject with several helpful algorithms [4]. The application of
bit Array Multiplier written in Verilog has been done. For
proper comparison, all multipliers are made with full adders, Vedic Mathematics concepts to multiplication would result in
half adders, n-bit adders, and basic gates. Creation and the a reduction in computational time.
simulation of the stated multipliers using Xilinx ISE 14.7 on Organisation of this paper is as follows, related work is
device 6slx9tqg144-2 and implementation of the 8-bit Vedic described in section II, section III talks about the methodology
multiplier on EDGE Spartan 7 FPGA Board has been done to used for designing and implementing the mentioned multipli-
validate the same. Design of Vedic multiplier and it’s comparison
with above mentioned multipliers is presented in this paper. ers, hardware implementation is shown in section IV, section
Index Terms—Vedic multiplier, Array multiplier, Wallace tree V shows all the results and section VI concludes the work.
multiplier, Xilinx ISE, Verilog.
II. R ELATED W ORK
I. I NTRODUCTION Some authors have worked hard to improve the perfor-
As the number of digital devices grows, the method of mance of existing multipliers like Booth multiplier [1][2],
processing digital data is using a Digital Signal Processing Array multiplier and Wallace tree multiplier [2][5][12] in
(DSP) unit. Multiplication is a critical arithmetic operation terms of propagation delay, power, and area whereas some
for processing digital data. In digital signal processing, mul- studies employed the method of keeping the same multipliers
tiplication is an essential hardware component for several but changing the adders, such as the Carry Save Adder,
activities. As a result, the multiplier’s performance is critical Kogge Stone Adder, Ripple Carry Adder, Carry Select Adder
in deciding the overall performance of the system. This is due [6][7][8][10][11][13]. While some authors have adopted the
to the multiplier being the slowest and most time-consuming methodology of demonstrating how one multiplier is superior
element of any system [1]. As the time required to execute a than the others in terms of area consumption, propagation la-
multiplication operation is longer, the goal should be to reduce tency, and total power consumption [2][12]. Many researchers
delay in the critical path. To do this, designers should pay have shown that propagation delay problem can be solved by
special attention to the adders that will be used in the multiplier using Vedic multiplier and Wallace tree multiplier [2][5][6].
architecture, because the propagation delay of the data inputs The authors of the study were able to obtain a significant
is heavily influenced by the path delay of the carry signal of reduction in propagation time [2][8]. In this paper, comparison
the adders that will be utilised. As a result, the performance of propagation delay, area, and power consumption for 8-bit
and cost of digital signal processors are affected. Hence, it Vedic Multiplier, 8-bit Wallace Tree Multiplier and 8-bit Array
is essential to select the type of multipliers and adders to be Multiplier has been done.
implemented in a system [2][3].
III. D ESIGN OF IMPLEMENTED M ULTIPLIERS
Bharati Krishna Tirthaji, an Indian monk, was a catalyst
for the development of Vedic mathematics in science and A. Design of 2-bit and 4-bit Vedic Multiplier
engineering, authoring the book ”Sixteen Simple Mathematical From Fig. 1, we can understand the working of Vedic Mul-
Formulae from the Vedas” published in 1965 [4]. Vedic Mathe- tiplication using Urdhva Tiryagbhyam method. To elaborate
matics is a list of control algorithm that the author claims were the same, first, the LSB of both the 2-bit binary numbers
retrieved from the Vedas and allegedly encompassed all math- are multiplied. Here, 0 multiplied with 0 which can be also
ematical knowledge. Vedic Mathematics is a fast-calculation seen as ’AND operation’ between the zeros. The result of the
method based on Vedic methods that saves time in arithmetic first step is stored, say R1 with no carry. Now, we perform
while also providing benefits and features to increase mental the crosswise multiplication. i.e. 1 multiplied with 0 plus 0

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 2023 International Conference on Nascent Technologies in Engineering (ICNTE 2023)

multiplied with 1 which gives us some result, say R2 with

no carry. The final step is vertical multiplication of MSB bits
which is 1 multiplied by 1 to give the result say R3. Thus we
have obtained R1 = 0, R2 = 0, and R3 = 1, which verifies (10)2
* (10)2 = (100)2 i.e. 2 * 2 = 4. We can simply derive the circuit
schematic for a 2-bit multiplier using the method described
above, as shown in Fig. 2 where the LSB bit is multiplied by
the AND gate, and the result c0 is the final answer’s LSB. The
diagonal bits are multiplied with AND gates and added with
the help of a half adder for cross-sectional multiplication. The
second bit of the output is the sum bit c1, and the carry is
transferred to the next half adder, which has the other input
being the AND operation of the multiplier’s and multiplicand’s Fig. 3. 4-bit Vedic Multiplier Addition tree
MSB bits [7][10][12][13].

Fig. 1. Method for multiplying 2-bits

Fig. 4. Block Diagram of 4-bit Vedic Multiplier

Next, the cross multiplication of the first 2 bits of A and the

last 2 bits of B is carried out and the 4 bit result obtained
is block C2 highlighted using green color in the tree and the
similar is sent to the 2 × 2 Vedic multiplier and then lastly
we multiply the last 2 bits of both A & B using 2 × 2 Vedic
multiplier for which the C3 block is highlighted using the red
color. Then again, the results from both these multipliers are
sent to the adder, but this time 6 bits from C2 and another
6 bits from C3 which are inclusive of zeros padded are sent.
So, finally, both the adders give us the 6 bit and 4 bit result
Fig. 2. 2-bit Vedic Multiplier Circuit
respectively which is finally sent to the last adder from where
the 6 bit output is received, and another 2 bits come from the
From Fig. 4 using four 2 × 2 multipliers and 3 adders we place which was present initially (q[1:0]) [7][10]. Thus the
can build a 4-bit multiplier. Here we multiply 2 bits at a time block diagram explains the algorithm depicted in Fig. 3.
because we are using the 2 × 2 Vedic multiplier that has been
B. Design of 8-bit Vedic Multiplier
already designed in the previous step. We begin with the first
step of multiplying the first 2 bits of A and first 2 bits of B Similar procedure that was used for 4-bit multiplier using
which would give a result consisting of 4 bits. We consider 2-bit multiplier is used for 8-bit Vedic multiplier using 4-bit.
the result obtained as C0. Now the last 2 bits from C0 would The difference is that the input will be 8-bit and the output
be the last 2 bits of the final answer as well. Then we cross will be of 16-bit. From the Fig. 5 we can see that, four 4-bit
multiply the next 2 bits of A and the first 2 bits of B and the Vedic multiplier, 8-bit adder and two 12-bit adder is required
result obtained is called C1. The diagram shows the yellow to build an 8-bit Vedic multiplier.
color bits of C0 and blue-colored bits of C1 in the addition
tree. Now the zero padding is done for C0 represented by C. 8-bit Array Multiplier
white-colored bubbles. The result of both these multipliers is The basic multiplier is an Array multiplier. One may assert
then sent to the adder from where the 4-bit result is received. that the key characteristics in an array multiplier is same as the

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 2023 International Conference on Nascent Technologies in Engineering (ICNTE 2023)

There are three primary steps in the Wallace Multiplier.

They are as follows:
• Divide the rows of partial products obtained into 3 rows.
Using half adders and full adders, combine the partial
products and place them in the next level.
• Shift the unused rows of partial products to the next level
as well.
• Continue with Steps 1 and 2 until you have two rows of
partial products at the end of the process and finally add
them as well to get the final product.
In stage 5 of Fig. 6, the carry generated (c53 to c62) is the
carry of the Level 5 generated using full and half adders. pr16
will always remain zero.
Fig. 5. Block Diagram of 8 x 8 Vedic Multiplier [7]
IV. H ARDWARE I MPLEMENTATION
Fig. 7 shows the hardware implementation of 8-bit Vedic
method we use in real life, meaning, multiplying two numbers multiplier. The LEDs have the weights 20 to 215 from R.H.S.
on a paper (normal multiplication method). We wait/calculate to L.H.S. i.e. 1, 2, 4,8 ,16 till 215 which is 32768. The switches
for all the partial products to arrive and then start adding the are divided into two parts, the first half to take first 8-bit input
column one by one till we get the final answer just like we do and the second half to take another 8-bit input. The first image
our normal multiplication. The multiplicand is multiplied by is 1 * 1 = 1 (0000000000000001), the second image depicts
one multiplier bit to obtain each partial product [9]. Because 24 * 2 = 48 (0000000000110000) and the last image is 255
of its regular construction, the array multiplier is well-known. * 255 = 65025 (1111111000000001). If the switch is off then
Even though array multiplier is well-known, designers avoid the number is 0 otherwise 1.
it because of its high propagation delay, which is an important
feature in a system where speed is a criterion.

D. 8-bit Wallace Tree Multiplier

A Wallace multiplier is a digital circuit for multiplying two
binary numbers. It sums partial products in stages using a
set of full and half adders until only two numbers remain.
On each layer, Wallace multipliers reduce as much as feasible
[2][11][12]. In Xilinx ISE, we have implemented 8-bit Wallace
Tree Multiplier. The data was kept in an 8-bit m and 8-bit n
array, as well as a 16-bit array, mapped as p for the output.
For the entire design of the Wallace tree multiplier, we used
47 full adders and 17 half adders. To get to the final product,
there were 5 phases to go through which can be seen in the
Fig. 6.

Fig. 7. Hardware Implementation

V. R ESULTS
In this paper, an 8-bit Vedic multiplier based on the Urdhva
Tiryagbhyam method is implemented. The code is written and
compiled in the Verilog HDL. Array multiplier and Wallace
tree multiplier are compared to the designed Vedic multiplier.
Xilinx ISE 14.7 IDE is used to build, simulate, and synthesize
the design. Furthermore, the design has been tested using
EDGE Spartan FPGA Board. Parameters like Propagation
Delay, LUTs used, and Total Power have been computed to
evaluate the performance of the proposed architectures. We
have only employed half adders, full adders, and basic gates
Fig. 6. Algorithm for 8-bit Wallace Tree Multiplier to design and compare these multipliers. No improved adders

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 2023 International Conference on Nascent Technologies in Engineering (ICNTE 2023)

like Ripple Carry adder, Carry Save adder, etc have been used
in any of the designed multipliers to make the comparison
acceptable.

Fig. 10. RTL Schematics of 8-bit Vedic Multiplier

taken, first is x = 25 multiplied by y = 25 results into p =

625 whereas x = 255 multiplied by y = 255 results into p =
65025. The explanation for Fig. 12 & 13 is similar. Table 1,
2 & 3 depicts the device utilization summary of all the above
mentioned multipliers.
Fig. 8. RTL schematics of 8-bit Array Multiplier

Fig. 11. Output of 8-bit Array Multiplier

Fig. 12. Output of 8-bit Wallace Tree Multiplier

Fig. 13. Output of 8-bit Vedic Multiplier

Fig. 9. RTL schematics of 8-bit Wallace Tree Multiplier

TABLE I
Fig. 8, 9 & 10 are the RTL Schematics of the mentioned D EVICE U TILIZATION S UMMARY TABLE OF A RRAY M ULTIPLIER
Multipliers in which there are two inputs and one output. The
outputs are obtained by designing the multipliers with their Device Utilization Summary
respective algorithms as stated in above sections. Also, Fig. 11, Slice Logic Utilization Used Available Utilization
Number of Slice Registers 0 11440 0%
12 & 13 are the simulation results of Array Multiplier, Wallace
Number of Slice LUTs 84 5720 1%
Tree Multiplier and Vedic Multiplier respectively obtain by Number used as logic 84 5720 1%
ISim Simulator. In Fig. 11, x and y are 8-bit inputs and p
is the output. In between 20ns to 40ns, there are 2 readings

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 2023 International Conference on Nascent Technologies in Engineering (ICNTE 2023)

TABLE II the Vedic Multipliers can be used in cases where speed and
D EVICE U TILIZATION S UMMARY TABLE OF WALLACE T REE M ULTIPLIER power consumption are both important factors.

Device Utilization Summary

R EFERENCES
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TABLE IV
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C OMPARISON TABLE
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[10] S. N. Gadakh and A. Khade, ”Design and optimization of 16×16 Bit
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say that the computational time for getting an output when R. Borse, ”Design and implementation of 16 × 16 multiplier us-
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almost have the same amount of Slice LUTs out of a total
of 5720 Slice LUTs. A trade-off between area consumption
and total path delay has to be made when comparing Vedic
multiplier and array multiplier.
It’s important to note that, unlike adders, lower bit multi-
pliers cannot be cascaded to construct a multiplier capable of
multiplying more bits, which is a disadvantage of developing
a higher bit multiplier. The Vedic multiplier can be used
to address this problem. A Vedic multiplier of 8 bits, for
example, can be used to make a 16-bit, 32-bit, and so on.
Wallace Tree Multiplier is significantly faster than a regular
array multiplier since its height is logarithmic in word size
rather than linear. As a result, when design complexity is an
issue, designers frequently avoid Wallace trees. As a result,

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