1). What is the standard form of ARM? © Advanced RISC Machine Automatic RISC Machine Automatic RISC Motor c 2 2 None of the above How many instruction sets does ARM have? One Two aon Three 2 Four How many registers does ARM have? Four Eight Sixteen aoe Thirty-seven 4). How many opera g modes does ARM have? Four Seven Sixteen Thirty-seven 5). When the processor is executing in ARM state, then all instructions are wide © Bits 16-bits 32-bits 64-bits 6). What is the standard form of LSL? © Logical Shift Left Left Shift Logical Logical Shift Logic ao 2 aoa0 None of the above 7). How many arithmet One shift operators does ARM have? ao Two Three a9 Four8). How many types of load instructions are there? © one © Two © Three 2 Four ). How many classes of hazards are there? One © Two aoo0 Three Four The OS timer is external peripheral in ARM7/9 Cortex-M3 Both a and b None of the above 11). are the hardware stacks in ARM7/9 FIQ, IRQ svc, USR ABT, UND Allof the above |. Which one of the following architecture has fewer number instructions? RISC cisc Both a and b ago 2 a None of the above . In which one of the following architecture the instructions are simple? RISC cisc Both a and b 27998799 98 None of the above = . The RISC processors execute of instructions per second Hundred Thousands a0 Millions 2 None of the above15). Which one of the following is a CISC architecture? © aRM7 8051 Both a and b 6 } © None of the above 46). When the processor is executing in thumb state, then all instructions are wide © Bits 16-bits 32-bits 64-bits 17). Which one of the following executes all instructions in one cycle? ARM7 « © 8051 © Both a and b © None of the above 18). What is the standard form of LSR? © Logical Shift Right © Left Shift Right © Local Shift Right © None of the above 19). Which one of the following is the 8-bit controller? © aRM7 © 8051 © Both a and b © None of the above 20). The ARM instruction set architecture divided into classes of instructions © Two © Four © six © Bight 21). When the processor is executing in jazelle state, then all instructions are wide © Bits © 46-bits24). Be a9 a a.oR a29OND y.oRO 32-bits 64-bits |. What is the standard form of ASR? Automatic Shift Right ARM Shift Right Arithmetic Shift Right None of the above |. What is the standard form of AMULET? Asynchronous Microprocessor Using Low Energy Technology Automatic Microprocessor Using Low Energy Technology ARM Microprocessor Using Low Energy Technology None of the above The frequency of load/store instruction is around 20% 10% 40% 67% . The branch with link, software interrupt, and general branch instructions are the instructions Branch Data processing ARM None of the above |. The typical clock rate of ARM9E is around 100 MHZ (130nm) 335 MHZ (130nm) 266 MHZ (130nm) None of the above |. The advanced RISC machine processors supports bytes 8 it signed & unsigned 16-bit signed & unsigned 32-bit signed & unsigned All of the above |. What are the benefits of on-chip RAM? Simpler CheaperUses less power All of the above 29), What is the standard form of ASL? Automatic Shift Left ARM Shift Left Arithmetic Shift Left None of the above 30). What is the standard form of CPSR? Current Program Register a 2 © Current Program Status Register © Complex Program Register © None of the above 31). What is the standard form of CPI? © Cycles Per Instructions © Complex Cycles Per Instructions c Current Per Instructions © None of the above 32). The load and store, data processing, branch, and coprocessor are the instruction set © Branch ° , Data processing © ARM } None of the above 33). What is the standard form of TCM? © Tightly Coupled Memory Tightly Controller Memory Tightly Coupled Microprocessor None of the above 34). What is the standard form of MMU? Memory Management Unit © Map Management Unit © Management Memory Unit } None of the above 35). The directly executed byte codes, emulated byte codes, and undefined byte codes are the byte codes Java36). 2a 37). aoa 38). a0 39). a0 a 40). 42). a Jazelle ARM None of the above The ARM and thumb instruction set and java byte codes are instruction set Java Jazelle ARM None of the above Which one of the following is the coprocessor instructions? Data processing, register transfer, and data transfer instructions Load or store single register, load and store multiple register Muttiply instructions, status register transfer instructions None of the above The clock speed of ARM7TDMI is around 10-20 MHz 20-30 MHz 50-60 MHz 80-100 MHz The program status register combines registers APSR IPSR EPSR Allof the above What is the standard form of EPLD? Electrically Programmable Large Device Electrically Programmable Logic Device Electrically Point Large Device None of the above . Which one of the following is the load and store instructions? Data processing, register transfer, and data transfer instructions Load or store single register, load and store multiple register Multiply instructions, status register transfer instructions None of the above What is the standard form of AMBA? ARM Microcontroller Bus Architecture Advanced Microcontroller Bus Architecture43), 2a 44). 48). 29 49). ARM Microprocessor Bus Architecture None of the above How much power does the ARM7TDMI core consume? 10 mW/MHz 0.25 mW/MHz, 20 mWIMHz 40 mW/MHz What is the standard form of FPA? Floating Point Accelerator Floating Point ARM Floating Point Application None of the above . Which one of the following is the data processing instructions? Data processing, register transfer, and data transfer instructions Load or store single register, load and store multiple register Multiply instructions, status register transfer instructions None of the above . What is the standard form of APSR? Application Program Status Register ARM Program Status Register Advanced Program Status Register None of the above |. What is the standard form of ICACHE? Instruction Cache Interrupt Cache Information Cache None of the above What is the standard form of ASSP? Application-Specific Standard Pan Advanced Specific Standard Procedure ARM Specific Standard Procedure None of the above What is the standard form of IPSR? Internal Program Status Register Interference Program Status Register Interrupt Program Status Register50). 2a agora arAgraoa9 9 arn None of the above What is the standard form of CAM? Content ARM Memory Content Addressable Memory Content Advanced Memory None of the above |. Which one of the following architecture has more number instructions? RISC cisc Both a and b None of the above |. What is the standard form of VRAM? Video Random Access Memory Virtual Random Access Memory Video/Virtual Random Access Memory None of the above None of the above |. What is the standard form of EPSR? External Program Status Register Execution Program Status Register Emulator Program Status Register |. Which one of the following is a cache write strategy? Write-through Copy back Write through with buffered write All of the above |. What is the standard form of SPSR? Synchronous Program Status Register Asynchronous Program Status Register Saved Program Status Register None of the above cycles are the basic types of memory cycle Idle cycle Sequential & non-sequential cycle En-processor register cycle57). 59). 294 60). a2989999 a.r7g0 ago aa0 All of the above Which one of the following cycles doesn’t require a transfer? Idle cycle ‘Sequential & non-sequential cycle Internal cycle All of the above . What is the standard form of SDLC? Synchronous Digital Logic Controller ‘Synchronous Data Link Controller Saved Digital Logic Controller None of the above What is the standard form of FSM? Finite Set Machine Finite Status Machine Float Set Machine None of the above In which one of the following architecture the instructions are complex? RISC cisc Both a and b None of the above . How many types of load-store instructions are there? One Two Three Four . How many types of pipeline hazards are there? One Two Three Four |. What is the standard form of DCACHE? Data Cache Dynamic Cache Data/Dynamic cache None of the above64). What is the standard form of FPSR? c 2.99 Floating Point Set Register Finite Point Set Register Floating Point Status Register None of the above