2.

3 Applications of gates 37

The EOR is a remarkably versatile logic element that pops allows us to build an equality tester that indicates whether or
up in many places in digital electronics. The output of an not two words are identical (Fig. 2.21).
EOR is true if its inputs are different and false if they are the In Fig. 2.21 two m-bit words (Word 1 and Word 2) are fed
same. As we’ve already stated, unlike the AND, OR, NAND to a bank of m EOR gates. Bit i from Word 1 is compared with
and NOR gates the EOR gate can have only two inputs. The bit i from Word 2 in the ith EOR gate. If these two bits are the
EOR gate’s ability to detect whether its inputs are the same same, the output of this EOR gate is zero.
If the two words in Fig. 2.21 are equal, the outputs of all
EORs are zero and we need to detect this condition in order
A to declare that Word 1 and Word 2 are identical. An AND gate
C=A⊕B will give a 1 output when all its inputs are 1. However, in this
B case, we have to detect the situation in which all inputs are 0.
We can therefore connect all m outputs from the m EOR gates
Figure 2.18 Circuit symbol for an EOR gate. to an m-input NOR gate (because the output of a NOR gate
is 1 if all inputs are 0).
If you look at Fig. 2.21 you can see that the outputs from
A A the EOR gates aren’t connected to a NOR gate but to an
G1 A.B
B m-input AND gate with inverting inputs. The little bubbles at
B
the AND gate’s inputs indicate inversion and are equivalent to
G3 NOT gates. When all inputs to the AND gate are active-low,
B F=A.B + A.B
the AND gate’s output will go active-high (exactly what we
A.B
A G2 want). In mixed logic we can regard an AND gate with active-
low inputs and an active-high output as a NOR gate.
Remember that we required an equality detector (i.e. com-
Figure 2.19 An alternative circuit for an EOR gate. parator) in Fig. 2.21 (Example 2) to control a multiplexer.
We’ve just built one.

A Example 4 The next example of an important circuit con-

structed from a few gates is the prioritizer whose circuit is
given in Fig. 2.22. As this is a rather more complex circuit
F=A⊕B
than the previous three examples, we’ll explain what it does
first. A prioritizer deals with competing requests for attention
and grants service to just one of those requesting attention.
B The prioritizer is a device with n inputs and n outputs. Each
of the inputs is assigned a priority from 0 to n1 (assume
Figure 2.20 An EOR circuit constructed with NAND gates only. that the highest priority is input n1, and the lowest is 0).

Word 1
Bit m–1 Bit 1 Bit 0 Each EOR gate compares
a pair of bits

F (high if Word 1 = Word 2)

m-input AND gate

with active-low inputs
Word 2
Figure 2.21 The application of
Bit m–1 Bit 1 Bit 0 EOR gates in an equality tester.
38 Chapter 2 Gates, circuits, and combinational logic

x0
Inputs Outputs
G1 y0
x4 x3 x2 x1 x0 y4 y3 y2 y1 y0

x1 0 0 0 0 0 0 0 0 0 0
G2 y1 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 0
x2 0 0 1 0 0 0 0 1 0 0
G3 y2
0 0 1 0 1 0 0 1 0 0
0 0 1 1 0 0 0 1 0 0
x3 0 0 1 1 1 0 0 1 0 0
y3 0 1 0 0 0 0 1 0 0 0
G4
0 1 0 0 1 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0
x4 y4 0 1 0 1 1 0 1 0 0 0
0 1 1 0 0 0 1 0 0 0
Figure 2.22 Example 4—the priority circuit. 0 1 1 0 1 0 1 0 0 0
0 1 1 1 0 0 1 0 0 0
If two or more inputs are asserted simultaneously, only the 0 1 1 1 1 0 1 0 0 0
output corresponding to the input with the highest priority 1 0 0 0 0 1 0 0 0 0
is asserted. Computers use this type of circuit to deal with 1 0 0 0 1 1 0 0 0 0
simultaneous requests for service from several peripherals 1 0 0 1 0 1 0 0 0 0
(e.g. disk drives, the keyboard, the mouse, and the modem). 1 0 0 1 1 1 0 0 0 0
Consider the five-input prioritizer circuit in Fig. 2.22. The 1 0 1 0 0 1 0 0 0 0
prioritizer’s five inputs x0 to x4 are connected to the outputs
1 0 1 0 1 1 0 0 0 0
of five devices that can make a request for attention (input x4
1 0 1 1 0 1 0 0 0 0
has the highest priority). That is, device i can put a logical
1 on input xi to request attention at priority level i. If several 1 0 1 1 1 1 0 0 0 0
inputs are set to 1 at the same time, the prioritizer sets only 1 1 0 0 0 1 0 0 0 0
one of its outputs to 1, all the other outputs remain at 0. 1 1 0 0 1 1 0 0 0 0
For example, if the input is x4,x3,x2,x1,x0
00110, the output 1 1 0 1 0 1 0 0 0 0
y4,y3,y2,y1,y0
00100, because the highest level of input is x2. 1 1 0 1 1 1 0 0 0 0
Table 2.11 provides a truth table for this prioritizer. 1 1 1 0 0 1 0 0 0 0
If you examine the circuit of Fig. 2.22, you can see that out- 1 1 1 0 1 1 0 0 0 0
put y4 is equal to input x4 because there is a direct connection. 1 1 1 1 0 1 0 0 0 0
If x4 is 0, then y4 is 0; and if x4 is 1 then y4 is 1. The value of x4 1 1 1 1 1 1 0 0 0 0
is fed to the input of the AND gates G3, G2, and G1 in the
lower priority stages via an inverter. If x4 is 1, the logical level
at the inputs of the AND gates is 0, which disables them and Table 2.11 Truth table for the priority circuit of Fig. 2.22.
forces their outputs to 0. If x4 is 0, the value fed back to the
AND gates is 1 and therefore they are not disabled by x4.
Similarly, when x3 is 1, gates G3, G2 and G1 are disabled,
(c) Compare the circuit diagrams of P and Q in terms of speed
and so on.
and cost of implementation.
Example 5 Our final example looks at two different circuits
(a) The circuit diagram for P
(X  Y)(Y 䊝 Z) is given by
that do the same thing. This is a typical exam question.
Fig. 2.23 and the circuit diagram for Q
Y ·Z  X·Y·Z
(a) Using AND, OR, and NOT gates only, draw circuits to is give by Fig. 2.24.
generate P and Q from inputs X, Y, and Z, where (b) The truth table for functions P and Q is given in
P
(X  Y)(Y 䊝 Z) and Q
Y ·Z  X·Y·Z . Table 2.12 from which it can be seen that P
Q.
(b) By means of a truth table establish a relationship between (c) We can compare the two circuits in terms of speed
P and Q. and cost.
40 Chapter 2 Gates, circuits, and combinational logic

X Y Z XY Y䊝Z P
(X  Y)(Y 䊝 Z) Y·Z X ·Y·Z Q
Y·Z  X ·Y·Z

0 0 0 1 0 0 0 0 0
0 0 1 1 1 1 1 0 1
0 1 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0
1 0 1 1 1 1 1 0 1
1 1 0 1 1 1 0 1 1
1 1 1 1 0 0 0 0 0

Table 2.12 Truth table for Figs 2.23 and 2.24.

This is the push This is the LED

The pointer tool allows button input tool symbol that lets you
you to select an object that lets you create see the state of a
in the window. You can a 0 or a 1 input. point in the circuit.
click the right-hand
mouse button to alter
the object's properties This is the wiring
This is a typical gate symbol. Click on tool that lets you
or act on it in some
it and move the mouse to where you wire gates together.
way.
want the gate to be positioned. Click
again and the gate is placed there.
This is the hand
tool that allows
you to set the
state of a switch.

Figure 2.25 Digital Works—the initial screen.

2.4 Introduction to Digital Works that Digital Works simulates both simple 1-bit storage
elements called flip-flops and larger memory components
We now introduce a Windows-based logic simulator called such as ROM and RAM.
Digital Works that enables you to construct a logic circuit After installing Digital Works on your system, you can run
from simple gates (AND, OR, NOT, NAND, NOR, EOR, it to get the initial screen shown in Fig. 2.25. We have anno-
XNOR) and to analyze the circuit’s behavior. Digital Works tated six of the most important icons on the toolbars. A cir-
also supports the tri-state logic gate that enables you to con- cuit is constructed by using the mouse to place gates on the
struct systems with buses. In the next chapter we will discover screen or workspace and a wiring tool to connect the gates
 2.4 Introduction to Digital Works 41

together. The input to your circuit may come from a clock clicking at a suitable point in the workspace as Fig. 2.27
generator (a continuous series of alternating 1s and 0s), a demonstrates. If you hold the control key down when placing
sequence generator (a user-defined sequence of 1s and 0s), or a gate, you can place multiple copies of the gate in the work-
a manual input (from a switch that you can push by means of space. The OR gate is shown in broken outline because we’ve
the mouse). You can observe the output of a gate by connect- just placed it (i.e. it is currently selected). Once a gate has been
ing it to a display, LED. You can also send the output of the placed, you can select it with the mouse by clicking the left
LED to a window that displays either a waveform or a button and drag it wherever you want. You can click the right
sequence of binary digits. button to modify the gate’s attributes (e.g. the number of
Digital Works has been designed to be consistent with the inputs).
Windows philosophy and has a help function that provides You can tidy up the circuit by moving the gates within the
further information about its facilities and commands. The work area by left clicking a gate and dragging it to where you
File command in the top toolbar provides the options you want it. Figure 2.28 shows the work area after we’ve moved
would expect (e.g. load, save, save as). the gates to create a symmetrical layout. You can even drag
gates around the work area after they’ve been wired up and
reposition wires by left clicking and dragging any node
2.4.1 Creating a circuit (a node is a point on a wire that consists of multiple sections
We are going to design and test an EOR circuit that has the or links).
logic function A·B  A·B. This function can be imple- Digital Works displays a grid to help you position the gates.
mented with two inverters, two AND gates, and an OR gate. The grid can be turned on or off and the spacing of the grid
Figure 2.26 shows three of the icons we are going to use to lines changed. Objects can be made to snap to the grid. These
create this circuit. The first icon is the new circuit icon that functions are accessed via the View command in the top line.
creates a fresh circuit (which Digital Works calls a macro). Before continuing, we need to save the circuit. Figure 2.29
The second icon is the pointer tool used to select a gate (or demonstrates how we use the conventional File function in
other element) from the toolbars. The third icon is a gate that the toolbar to save a circuit. We have called this circuit
can be planted in the work area. OUP_EOR1 and Digital Works inserts the extension .dwm.
Let’s start by planting some gates on the work area. The The next step is to wire up the gates to create a circuit. First
EOR requires two AND gates, an OR gate, and two inverters. select the wiring tool from the tool bars by left clicking on it
First click on the pointer tool on the bottom row of icons. If it (Fig. 2.30). Then position the cursor over the point at which
hasn’t already been selected, it will become depressed when you wish to connect a wire and left click. The cursor changes
you select it. The pointer tool remains selected until another to wire when it’s over a point that can legally be connected to.
tool is selected. Left click to attach a wire and move the cursor to the point
You select a gate from the list on the second row of icons by you wish to connect. Left click to create a connection. Instead
first left clicking on the gate with the pointer tool and then left of making a direct connection between two points, you can

This is one of the gates

that you can select and put
in the work area.

This is the pointer tool and

This icon creates a new is the most important icon
macro. If a circuit is because you use it to
already open, you will be select objects.
invited to save it.

Figure 2.26 Beginning a session with Digital Works.

42 Chapter 2 Gates, circuits, and combinational logic

This is the icon for

a NOT gate
This was the last
(inverter). Select it
item placed. Note
with the pointer
that it remains
tool and left click in
dotted until the
the workspace at
next item is
the point you wish
selected.
to place it.

Figure 2.27 Placing gates in the work area.

The View
command is used
to set up the grid,
display it, or select
snap-to-grid. You can select a
gate by left clicking
on it and then drag
it to a suitable point
in the work area.

Figure 2.28 Tidying up the circuit.

click on the workspace to create a node (i.e. the connection is straight-line segments. If you select the pointer tool and left
series if straight lines.) click on a wire, you can drag any of its nodes (i.e. the points
You can make the wiring look neat by clicking on interme- between segments on a line). If you right click on a wire you
diate points to create a signal path made up of a series of can delete it or change its color. Once a wire has been
 2.4 Introduction to Digital Works 43

Click on the File

command to
bring down the
menu.

Figure 2.29 Saving the circuit.

STEP 1 Click on
the output of the
gate we wish to
connect.
Click on the
wiring tool to
connect gates
together.
STEP 2 Click
on the input we
wish to
connect the
output to.

Figure 2.30 Wiring gates together.

connected to another wire (or an input or output), the con- inputs and output we need points we can connect the wire to.
nection point can’t be moved. To move a connection you have In this case we are going to use the interactive input device
to delete the wire and connect a new one. to provide an input signal from a push button and the LED to
Digital Works permits a wire to be connected only between show the state of the output.
two legal connections. In Fig. 2.30 the inputs to the two In Fig. 2.31 we’ve added two interactive inputs and an LED
inverters and the circuit’s outputs aren’t connected anywhere. to the circuit. When we run the simulator, we can set the
This is because each wire must be connected between two states of the inputs to provide a 0 or a 1 and we can observe
points—it can’t just be left hanging. In order to wire up the the state of the output on the LED.
44 Chapter 2 Gates, circuits, and combinational logic

The interactive
tool allows you
to generate
digital inputs.

The hand The LED is selected

tool is used like any other device
to operate and placed on the
the input. workspace.

Figure 2.31 Adding inputs and outputs to the circuit.

The text tool is

used to add labels
and comments to
the work area.

Figure 2.32 Completing the circuit.

We can now wire up the inputs and the output and com- window. This brings down a text box. Enter the text and click
plete the rest of the wiring as shown in Fig. 2.32. At this stage ok to place it on the screen.
we could run the circuit if we wanted. However, we will use We also wish to label the circuit’s inputs and outputs.
the text tool (indicated by the letter A on the middle toolbar) Although you can use the text tool to add text at any point,
to give the circuit a title. Click on the A and then click on the input and output devices (e.g. clocks, switches, LEDs) can be
place at which you wish to add the text to open the text given names. We will use this latter technique because the
 2.4 Introduction to Digital Works 45

Right click on the LED

to bring down the
menu and click on Text
to select the text box.

Figure 2.33 Labeling the circuit and inputs and outputs.

names attached to input and output devices are automatically values 0,0, 0,1, 1,0, and 1,1 to verify that the circuit is an EOR
used to label the timing diagrams we will introduce later. (the output LED should display the sequence 0, 1, 1, 0).
Figure 2.33 shows the circuit with annotation. The label Just observing the outputs of the LEDs is not always
EOR circuit has been added by the text tool, and inputs A and enough to get a picture of the circuit’s behavior. We need a
B have been labeled by right clicking on the input devices. In record of the states of the inputs and outputs. Digital Works
Fig. 2.33 we have right clicked on the LED to bring down provides a Logic History function that records and displays
a menu and then selected Text to invoke the text box (not inputs and outputs during a simulator run. Any input or out-
shown). You enter the name of the output (in this case Sum) put device can be added to Logic History. If you select input
into the text box and click ok. This label is then appended to A with the pointer tool and then right click, you get a pull
the LED on the screen. You can change the location of the down menu from which you can activate the Add to Logic
label by right clicking on its name, selecting Text Style from History function to record the value of input A. When this
the menu, and then selecting the required position (Left, function is selected (denoted by a tick on the menu), all input
Right, Top, Bottom). is copied to a buffer (i.e. store). As we have two inputs, A and
B, we will have to assign them to the Logic History function
independently.
2.4.2 Running a simulation To record the output of the LED, you carry out the same
We are now ready to begin simulation. The bottom row of procedure you did with the two inputs A and B (i.e. right
icons is concerned with running the simulation. The leftmost click on the LED and select Add to Logic History) (see
icon (ringed in Fig. 2.34) is left clicked to begin the simulation. Fig. 2.35).
The next step is to change the state of the interactive input In order to use the Logic History function, you have to
devices. If you click on the hand tool icon, the cursor changes activate it from the Tools function on the toolbar. Selecting
to a hand when positioned anywhere over the work area. Tools pulls down a menu and you have to select the Logic
By putting the hand cursor over one of the input devices, History window. Figure 2.36 shows the logic history window
you can left click the mouse to change the status of the input after a simulation run. Note that the inputs and outputs have
(i.e. input 0 or input 1). When the input device is supplying the labels you gave them (i.e. A, B, and Sum).
a 1, it becomes red. Figure 2.34 shows the situation input We now need to say something about the way the simulator
A
1, B
0, and the Sum
1 (the output LED becomes operates. The simulator uses an internal clock and a record of
red when it is connected to a 1 state). You can change the the state of inputs and outputs is taken at each clock pulse.
states of the input devices to generate all the possible input Figure 2.37 shows how you can change the clock speed from
46 Chapter 2 Gates, circuits, and combinational logic

The hand tool is used to

operate the input switches.
First click on the hand tool to
select it. Then move the
hand cursor to the switch
(interactive input device) you
The run wish to operate. Each click
tool is used changes the input state. A
to begin a logical one state is shown by
simulation. the switch becoming red.
The LED connected to the
output becomes red when
the output is a 1.

Figure 2.34 Running the simulator.

Use the pointer tool to

select and right click
on the output LED.
This brings down the
attributes menu. Click
on Add to Logic
History to record the
output values
generated during a
simulation.

Figure 2.35 Recording inputs and output.

the toolbar by pulling down the Circuit menu and selecting the signals are read and recorded at each clock pulse, the entire
Clock Speed. simulation is over in a second or so. Blink and you miss it.
We’re not interested in clocks at this stage because we are We need to stop the clock to perform a manual simulation.
looking at a circuit that doesn’t have a clock. However, because The Logic History window contains a copy of the run, stop,
98 Chapter 2 Gates, circuits, and combinational logic

A 0
1 0
D
1 1
Node to tested
1
B G
E 3 5 H
0 1 0
F 0

1
F 0
C 1
In order to establish a sensitive path for internal node D
to external node H, it is necessary to set inputs G and F to
Contradiction OR gate 5 low. G is set low by setting inputs B and
E to NAND gate 3 high. Input E is derived from NOT gate
2 and is set high by setting input A low. Similarly, output F
of NAND gate 4 is set low by setting inputs A and C to
gate 4 high. Unfortunately, in order to set G and F low
requires that input A be both 0 and 1 simultaneously. Figure 2.109 Circuit with an
This condition is a contradiction and therefore node D undetectable fault.

fault is due to redundancy in the circuit and can be eliminated AB CD

by redesigning the circuit. Alternatively, a circuit can be made
P
easier to test by connecting some of its internal nodes to pins Q
so that they can be directly examined.

■ SUMMARY
In this chapter we have looked at the basic set of logic elements S
R U
used to create any digital system—the AND, OR, and NOT
gates. We have demonstrated how simple functions can be
generated from gates by first converting a problem in words into
a truth table and then using either graphical or algebraic
methods to convert the truth table into a logical expression and T
finally into a circuit made up of gates. At the end of this chapter
we briefly mentioned the new families of programmable logic
elements and their design tools that have revolutionized the Figure 2.110 Circuit for Question 2.2.
creation of today’s complex digital systems.
We have introduced Digital Works, a design tool that enables
you to create digital circuits and to observe their behavior. We
also introduced the tri-state buffer, a device that enables you to (c) Minterm
connect logic subsystems to each other via a common data (d) Truth table
highway called a bus. (e) Literal
In the next chapter we look at sequential circuits built from (f) Constant
flip-flops. As the term sequential suggests, these circuits involve (g) Variable
the time factor, because the logical state of a sequential device is
2.2 Tabulate the values of the variables P, Q, R, S, T, and U in the
determined by its current inputs and its past history (or
circuit of Fig. 2.110 for all possible input variables A, B, C, and D.
behavior). Sequential circuits form the basis of counters and data
The truth table for this question should be expressed in the form
storage devices. Once we have covered sequential circuits, we
of Table 2.29.
will have covered all the basic building blocks necessary to design
a digital system of any complexity (e.g. the digital computer). 2.3 For the circuit of Fig. 2.110 in Question 2.2 obtain a
Boolean expression for the output U, in terms of the inputs A, B,
C, and D. You should obtain an expression for the output U by
■ PROBLEMS considering the logic function of each gate.
2.1 Explain the meaning of the following terms. 2.4 For the truth table in Question 2.2 (Table 2.29) obtain a
(a) Sum-of-products sum-of-minterms expression for U and use Boolean algebra to
(b) Product of sums obtain a simplified sum-of-products expression for U.
 2.8 Programmable Logic 99

Inputs Output
– –
A B C D P
B C Q
P⋅A R
CD S
B⋅R T
B⋅D U
QST

0 0 0 0 1 0 1 0 0 0
0 0 0 1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
0 0 1 0 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
0 0 1 1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
0 1 0 0 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
0 1 0 1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅ ⋅ ⋅ ⋅
⋅ ⋅ ⋅ ⋅
1 1 1 1 1 1 1 1 1 1

Table 2.29 Truth table for Question 2.2.

2.7 Plot the following functions on a Karnaugh map.

X
(a) F
A⋅B⋅C  A⋅B⋅C
A
(b) F
A⋅B ⋅C  A⋅B⋅C  A⋅B⋅C
B (c) F
A  A⋅B  A⋅C  A⋅B⋅C
C
(d) F
A  B⋅A⋅C  D
(e) F
A⋅B⋅C⋅D  A⋅B⋅C⋅D  B⋅D
Y
2.8 How would you plot the following expressions on a
Karnaugh map?
(a) (A  B  C) (D  B) (A  C)
(b) (A ⋅ B  A ⋅ B  A ⋅ C) (A ⋅ D  A ⋅ B  A ⋅ C)
2.9 Simplify the following expressions by means of Boolean
Figure 2.111 Circuit for Question 2.5. algebra. That is, do not use Karnaugh maps.
(a) A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C
(b) A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C
2.5 Use a truth table to obtain the relationship between A ⋅ B ⋅ C
outputs X and Y and the input variables A, B, and C for the circuit (c) A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C
in Fig. 2.111. From the truth table write down Boolean  A⋅B⋅C  A⋅B⋅C  A⋅B⋅C
expressions for X and Y. Derive expressions for X and Y by
2.10 Simplify the following expressions.
considering the Boolean equations of the gates.
Demonstrate that the two results (i.e. those derived from the (a) (A  B  C)(A  B  C)
truth table and those derived from the Boolean equations) are (b) (A ⋅ B  A ⋅ B  A ⋅ C) (A ⋅ B  A ⋅ B  A ⋅ C)
equivalent by substituting literals (000, 001, etc.) for A, B, and C
in the Boolean equations. (c) A  B  (A  C ⋅ D) (A  B ⋅ C)
(d) A ⋅ B  B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C ⋅ D
2.6 Draw logic diagrams, using AND, OR, and NOT gates only, to
implement the following Boolean expressions. In each case draw (e) (A  B)(A  B  C) (A  B  C) (A  B  C)
the diagrams directly from the equations and do not attempt to 2.11 Use de Morgan’s theorem to complement the following
simplify the expressions. expressions. Do not simplify the expressions either before or
(a) F
A·B  A·B after you complement them.
(b) F
(A  B  C)(A ⋅ B  A ⋅ C) (a) B ⋅ C  B ⋅ C
(b) B ⋅ C ⋅ D  B ⋅ C
(c) F
(A  C)(A  B ⋅ D) (c) B (C  D) B ⋅ C
(d) A ⋅ B(C ⋅ D  C ⋅ D)
(d) F
A  C·A  B·D
(e) A ⋅ B(A ⋅ D  C ⋅ D)
(e) F
(A·B  A·B  A·C)(A·B  A·B  A·C) (f) B ⋅ C  B ⋅ C (A ⋅ D  A ⋅ D)
100 Chapter 2 Gates, circuits, and combinational logic

2.12 Convert the following expressions to sum-of-products form. output is given by the input plus 1; for example, if C, B, A
0, 1,
(a) (A  B) (B  C) (A  C) 1, the output R, Q, P is 1, 0, 0. Note that 111  1
000 (i.e.
there is no carry out). Design a circuit to implement this system.
(b) (C  D) (A ⋅ B  A ⋅ C) (A ⋅ C  B)
(c) (A  B  C) (A  C ⋅ D) (D  F) 2.20 A 4-bit binary number is applied to a circuit on four lines
D, C, B, and A. The circuit has a single output, F, which is true if
2.13 Simplify the number is in the range 3 to 12, inclusive. Draw a truth table
(a) A 䊝 B 䊝 C for this problem and obtain a simplified expression for F in
(b) A·B(C䊝A) terms of the inputs. Implement the circuit
(a) in terms of NAND gates only
2.14 Convert the following expressions to product-of-sums form. (b) in terms of NOR gates only
(a) A ⋅ B  A ⋅ B  B ⋅ C
2.21 A circuit has four inputs D, C, B, and A encoded in 8421
(b) A ⋅ B  B ⋅ C  B ⋅ C ⋅ D natural binary form. The inputs in the range 00002
0 to
(c) A ⋅ B  A ⋅ C  B ⋅ C 10112
11 represent the months of the year from January (0)
(d) A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C  A ⋅ B ⋅ C to December (11). Inputs in the range 1100 to 1111 (i.e. 12 to
15) cannot occur. The output of the circuit is a logical one if the
2.15 A circuit has four inputs, P, Q, R, and S, representing the month represented by the input has 31 days. Otherwise the
natural binary numbers 0000
0, to 1111
15. P is the output is false. The output for inputs in the range 1100 to 1111
most-significant bit. The circuit has one output, X, which is true is undefined.
if the number represented by the input is divisible by three
(a) Draw a truth table to represent the problem and use it to
(regard zero as being indivisible by three.) Design a truth table
construct a Karnaugh map.
for this circuit and hence obtain an expression for X in terms
(b) Use the Karnaugh map to obtain a simplified
of P, Q, R, and S. Give the circuit diagram of an arrangement of
expression for the function.
AND, OR, and NOT gates to implement this circuit. Design a
(c) Construct a circuit to implement the function using AND,
second circuit to implement this function using NAND
OR, and NOT gates.
gates only.
(d) Construct a circuit to implement the function using NAND
2.16 A device accepts natural binary numbers in the range gates only.
0000 to 1111 which represent 0 to 15. The output of the circuit 2.22 A multiplexer has eight inputs Y0 to Y7 and a single output
is true if the input to the circuit represents a prime number and Z. A further three inputs A, B, and C (A
least-significant bit)
is false otherwise. Design a circuit using AND, OR, and NOT determine which output the single input X is connected to. For
gates to carry out this function. A prime number is an integer example, if A, B, C
110, the output Y6
X and all other
that is greater than 1 and is divisible only by itself and 1. Zero outputs are low. Design a circuit to implement this function.
and 1 are not prime numbers.
2.23 What is tri-state logic and why is it used in digital
2.17 Demonstrate how you would use a 4-line to 16-line systems?
demultiplexer to implement the system in Question 2.16.
2.24 Use Digital Works to construct a circuit that realizes the
2.18 A logic circuit accepts a natural binary number DCBA in expression
the range 0 to 15 (the least-significant bit is bit A). The output is
A⋅B⋅C  A⋅B⋅C  A⋅B⋅C  A⋅B⋅C
the square of the input; for example, if DCBA
01012
510, the
output is 000101012
2510. Design a circuit to implement this Simplify the above expression and use Digital Works to
function. construct a new circuit. Demonstrate that the two circuits are
equivalent (by comparing their outputs for all inputs).
2.19 A logic circuit has three inputs C, B, and A, where A is the
least-significant bit. The circuit has three outputs R, Q, and P. For 2.25 Use Digital Works to construct the system of
any binary code applied to the input terminals (A, B, and C) the Question 2.20 and demonstrate that your system works.
140 Chapter 3 Sequential logic

combinational logic we introduced in the previous chapter to 3.2 Explain why it is necessary to employ clocked flip-flops in
create a digital computer. sequential circuits (as opposed to unclocked flip-flops)?
Sequential machines fall into two categories. Asynchronous 3.3 What are the three basic flip-flop clocking modes and why
sequential machines don’t have a master clock and the output is it necessary to provide so many clocking modes?
from one flip-flop triggers the flip-flop it’s connected to. In a
synchronous sequential machine all the flip-flops are triggered 3.4 The behavior of an RS flip-flop is not clearly defined when
at the same time by means of a common master clock. R
1 and S
1. Design an RS flip-flop that does not suffer from
Synchronous machines are more reliable. In this chapter we this restriction. (Note:What assumptions do you have to
have briefly demonstrated how you can construct a make?)
synchronous counter and a machine that can detect a specific 3.5 For the waveforms in Fig. 3.62 draw the Q and Q outputs
binary pattern in a stream of serial data. of an RS flip-flop constructed from two NOR gates (as in
Fig. 3.2).
■ PROBLEMS 3.6 For the input and clock signals of Fig. 3.63, provide a
timing diagram for the Q output of a D flip-flop. Assume that
3.1 What is a sequential circuit and in what way does it differ the flip-flop is
from a combinational circuit?
(a) Level sensitive
(b) positive edge triggered
(c) negative-edge triggered
(d) a master–slave flip-flop
R input 3.7 What additional logic is required to
convert a JK flip-flop into a D flip-flop?
3.8 Assuming that the initial state of the
S input circuit of Fig. 3.64 is given by C
1, D
1,
P
1, and Q
0, complete the table. This
question should be attempted by calculating
the effect of the new C and D on the inputs to
Q output both cross-coupled pairs of NOR gates and
therefore on the outputs P and Q. As P and Q
are also inputs to the NOR gates, the change
in P and Q should be taken into account when
Q output calculating the effect of the next inputs C and
D. Remember that the output of a NOR is 1 if
Figure 3.62 R and S inputs to an RS flip-flop. both its inputs are 0, and is 0 otherwise.

D input to
flip-flop

Clock input

Figure 3.63 Timing diagram of a clock and data signal.

D P

Figure 3.64 Circuit for Question 3.8. Figure 3.65 Circuit for Question 3.9.
 3.7 Introduction to state machines 141

3.11 A T flip-flop has a single clock input and outputs Q and Q.

C D P Q
Its Q output toggles (changes state) each time it is clocked. The
T flip-flop behaves exactly like a JK flip-flop with its J and K
1 1 1 0
inputs connected permanently to a logical one. Design a T flip-
1 0 flop using a D flip-flop.
0 0
3.12 Why haven’t D and RS flip-flops been replaced by the JK
1 1 flip-flop, because the JK flip-flop can, apparently, do everything a
0 1 D flip-flop or an RS flip-flop can do?
1 1 3.13 What is a shift register and why is it so important in digital
0 1 systems?
0 0 3.14 Design a shift register that has two inputs, a clock input
1 0 and a shift input. Whenever this register receives a pulse at its
shift input, it shifts its contents two places right.
Modify the circuit to provide a new input S which, when 1, will 3.15 Analyze the operation of the circuit of Fig. 3.66 by
at any time set P to 1 and Q to 0. Provide another input R that constructing a timing diagram (assume that Q0 and Q1 are
will similarly set P to 0 and Q to 1. Note that R and S cannot initially 0). Construct the circuit using Digital Works and observe
both be a 1 at the same time and therefore the condition its behavior.
R
S
1 need not be considered.
3.16 Analyze the operation of the circuit of Fig. 3.67 by
3.9 Demonstrate that the flip-flops in Fig. 3.65 are equivalent. constructing a timing diagram (assume any initial value for Q0 to
Are they exactly equivalent? Q3). Construct the circuit using Digital Works and observe its
3.10 Many flip-flops have unconditional preset and clear inputs. behavior.This type of circuit is an important circuit in digital
What do these inputs do and why are they needed in sequential systems because it can be used to generate a pseudo random
circuits? sequence; that is, the sequence of bits at its Q0 output look (to an

Output
Input J0 Q0 J1 Q1

C C

K0 Q0 K1 Q1

Figure 3.66 Circuit diagram for

Clock Question 3.15.

J Q3 J Q2 J Q1 J Q0
C C C C
K Q K Q K Q K Q

Figure 3.67 Circuit diagram for

Shift clock Question 3.16.

1
J1 Q1 J2 Q2 J3 Q3

C C C
1
K1 K2 Q2 K3 Q3
Figure 3.68 Circuit diagram for
Clock Question 3.17.