UNIVERSITY OF BAHRAIN

Department of Electrical and Electronics Engineering

EENG352: Digital System II

Experiment No. 3
Lab Title Sequential Circuit Design using SPLDs

Student Name(s) Student ID(s)

Hamza Mohammed 202103178
Aya Abdulla 202012262

Lecturer:
Due Date: 30th November 2023
Date of Submission: 30th November 2023

By submitting this lab report for marking I confirm the following:

o This assignment is my own work o Any information used has been properly
referenced o I understand that a copy of my work may be used for ABET
documentations.

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 Comments:

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 EENG352
Sequential Circuit Design using SPLDs

Objective

The purpose of this laboratory is to introduce the students to the different CAD
tools required to implement a logic circuit using simple programmable logic
devices such as the GAL 22v10.

Learning Outcome:

This lab assignment satisfies the Course Intended Learning Outcome # b, which is, an
ability to design and conduct experiments, as well as to analyze and interpret data.
PILO.1 Be able to use counter ICs to design various sequential circuits

Apparatus
1. C. H. Roth, Digital System Design Using VHDL, PWS Publishers
2. Logic Aid or WinCupl to get the jed file
3. GAL22V10 Data Sheet
4. Using Proteus Simulation Software. #Online & #On campus
5. Using the Dataman Universal Programmer & Tests manual. #On campus only
Method
This lab has been designed to --------------------------- --.
This document is to be submitted to the tutor by hardcopy next lab period and also by email in the due time
announced.

Marking Scheme
Marks
Assigned
Assignment I
Assignment II
Assignment III
Assignment IV
Assignment V
Conclusions + Discussion
Total 100

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Theory And Background

Introduction

All PLDs contain arrays. Two important kinds of SPLD are PALs (Programmable
Array Logic) and GALs (Generic Array Logic). A typical array consists of a matrix
of conductors connected in rows and columns to AND gates.

The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed.
For this reason, they are useful for new product developme nt (prototyping) and
for training purposes (educational).

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 PALs and GALs are often represented by simplified diagrams in which a single
line represents multiple gate inputs. The logic shown is for the XOR gate, given
previously.

The AND-gate arrays in PALs and GALs connected to macrocells. A macrocellis

an OR gate together with associated output logic. Two types of PAL/GAL
macrocellsare shown. For these particular macrocells, the I/O pin can serve as
an input or an output

The GAL22V10 is a series of programmable -logic devices from Lattice Semiconductor,

implemented as CMOS-based generic array logic ICs, and available in dual inline packages
or plastic leaded chip carriers. It is an example of a standard production GAL devic e that is
often used in educational settings as a basic PLD.

The GAL22V10 has 12 input pins, and 10 pins that can be configured as either inputs or
outputs, and exists in various switching speeds, from 25 to 4 ns. Each output is driven by an
output-logic macrocell, with an output -enable product term, and a variable number of
product terms, ranging from eight to sixteen. Each OLMC may be set to output as inverting
or non-inverting, and be placed into either registered or combinatorial mode. In registered
mode, each macrocell actively uses a D-flip-flop to hold a state under the control of the data
input from the logic portion of the macrocell and the rising edge of the clock signal, while in
combinatorial mode the flip -flop is removed from the macrocell and the outputs are driven
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 directly by the logic. In the latter mode, the pin may also dynamically switch between input
and output based on the product term. In either model, the pin value is fed back into the array
as a product term. Combinations are set using an E2PROM. The output registers can be
preloaded into a potentially invalid state for testing by a GAL22V10 programmer. Inputs and
outputs include active pull-ups and are transistor-transistor logic compatible due to high-
impedance buffers. A user electronic signature section is included for details such as user ID
codes, revision IDs, or asset tagging on official Lattice Semiconductor units, as well as a
static ES section for compatibility with non-Lattice Semiconductor GAL22V10 units. In
addition, a security cell is included which, when set, disallows the retrieval of the array logic
from the chip, until a new set of logic is set.

Latch-up protection is implemented using n-pullups and a charge pump in the official Lattice
Semiconductor models.

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 Design Problem:
A Mealy sequential circuit accepts 2-bit input X and generates 3-bit output Z. The output Z
represents a binary number whose value equals the accumulated total number of 1’s received
at the inputs. The circuit resets every three clock pulses. Implement the circuit using GAL 22V10.
Example:
X1 1 1 1 0 0 0 1 1 0 1 1 1
X0 1 0 1 1 0 1 0 1 0 1 1 1

N= No. of 1’s 2 3 5 1 1 2 1 3 3 2 4 6

Z2 0 0 1 0 0 0 0 0 0 0 1 1
Z1 1 1 0 0 0 1 0 1 1 1 0 1
Z0 0 1 1 1 1 0 1 1 1 0 0 0

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 Experiment Procedure:
1. Construct the state table of the counter using LogicAid.
2. Use LogicAid to derive the flip flops and outputs equation for the circuit.
3. Generate a JEDEC file for the GAL22V10 from the derived equations.
4. Save the output file with a *.jed extension
5. For the simulation use the Proteus software to connect and simulate the circuit. Use
AM22v10 and upload the *.jed file.
6. For the Hardware Insert the GAL22v10 PLD into the universal programmer.
7. Start the universal programmer program.
8. Use the Universal program to program the GAL22v10 PLD, by loading your *.jed file into
the buffer of the programmer then programming the PLD. (Make sure that the IC is
erased first)
9. Place the programmed PLD into the breadboard of the logic trainer and connect the
inputs to switches and outputs to LEDs. Connect the clock input (pin 1) to a 1 Hz clock
signal. Demonstrate the operation of your circuit to the instructor.

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 Introduction:
Objective:
Design a circuit to count the number of ones every 3-clock period. Use
LogicAid to derive a state table, reduce the number of states, find D flip-
flop equations, and simulate the circuit in Proteus using the AM22v10 IC
to verify the state table's accuracy.

State Diagram:

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 State table:

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 D-FF Equations:

JEDEC (inputs and outputs)

and the circuit

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 Timing diagram:

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 Discussion:
• Compare the cost, design time, space of your design with a glue logic design.
• Discuss your experience in the laboratory and any problems with the procedure.
• Show the circuit for the design problem only. Include in your report.
• Make sure to include the pin numbers of the gates used.
• You do NOT have to show the package outline, just the pin numbers of the gates.
•
Discussion:
The experiment was conducted to compare the performance of two different approaches:
the glue logic design and the G22v10 design. The results indicated that when the input
values X1X0 were set to 11, the output Z2Z1Z0 was 010, representing the detection of two
ones in the input. Conversely, when X1X0 was set to 00, the output Z2Z1Z0 was 000,
indicating the absence of ones in the input.

In terms of the design process, both the glue logic and G22v10 designs were derived using
the LogicAid software, and the time required for equation derivation was equal for both
approaches. However, the glue logic design would have necessitated many different gates,
resulting in a complex and costly circuit. This complexity would have been impractical for a
bug circuit.

On the other hand, employing the G22v10 integrated circuit (IC) significantly simplified the
design process. With only 2 inputs, 3 outputs, and the G22v10 IC, the design became more
realistic and practical. Furthermore, the utilization of the IC saved space, as it had a
maximum of 6 outgoing wires.

It is noteworthy that no issues were encountered during the experiment, and the desired
results were obtained seamlessly. In conclusion, the experiment effectively demonstrated
the disparities between the glue logic design and the G22v10 design. The G22v10 design
exhibited superior efficiency, cost-effectiveness, and practicality, making it the preferred
choice for our specific requirements

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 Conclusion:

To conclude, the experiment successfully achieved its objective by investigating the

utilization of the AM22v10 IC in implementing a logic circuit. This integrated circuit is pre-
manufactured and programmable to meet the specific requirements of the circuit design.

One notable advantage of the AM22v10 IC is its space-saving feature, eliminating the need
for a complex glue logic circuit. This efficiency in space utilization is highly advantageous
and contributes to resource optimization.

Furthermore, the utilization of the AM22v10 IC simplifies the design process significantly.
Instead of constructing a circuit comprising multiple components and gates, the equations
can be formulated on a computer and directly programmed into the IC. This approach not
only saves time but also reduces the complexity and effort involved in circuit design and
implementation.

In summary, the integration of programmable SPLDs such as the AM22v10 IC offers a

streamlined and efficient approach to circuit connectivity and design. It's user-friendly
programming, space-saving attributes, and simplified implementation make it a practical
and effective choice for circuit design endeavours.

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