UEC2021142 Assignment7 MUX
UEC2021142 Assignment7 MUX
VLSI Design
Aim: Design of 2:1 MUX using Transmission gates.
Theory:
When the voltage on node A is Logic 1, the complementary Logic 0 is applied to node𝐴´,
allowing both transistors to conduct and pass the signal at IN to OUT. When the voltage on
node A is Logic 0, the complementary Logic 1 is applied to node𝐴´, turning both transistors
off and forcing a high-impedance condition on both the IN and OUT nodes. The common
circuit symbol for a transmission gate depicts the bidirectional nature of the circuit's
operation
Transmission gates are typically used as building blocks for logic circuitry, such as a
Multiplexer, D Latch or D Flip-Flop. As a stand-alone circuit, a transmission gate can isolate
a component or components from live signals during hot insertion or removal. In a security
application, they can selectively block critical signals or data from being transmitted without
proper hardware-controlled authorization.
Cummins College Of Engineering For women, Pune-52 3rd Year B-Tech E&TC
2
This circuit demonstrates the basic transmission-gate multiplexer. The idea behind this circuit
is to use two transmission-gates as simple switches to propagate either input A or input B
directly to the output. The extra inverter generates the inverse of the S select input. While the
lower transmission-gate is activated by logic 1 at select input S, the upper transmission-gate
is activated by logic 0 at the select input S, due to the wiring of their control (gate) inputs.
When select input S is low, only the upper transmission-gate is conducting (because𝑆´ is
connected to its n-channel and S to its p-channel transistor gate inputs), while the lower
transmission-gate is non-conducting. As a result, the value of X1 is passed through to the
output of the multiplexer.
When S is high, the lower transmission-gate is activated, while the upper transmission-gate is
non-conducting. Therefore, the value of X2 is passed through to the multiplexer output.
Conclusion:
We built 2:1 mux using 3 NMOS and 3 PMOS with input A and B, select line S and output Y. We can
see that with the help of select line S=0 input B is passed as output and for S=1 A is passed as output.
Assignment Questions :
1. different approaches to construct 2:1 MUX in the selected CMOS technology &
calculate the no. of transistors required.
- Total Transistors: 12 (4 nMOS, 4 pMOS for transmission gates, 2 nMOS, 2 pMOS for the
inverter).
- Components: 1 transmission gate and an inverter for generating the inverted select signal.
- Total Transistors: 8 (2 nMOS, 2 pMOS for the transmission gate, 2 nMOS, 2 pMOS for the
inverter).
Approach 2 is more transistor-efficient, requiring fewer transistors to achieve the same 2:1
MUX functionality.
3. Explain Transmission Gate & Its advantages over CMOS Inverter as a switch.
Analog/Digital Hybrid Use: Versatile for bridging analog and digital circuits effectively.