Testability of VLSI

Lecture 3: Fault Collapsing

By Dr. Sanjay Vidhyadharan

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 Functional Versus Structural Testing

𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛𝑎𝑙 𝑇𝑒𝑠𝑡
𝑇𝑒𝑠𝑡 𝑉𝑒𝑐𝑡𝑜𝑡𝑠 2129 = 6.8 ∗ 1038
𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑖𝑚𝑒 𝑤𝑖𝑡ℎ 𝐶𝑙𝑜𝑐𝑘 𝑜𝑓 1 𝐺𝐻𝑧 ≈ 22 𝑦𝑒𝑎𝑟𝑠

𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 64 ∗ (10 + 17)

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 Single Stuck-at faults

How many Fault Sites ? 3

How many Fault ?

Minimum test length for 100% SSF fault coverage ? 3

No requirement to exactly identify which fault. Entire gate is to be discarded 3

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 Delay faults

How Many Paths ? 5 paths: {AHK, BELHK, BEFJK, CELHK, CEFJK}

How Many set of test vectors ? 10 sets

Test vector to detect delay fault at F ? 001-000

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 Transistor faults

Two-pattern Tests for Stuck-open Faults

Automation available to optimize Stuck-at and Stuk-open Fault

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 Fault Detection

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 Fault Sensitization
1. Fault Sensitization: We need to choose a test vector that activates the fault site
with complementary signal

X3 =1

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 Fault Propagation
2. Fault Propagation: We need to chose a suitable path for propagate the fault to
a primary output.

G5

G4 >> G5>> z

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 Fault Justification
3. Fault Justification: We need to work from output to input to assign test vectors
to primary inputs.

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 Fault Detectability
A fault f is said to be detectable if there exists a test t that detects f ;
otherwise, f is an undetectable fault

E.g. And 3 S-a-0 is not detectable

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 Fault Coverage

Complete detection test set: A set of tests that detect any detectable faults
in a class of faults

The quality of a test set is measured by fault coverage

Fault coverage: Fraction of faults that are detected by a test set

>95% - 99.9% is typically required

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 Fault Equivalence
Fault equivalence.

1. Two faults of a Boolean circuit are called equivalent iff they transform the circuit
such that the two faulty circuits have identical output functions.

2. Equivalent faults are also called indistinguishable and have exactly

the same set of tests.
Faults f and g are functionally equivalent (or simply equivalent) if faulty outputs
of them are identical for all test patterns

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 Fault Equivalence

Input Output
A B Good A/0 B/0 C/0 A/1 B/1 C/1
0 0 0 0 0 0 1 1 1
0 1 1 1 0 0 1 1 1
1 0 1 0 0 0 1 1 1
1 1 1 1 1 0 1 1 1

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 Fault Equivalence

Input Output
A B Good A/0 B/0 C/0 A/1 B/1 C/1
0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 0 1 1
1 0 1 1 1 0 0 0 1
1 1 0 1 1 0 1 1 1

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 Fault Equivalence

Input Output
Good in/0 in/1 out/0 out/1
0 1 1 0 0 1
1 0 1 0 0 1

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 Fault Equivalence

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 Equivalence Fault Collapsing
n+2 instead of 2n+2 faults need to be
considered for an n-input gate

Why Equivalence Fault Collapsing (EFC)?

➢ Reduce number of faults so that
➢ Speed up ATPG
➢ Shorten test set ( 6 to 4 sa faults for 2 i/p gates)

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 Equivalence Fault Collapsing
EFC on Fanout-free Circuits
EFC Rules
 (1) both stuck-at one and zero faults for every primary output
 (2) one collapsed fault for each gate input

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 Equivalence Fault Collapsing

Fault collapsing reduces 18 s-a faults to 12

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 Equivalence Fault Collapsing
Fanout stem faults are NOT always equivalent to fanout branch faults

Example:
 E/0 is equivalent to F/0
 but not equivalent to L/0
 The other faults are NOT equivalent

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 Equivalence Fault Collapsing

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 Dominance Fault Collapsing
Detecting set of fault f (Tf) = set of all possible test patterns that detect fault f
Fault f dominates fault g if the detecting set of f contains that of g

For F2 Sa1 {00,01,10}

For F1 sa1
01

Fault F2 dominates fault F1

If fault F2 dominates F1, then F2 is removed from the fault list
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 Dominance Fault Collapsing

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 Dominance Fault Collapsing

g
f

𝒇↔ 𝒈↔𝒉 𝒇→ 𝒈→𝒉

[2] Video lectures by Professor James Chien-Mo Li

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 Dominance Fault Collapsing

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 Dominance Fault Collapsing

If this is passed
obviously C is
not Sa0

Input Output
A B Good A/0 B/0 C/0 A/1 B/1 C/1
0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 0 1 1
If this is
1 0 1 1 1 0 1 0 1
passed
1 1 0 1 1 0 0 0 1 obviously A
and B are is
not Sa0

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 Dominance Fault Collapsing

→ DFC 7 faults

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 Dominance Fault Collapsing

14 faults → 8 faults after EFC

→ 5 faults after DFC

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 Dominance Fault Collapsing
Fanout Stem and Branches

→ DFC 7 faults
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 Checkpoint Theorem
Primary inputs and fanout branches of a combinational circuit are called
checkpoints

Checkpoint theorem: “A test set that detects all single (multiple) stuck-at
faults on all checkpoints of a combinational circuit, also detects all single
(multiple) stuck-at faults in that circuit.”

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 Checkpoint Theorem

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 Checkpoint Theorem

Chkpt is a Simpler Alternative to EFC/DFC

DFC has issues in sequential circuits and EFC is most preferred technique
for ATPG

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 Collapse Ratio

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 Simulation for Design Verification

True-value means that the simulator will compute the response for given input stimuli without
injecting any faults in the design. The input stimuli are also based on the specification.
A frequently used strategy is to exercise all functions with only critical data patterns. This is
because the simulation of the exhaustive set of data patterns can be too expensive
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 True Value Simulation

1. A design can be first simulated at a higher behavior level (such as C).

Netlist not required
Does not contain the detailed timing information.
No electrical behavior
2, Once this design is verified, higher-level blocks are replaced by logic-level netlists.
At this point, a logic simulator is used for verification.
3. The process may be repeated by replacing some or all portions by transistor-level or
circuit-level implementations.

Simulation is used in this way for verifying very large electronic systems.

The weakness of this method is its dependence on the designer’s heuristics used
in generating the input stimuli.

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 Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder. How Many Test vectors Required?

The first seven vectors

cover all stuck-at faults.
One may, therefore, use
only the first seven vectors
in the manufacturing test.

Note: This optimization is possible because of same blocks (FA) being used
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and each test vector verifying similar faults in all blocks 36

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 Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder.

Timing analysis of 2 followed by 6 or 3 followed by 7 where carry propagates through the

chain

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 Fault simulation for test generation

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 References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

Lab. of Dependable Systems Graduate Institute of Electronics Engineering
National Taiwan University
https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-
SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

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 Thankyou

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